[OpenSPARC-T2-DV] / verif / diag / assembly / include / bootprom_init.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: bootprom_init.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#include "partial_modes.h"
bootprom_init:
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!! This section replicated from hred_reset_handler.s
!! becuse we need to run the bootprom init fom chip master
!! thread ONLY.
!
    rdhpr   %hpstate, %l1
    wrhpr   %l1, 0x820, %hpstate
    wrpr    1, %tl

    ! set hyper trap base addr
    best_set_reg(HV_TRAP_BASE_PA,  %g2, %l7)
    wrhpr %l7, %g0, %htba

    ! Doing this in delay slot of jump from boot prom ...
    !wrpr    0, %g0, %gl

    ! load core id to %g1
    ldxa    [%g0] ASI_INTR_ID, %g1      ! USING this on N2 as a shortcut

#ifndef CMP_THREAD_START
bootprom_init_non_cmp_check_master_tid:
    ! Non-cmp thread startup.
#ifndef PORTABLE_CORE
    ! If T0 then chip-master
    brz %g1, bootprom_init_master      ! T0 is chip master
    ! Else figure out if lowest running
#endif
    wr %g0,  ASI_CMP_CORE, %asi
    ldxa [0x50]%asi, %g2                ! Who is running ?
    and %g2, 1, %g3                     ! T0 IS running
    brnz %g3, bootprom_init_notmaster
    neg %g2, %l1
    xnor %g2, %l1, %l1
    popc %l1, %l1                       ! Get lowest bit set ..
    dec %l1
    cmp %l1, %g1
    be %xcc, bootprom_init_master
    srlx %g1, 3, %l1                    ! Get core-id
#else
bootprom_init_cmp_check_master_tid:
#ifndef SIXGUNS
#ifndef PORTABLE_CORE
    ! CMP thread startup   ! DONT USE %G1 until CMP IS Done
    ! Find out if current thread is chip master thread,
changequote([, ])dnl ! The M4_* variables need this
    cmp %g1, M4_master_tid
changequote(`,')dnl ! [] are not quotes anymore
#else
    andcc %g1, 0x7, %g2
#endif
#else
    ! Determine master thread by querying CORE_RUNNING
    mov 0x50, %g3
    ldxa [%g3]ASI_CMP_CORE, %g2         ! Who is running ?
    neg %g2, %l1
    xnor %g2, %l1, %l1
    popc %l1, %l1                       ! Get lowest bit set ..
    dec %l1
    cmp %l1, %g1
#endif
    be %xcc, bootprom_init_master
#endif

!!!!!!!!!End of thread check for chip master !!!!!!!!!!!!!!!!!!!

bootprom_init_notmaster:

#ifndef CMP_THREAD_START
ifelse(mpeval((HV_RED_TEXT_PA > 0xffffffff),2),1,
    `setx nc_check_core_master_thread,  %g3, %g2',
    `set nc_check_core_master_thread,  %g2')
    jmp %g2
    wr %g0,  ASI_CMP_CORE, %asi
#else
ifelse(mpeval((HV_RED_TEXT_PA > 0xffffffff),2),1,
    `setx check_core_master_thread,  %g3, %g2',
    `set check_core_master_thread,  %g2')
    jmp %g2
    wr %g0,  ASI_CMP_CORE, %asi
#endif

bootprom_init_master:
!!!!!!!!!!!! Master Thread Inits Here !!!!!!!!!!!!!!!!!!!!!!!!!!
#ifdef SYNC_SLAM_NO_SLAM
#include "ccu_defines.h"
    setx RESET_STAT, %g3, %g2
    ldx [%g2], %g3          !! read reset source
    and %g3, 2, %g3         !! nonzero if WMR
    brnz %g3, continue_por
    nop
    setx RESET_GEN, %g2, %g4
    mov  0x1, %g3 
    stx  %g3, [%g4]  !!trigger a warm reset
#endif


!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!if ccu programming is required then it is done here
!and then a warm reset is issued
#ifdef WARM_RESET_INIT
bootprom_init_check_reset_stat:
#include "ccu_defines.h"
    setx RESET_STAT, %g3, %g2
    ldx [%g2], %g3          !! read reset source
    and %g3, 2, %g3         !! nonzero if WMR
    brnz %g3, continue_por
    nop
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!program the ccu
#ifdef CCU_REG_PROG
bootprom_init_program_ccu:
    setx cregs_ccu_ctl_reg_r64, %g2, %g3
    setx PLL_CTL, %g2, %g4
    stx  %g3, [%g4]    !!store to pll_ctl reg to make freq change
#endif

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
! AT 04/12/06: Add DTM setup for PEU/PSR CSRs.

#ifdef DTM_ENABLED

#define PEU_MPY_FACTOR_DATA    0x0000000000000005
#define PEU_ILU_FACTOR_DATA    0x00000003ffff0004

#define PEU_PLL_CNTL_REG_ADDR	0x88006e2200
#define PEU_ILU_REG_ADDR	0x8800652000

! program MPY field of PEU Serdes PLL Ctrl Reg to x10
	setx PEU_MPY_FACTOR_DATA, %g1, %g4
	setx PEU_PLL_CNTL_REG_ADDR, %g1, %g2
	stx	%g4, [%g2]

! Now switch the PEU rate scale from full to half rate

	setx PEU_ILU_FACTOR_DATA, %g1, %g4
	setx PEU_ILU_REG_ADDR, %g1, %g2
	stx	%g4, [%g2]

#if defined(NO_SLAM_INIT_MCUCTL)

#ifndef MCU_CHANNEL_DATA
#define MCU_CHANNEL_DATA   0x0000000000170017
#endif

#define MCU_CHANNEL_MASK   0xffffffffff000000
#define MCU_CHANNEL_ADDR   0x84000008b8

#define SER_CONFIG_DATA	 0x0000000010000000
#define SER_CONFIG_MASK	 0xffffffffcfffffff
#define SER_CONFIG_ADDR	 0x84000008d0

	mov  0x1, %g5
	sllx %g5, 12, %g5	!! %g5 is 0x1000. MCU0/1/2/3's FBD_CHANNEL_STATE_REG is 0x1000 apart

!  Now set the channel latency in the MCU to 0x14

	setx	MCU_CHANNEL_ADDR, %g1, %g2
	setx	MCU_CHANNEL_MASK, %g1, %g4
#ifdef BANK01
	ldx	[%g2], %g1
	and	%g1, %g4, %g3
	setx	MCU_CHANNEL_DATA, %g1, %g4  !MCU_CHANNEL_DATA
	or	%g3, %g4, %g4
	stx	%g4, [%g2]
#endif
	add	%g2, %g5, %g2  !%g2 has MCU1 address
#ifndef BANK01
#ifdef BANK23
	ldx	[%g2], %g1
	and	%g1, %g4, %g3
	setx	MCU_CHANNEL_DATA, %g1, %g4  !MCU_CHANNEL_DATA
	or	%g3, %g4, %g4
#endif
#endif

#ifdef BANK23
	stx	%g4, [%g2]
#endif
	add	%g2, %g5, %g2  !%g2 has MCU2 address

#ifndef BANK01
#ifndef BANK23
#ifdef BANK45
	ldx	[%g2], %g1
	and	%g1, %g4, %g3
	setx	MCU_CHANNEL_DATA, %g1, %g4  !MCU_CHANNEL_DATA
	or	%g3, %g4, %g4
#endif
#endif
#endif

#ifdef BANK45
	stx	%g4, [%g2]
#endif
	add	%g2, %g5, %g2    !%g2 has MCU3 address

#ifndef BANK01
#ifndef BANK23
#ifndef BANK45
#ifdef BANK67
	ldx	[%g2], %g1
	and	%g1, %g4, %g3
	setx	MCU_CHANNEL_DATA, %g1, %g4  !MCU_CHANNEL_DATA
	or	%g3, %g4, %g4
#endif
#endif
#endif
#endif

#ifdef BANK67
	stx	%g4, [%g2]
#endif

! Now set the MCU serdes Configuration Register to half rate.

	setx	SER_CONFIG_ADDR, %g1, %g2
	setx	SER_CONFIG_MASK, %g1, %g4
#ifdef BANK01
	ldx	[%g2], %g1
	and	%g1, %g4, %g3
	setx	SER_CONFIG_DATA, %g1, %g4
	or	%g3, %g4, %g4
	stx	%g4, [%g2]
#endif
	add	%g2, %g5, %g2
#ifndef BANK01
#ifdef BANK23
	ldx	[%g2], %g1
	and	%g1, %g4, %g3
	setx	SER_CONFIG_DATA, %g1, %g4
	or	%g3, %g4, %g4
#endif
#endif
#ifdef BANK23
	stx	%g4, [%g2]
#endif
	add	%g2, %g5, %g2
#ifndef BANK01
#ifndef BANK23
#ifdef BANK45
	ldx	[%g2], %g1
	and	%g1, %g4, %g3
	setx	SER_CONFIG_DATA, %g1, %g4
	or	%g3, %g4, %g4
#endif
#endif
#endif
#ifdef BANK45
	stx	%g4, [%g2]
#endif
	add	%g2, %g5, %g2

#ifndef BANK01
#ifndef BANK23
#ifndef BANK45
#ifdef BANK67
	ldx	[%g2], %g1
	and	%g1, %g4, %g3
	setx	SER_CONFIG_DATA, %g1, %g4
	or	%g3, %g4, %g4
#endif
#endif
#endif
#endif
#ifdef BANK67
	stx	%g4, [%g2]
#endif

#include "boot_mcuctl_init_b4wmr.s"

#endif		
! end of ifdef NO_SLAM_INIT_MCUCTL
#endif		
! end of ifdef DTM_ENABLED

! END AT 04/12/06

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#ifdef MBIST_REG_PROG
bootprom_init_program_mbist:
#include "mbist_defines.h"
    setx MBIST_MODE, %g2, %g4
    mov  MBIST_MODE_REG, %g3
    stx  %g3, [%g4]    !!store to mbist_mode to configure mbist operation

    setx MBIST_BYPASS_REG, %g2, %g3
    setx MBIST_BYPASS, %g2, %g4
    stx  %g3, [%g4]  !!Program mbist_bypass to select engines

    setx MBIST_START_WMR, %g2, %g4
    mov  0x1, %g3
    stx  %g3, [%g4]  !!Enable MBIST operation during warm reset
#endif

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

#ifdef L2_CORE_ENABLE
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!program core enable register
bootprom_init_program_core_enable:
    ldxa [%g0]0x41, %g3
    stxa %g3, [%g0+0x20]

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!program bank enable register
bootprom_init_program_l2_bank_enable:
    setx 0x8400001018, %g2, %g3
    ldxa [%g3], %g4
    add %g3, 0x8, %g3
    stxa %g4, [%g3]
#endif

#ifdef L2_IDX_HASH_EN
bootprom_init_program_l2_hash_enable:
#include "ncu_defines.h"
    setx L2_IDX_HASH_EN_ADDR, %g2, %g3
    mov  0x1, %g4
    stx  %g4, [%g3]
#endif


!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!Progam the SSI clock ratio io2clk/4
!!system defaults to io2clk/8
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#ifdef SSI_CLK_4
bootprom_init_program_ssi_clk_4:
#include "ncu_defines.h"
   setx NCU_SCKSEL, %l2, %l1
   mov  0x1, %l2
   stx  %l2, [%l1]
#endif

#ifdef SSI_CLK_8_2
bootprom_init_program_ssi_clk_8_2:
#include "ncu_defines.h"
   setx NCU_SCKSEL, %l2, %l1
   mov  0x2, %l2
   stx  %l2, [%l1]
#endif

#ifdef SSI_CLK_8_3
bootprom_init_program_ssi_clk_8_3:
#include "ncu_defines.h"
   setx NCU_SCKSEL, %l2, %l1
   mov  0x3, %l2
   stx  %l2, [%l1]
#endif

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!Down the FBD links b4 a warm reset is given
    setx 0x8400000800, %g3, %g4    !! MCU0's FBD_CHANNEL_STATE_REG
    mov  0x1, %g5
    sllx %g5, 12, %g5     !! %g5 is 0x1000. MCU0/1/2/3's FBD_CHANNEL_STATE_REG is 0x1000 apart
    stx  %g0, [%g4]
    add  %g4, %g5, %g4
    stx  %g0, [%g4]
    add  %g4, %g5, %g4
    stx  %g0, [%g4]
    add  %g4, %g5, %g4
    stx  %g0, [%g4]

! AT 04/12/06: 	For DTM vector generation, JTAG asserts PB_RST to trigger
!		WMR1 and WMR2.	Hence, not trigger WMR here in boot code.
! 		In normal DTM runs, still want to issue the WMR.
#ifndef DTM_JTAG_POR

!Generate the warm reset
    setx RESET_GEN, %g2, %g4
    mov  0x1, %g3
    stx  %g3, [%g4]  !!trigger a warm reset
#endif /* DTM_JTAG_POR */

#endif

continue_por:
#ifndef DTM_ENABLED  /* Does not work for partial mode in DTM so removed for DTM */
        setx    0x8400000280, %g2, %g3
        ldx     [%g3], %g4
        stx     %g4, [%g3]
#endif
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!WRITE to ASI_VEC_MASK This will cause all threads started
!from now on to vector to 0000020
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#ifdef BOOT_SLAVE_THREADS_FROM_MEMORY
programm_asi_vec_mask:
mov 1, %l0
mov 0x18, %l1
stxa %l0, [%l1]0x45   !set the vec mask to 1 this should cause
                      !fetches to 0x0000 for other threads
#endif


#ifdef DTM_ENABLED
#ifdef TOGGLE_ENFTP
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!Set and release the ENFTP signal
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#define SERDES_CONFIG_ENFTP_MASK 0x80000

        setx    SER_CONFIG_ADDR, %g3, %g2
        ldx     [%g2], %g4
        setx    SERDES_CONFIG_ENFTP_MASK, %g5, %g6
        mov  0x1, %g5
        sllx %g5, 12, %g5       !! %g5 is 0x1000. MCU0/1/2/3's FBD_CHANNEL_STATE_REG is 0x1000 apart
        xor     %g6, %g4, %g4

    
        stx     %g4, [%g2]
        add     %g2, %g5, %g2
        stx     %g4, [%g2]
        add     %g2, %g5, %g2
        stx     %g4, [%g2]              
        add     %g2, %g5, %g2           
        stx     %g4, [%g2]
    
    
        setx    SER_CONFIG_ADDR, %g3, %g2 
        ldx     [%g2], %g4
        setx    SERDES_CONFIG_ENFTP_MASK, %g5, %g6
        mov  0x1, %g5
        sllx %g5, 12, %g5       !! %g5 is 0x1000. MCU0/1/2/3's FBD_CHANNEL_STATE_REG is 0x1000 apart

        xor     %g6, %g4, %g4
    
    
        stx     %g4, [%g2] 
        add     %g2, %g5, %g2
        stx     %g4, [%g2]
        add     %g2, %g5, %g2
        stx     %g4, [%g2]
        add     %g2, %g5, %g2
        stx     %g4, [%g2]
#endif /* TOGGLE_ENFTP */
#endif /* DTM_ENABLED */

!! AT 04/12/06: Add DTM setup to bypass IOMMU, also disable scrambling.
!		Note these are not wmr_protected, need to do this after WMR2.
!		Then trigger user event to train PCI-E link.

#ifdef DTM_ENABLED
#ifdef SSI_VEC_DIAG_POST_WRM_PEU

programm_peu_reg_dtm:
#define PEU_IOMMU_CNTL_REG_ADDR         0x8800640000
#define PEU_IOMMU_DATA                  0x0000000000000002

#define PEU_SYMBOL_TIMER_REG_ADDR	0x88006e2078
#define PEU_SYMBOL_TIMER_DATA		0x20

#define PEU_MAC_CTRL_REG_ADDR		0x88006e2060
#define PEU_MAC_CTRL_REG_SCRAMBLE_MASK	0xfffffffffffffffd
#define PEU_MAC_CTRL_REG_SCRAMBLE_DATA	0x0000000000000002

    setx PEU_IOMMU_DATA, %g1, %g4
    setx PEU_IOMMU_CNTL_REG_ADDR, %g1, %g2
    stx  %g4, [%g2]
    nop

! Disable scrambling so that peu_mio_debug_txdata is meaningful.
programm_peu_scrambling_reg_dtm:
    setx PEU_MAC_CTRL_REG_ADDR, %g1, %g2
    setx PEU_MAC_CTRL_REG_SCRAMBLE_MASK, %g1, %g4
    ldx [%g2], %g1
    and %g1, %g4, %g3
    setx PEU_MAC_CTRL_REG_SCRAMBLE_DATA, %g1, %g4
    or	%g3, %g4, %g4
    stx %g4, [%g2]

! Now we need to create a user event for the tester to send
! sufficent FTS order sets

! Also need  the tester to send one SKP order set
! Following user event does both

#ifdef DTM_PCI_USER_EVENT
!!!! StartDtm:
!!!!! x$EV trig_pc_d(1,expr(@VA(.RED_SEC.StartDtm)&0x0000ffffffffffff,16,16)) -> EnablePCIeIgCmd("STARTDTM", 0, 0, 0, 1)

! the above User Event does 25 FTSs and 1 SKP
#endif

#include "peu_init_dtm.h"

#endif		
! end of ifdef SSI_VEC_DIAG_POST_WRM
#endif		
! end of ifdef DTM_ENABLED


!!!! MCU Inits

!!!!!!!#if defined(NO_SLAM_INIT_MCUCTL)
#include "hboot_mcuctl_init.s"
!!!!!!!#endif


!!!! Partial Bank Enable

#ifdef BANK_SET_MASK_CSR
 ! Check bank enable status
 setx    0x8000001028, %g3, %g2
 ldx  [%g2 + 0], %l1
 sllx   %l1, 0x4, %l1
 and %l1, 1, %l1
 brnz	%l1, partial

 ! Set partial bank mode

 sub %g2, 8, %g2
 mov BANK_SET_MASK_CSR, %l1
 stx %l1, [%g2 + 0]
 stx %l1, [%g2 + 0x40]
 stx %l1, [%g2 + 0x80]
 stx %l1, [%g2 + 0xc0]
 stx %l1, [%g2 + 0x100]
 stx %l1, [%g2 + 0x140]
 stx %l1, [%g2 + 0x180]
 stx %l1, [%g2 + 0x1c0]

 ! Warm reset
 setx    0x8900000808, %g3, %g4
 mov     0x1, %g5
 stx     %g5, [%g4]

 partial:
#endif

#ifdef SSI_VEC_DIAG_POST_WRM
#include SSI_VEC_DIAG_POST_WRM
#endif


!!!!!!!!!!!! Master Thread Inits END !!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!! END OF BOOTPROM INIT    !!!!!!!!!!!!!!!!!!!!!!!!!!

#ifndef CMP_THREAD_START
ifelse(mpeval((HV_RED_TEXT_PA > 0xffffffff),2),1,
    `setx nc_chip_master_thread,  %g3, %g2',
    `set nc_chip_master_thread,  %g2')
    jmp %g2
    wr %g0,  ASI_CMP_CORE, %asi
#else
ifelse(mpeval((HV_RED_TEXT_PA > 0xffffffff),2),1,
    `setx chip_master_thread,  %g3, %g2',
    `set chip_master_thread,  %g2')
    jmp %g2
    wr %g0,  ASI_CMP_CORE, %asi
#endif

! No Code beyond this point
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: bootprom_init.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#include "partial_modes.h"
	39	bootprom_init:
	40	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	41	!! This section replicated from hred_reset_handler.s
	42	!! becuse we need to run the bootprom init fom chip master
	43	!! thread ONLY.
	44	!
	45	rdhpr %hpstate, %l1
	46	wrhpr %l1, 0x820, %hpstate
	47	wrpr 1, %tl
	48
	49	! set hyper trap base addr
	50	best_set_reg(HV_TRAP_BASE_PA, %g2, %l7)
	51	wrhpr %l7, %g0, %htba
	52
	53	! Doing this in delay slot of jump from boot prom ...
	54	!wrpr 0, %g0, %gl
	55
	56	! load core id to %g1
	57	ldxa [%g0] ASI_INTR_ID, %g1 ! USING this on N2 as a shortcut
	58
	59	#ifndef CMP_THREAD_START
	60	bootprom_init_non_cmp_check_master_tid:
	61	! Non-cmp thread startup.
	62	#ifndef PORTABLE_CORE
	63	! If T0 then chip-master
	64	brz %g1, bootprom_init_master ! T0 is chip master
65	! Else figure out if lowest running
66	#endif
67	wr %g0, ASI_CMP_CORE, %asi
68	ldxa [0x50]%asi, %g2 ! Who is running ?
69	and %g2, 1, %g3 ! T0 IS running
70	brnz %g3, bootprom_init_notmaster
71	neg %g2, %l1
72	xnor %g2, %l1, %l1
73	popc %l1, %l1 ! Get lowest bit set ..
74	dec %l1
75	cmp %l1, %g1
76	be %xcc, bootprom_init_master
77	srlx %g1, 3, %l1 ! Get core-id
78	#else
79	bootprom_init_cmp_check_master_tid:
80	#ifndef SIXGUNS
81	#ifndef PORTABLE_CORE
82	! CMP thread startup ! DONT USE %G1 until CMP IS Done
83	! Find out if current thread is chip master thread,
84	changequote([, ])dnl ! The M4_* variables need this
85	cmp %g1, M4_master_tid
86	changequote(`,')dnl ! [] are not quotes anymore
87	#else
88	andcc %g1, 0x7, %g2
89	#endif
90	#else
91	! Determine master thread by querying CORE_RUNNING
92	mov 0x50, %g3
93	ldxa [%g3]ASI_CMP_CORE, %g2 ! Who is running ?
94	neg %g2, %l1
95	xnor %g2, %l1, %l1
96	popc %l1, %l1 ! Get lowest bit set ..
97	dec %l1
98	cmp %l1, %g1
99	#endif
100	be %xcc, bootprom_init_master
101	#endif
102
103	!!!!!!!!!End of thread check for chip master !!!!!!!!!!!!!!!!!!!
104
105	bootprom_init_notmaster:
106
107	#ifndef CMP_THREAD_START
108	ifelse(mpeval((HV_RED_TEXT_PA > 0xffffffff),2),1,
109	`setx nc_check_core_master_thread, %g3, %g2',
110	`set nc_check_core_master_thread, %g2')
111	jmp %g2
112	wr %g0, ASI_CMP_CORE, %asi
113	#else
114	ifelse(mpeval((HV_RED_TEXT_PA > 0xffffffff),2),1,
115	`setx check_core_master_thread, %g3, %g2',
116	`set check_core_master_thread, %g2')
117	jmp %g2
118	wr %g0, ASI_CMP_CORE, %asi
119	#endif
120
121	bootprom_init_master:
122	!!!!!!!!!!!! Master Thread Inits Here !!!!!!!!!!!!!!!!!!!!!!!!!!
123	#ifdef SYNC_SLAM_NO_SLAM
124	#include "ccu_defines.h"
125	setx RESET_STAT, %g3, %g2
126	ldx [%g2], %g3 !! read reset source
127	and %g3, 2, %g3 !! nonzero if WMR
128	brnz %g3, continue_por
129	nop
130	setx RESET_GEN, %g2, %g4
131	mov 0x1, %g3
132	stx %g3, [%g4] !!trigger a warm reset
133	#endif
134
135
136	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
137	!if ccu programming is required then it is done here
138	!and then a warm reset is issued
139	#ifdef WARM_RESET_INIT
140	bootprom_init_check_reset_stat:
141	#include "ccu_defines.h"
142	setx RESET_STAT, %g3, %g2
143	ldx [%g2], %g3 !! read reset source
144	and %g3, 2, %g3 !! nonzero if WMR
145	brnz %g3, continue_por
146	nop
147	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
148	!program the ccu
149	#ifdef CCU_REG_PROG
150	bootprom_init_program_ccu:
151	setx cregs_ccu_ctl_reg_r64, %g2, %g3
152	setx PLL_CTL, %g2, %g4
153	stx %g3, [%g4] !!store to pll_ctl reg to make freq change
154	#endif
155
156	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
157	! AT 04/12/06: Add DTM setup for PEU/PSR CSRs.
158
159	#ifdef DTM_ENABLED
160
161	#define PEU_MPY_FACTOR_DATA 0x0000000000000005
162	#define PEU_ILU_FACTOR_DATA 0x00000003ffff0004
163
164	#define PEU_PLL_CNTL_REG_ADDR 0x88006e2200
165	#define PEU_ILU_REG_ADDR 0x8800652000
166
167	! program MPY field of PEU Serdes PLL Ctrl Reg to x10
168	setx PEU_MPY_FACTOR_DATA, %g1, %g4
169	setx PEU_PLL_CNTL_REG_ADDR, %g1, %g2
170	stx %g4, [%g2]
171
172	! Now switch the PEU rate scale from full to half rate
173
174	setx PEU_ILU_FACTOR_DATA, %g1, %g4
175	setx PEU_ILU_REG_ADDR, %g1, %g2
176	stx %g4, [%g2]
177
178	#if defined(NO_SLAM_INIT_MCUCTL)
179
180	#ifndef MCU_CHANNEL_DATA
181	#define MCU_CHANNEL_DATA 0x0000000000170017
182	#endif
183
184	#define MCU_CHANNEL_MASK 0xffffffffff000000
185	#define MCU_CHANNEL_ADDR 0x84000008b8
186
187	#define SER_CONFIG_DATA 0x0000000010000000
188	#define SER_CONFIG_MASK 0xffffffffcfffffff
189	#define SER_CONFIG_ADDR 0x84000008d0
190
191	mov 0x1, %g5
192	sllx %g5, 12, %g5 !! %g5 is 0x1000. MCU0/1/2/3's FBD_CHANNEL_STATE_REG is 0x1000 apart
193
194	! Now set the channel latency in the MCU to 0x14
195
196	setx MCU_CHANNEL_ADDR, %g1, %g2
197	setx MCU_CHANNEL_MASK, %g1, %g4
198	#ifdef BANK01
199	ldx [%g2], %g1
200	and %g1, %g4, %g3
201	setx MCU_CHANNEL_DATA, %g1, %g4 !MCU_CHANNEL_DATA
202	or %g3, %g4, %g4
203	stx %g4, [%g2]
204	#endif
205	add %g2, %g5, %g2 !%g2 has MCU1 address
206	#ifndef BANK01
207	#ifdef BANK23
208	ldx [%g2], %g1
209	and %g1, %g4, %g3
210	setx MCU_CHANNEL_DATA, %g1, %g4 !MCU_CHANNEL_DATA
211	or %g3, %g4, %g4
212	#endif
213	#endif
214
215	#ifdef BANK23
216	stx %g4, [%g2]
217	#endif
218	add %g2, %g5, %g2 !%g2 has MCU2 address
219
220	#ifndef BANK01
221	#ifndef BANK23
222	#ifdef BANK45
223	ldx [%g2], %g1
224	and %g1, %g4, %g3
225	setx MCU_CHANNEL_DATA, %g1, %g4 !MCU_CHANNEL_DATA
226	or %g3, %g4, %g4
227	#endif
228	#endif
229	#endif
230
231	#ifdef BANK45
232	stx %g4, [%g2]
233	#endif
234	add %g2, %g5, %g2 !%g2 has MCU3 address
235
236	#ifndef BANK01
237	#ifndef BANK23
238	#ifndef BANK45
239	#ifdef BANK67
240	ldx [%g2], %g1
241	and %g1, %g4, %g3
242	setx MCU_CHANNEL_DATA, %g1, %g4 !MCU_CHANNEL_DATA
243	or %g3, %g4, %g4
244	#endif
245	#endif
246	#endif
247	#endif
248
249	#ifdef BANK67
250	stx %g4, [%g2]
251	#endif
252
253	! Now set the MCU serdes Configuration Register to half rate.
254
255	setx SER_CONFIG_ADDR, %g1, %g2
256	setx SER_CONFIG_MASK, %g1, %g4
257	#ifdef BANK01
258	ldx [%g2], %g1
259	and %g1, %g4, %g3
260	setx SER_CONFIG_DATA, %g1, %g4
261	or %g3, %g4, %g4
262	stx %g4, [%g2]
263	#endif
264	add %g2, %g5, %g2
265	#ifndef BANK01
266	#ifdef BANK23
267	ldx [%g2], %g1
268	and %g1, %g4, %g3
269	setx SER_CONFIG_DATA, %g1, %g4
270	or %g3, %g4, %g4
271	#endif
272	#endif
273	#ifdef BANK23
274	stx %g4, [%g2]
275	#endif
276	add %g2, %g5, %g2
277	#ifndef BANK01
278	#ifndef BANK23
279	#ifdef BANK45
280	ldx [%g2], %g1
281	and %g1, %g4, %g3
282	setx SER_CONFIG_DATA, %g1, %g4
283	or %g3, %g4, %g4
284	#endif
285	#endif
286	#endif
287	#ifdef BANK45
288	stx %g4, [%g2]
289	#endif
290	add %g2, %g5, %g2
291
292	#ifndef BANK01
293	#ifndef BANK23
294	#ifndef BANK45
295	#ifdef BANK67
296	ldx [%g2], %g1
297	and %g1, %g4, %g3
298	setx SER_CONFIG_DATA, %g1, %g4
299	or %g3, %g4, %g4
300	#endif
301	#endif
302	#endif
303	#endif
304	#ifdef BANK67
305	stx %g4, [%g2]
306	#endif
307
308	#include "boot_mcuctl_init_b4wmr.s"
309
310	#endif
311	! end of ifdef NO_SLAM_INIT_MCUCTL
312	#endif
313	! end of ifdef DTM_ENABLED
314
315	! END AT 04/12/06
316
317	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
318	#ifdef MBIST_REG_PROG
319	bootprom_init_program_mbist:
320	#include "mbist_defines.h"
321	setx MBIST_MODE, %g2, %g4
322	mov MBIST_MODE_REG, %g3
323	stx %g3, [%g4] !!store to mbist_mode to configure mbist operation
324
325	setx MBIST_BYPASS_REG, %g2, %g3
326	setx MBIST_BYPASS, %g2, %g4
327	stx %g3, [%g4] !!Program mbist_bypass to select engines
328
329	setx MBIST_START_WMR, %g2, %g4
330	mov 0x1, %g3
331	stx %g3, [%g4] !!Enable MBIST operation during warm reset
332	#endif
333
334	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
335
336	#ifdef L2_CORE_ENABLE
337	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
338	!program core enable register
339	bootprom_init_program_core_enable:
340	ldxa [%g0]0x41, %g3
341	stxa %g3, [%g0+0x20]
342
343	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
344	!program bank enable register
345	bootprom_init_program_l2_bank_enable:
346	setx 0x8400001018, %g2, %g3
347	ldxa [%g3], %g4
348	add %g3, 0x8, %g3
349	stxa %g4, [%g3]
350	#endif
351
352	#ifdef L2_IDX_HASH_EN
353	bootprom_init_program_l2_hash_enable:
354	#include "ncu_defines.h"
355	setx L2_IDX_HASH_EN_ADDR, %g2, %g3
356	mov 0x1, %g4
357	stx %g4, [%g3]
358	#endif
359
360
361	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
362	!!Progam the SSI clock ratio io2clk/4
363	!!system defaults to io2clk/8
364	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
365	#ifdef SSI_CLK_4
366	bootprom_init_program_ssi_clk_4:
367	#include "ncu_defines.h"
368	setx NCU_SCKSEL, %l2, %l1
369	mov 0x1, %l2
370	stx %l2, [%l1]
371	#endif
372
373	#ifdef SSI_CLK_8_2
374	bootprom_init_program_ssi_clk_8_2:
375	#include "ncu_defines.h"
376	setx NCU_SCKSEL, %l2, %l1
377	mov 0x2, %l2
378	stx %l2, [%l1]
379	#endif
380
381	#ifdef SSI_CLK_8_3
382	bootprom_init_program_ssi_clk_8_3:
383	#include "ncu_defines.h"
384	setx NCU_SCKSEL, %l2, %l1
385	mov 0x3, %l2
386	stx %l2, [%l1]
387	#endif
388
389	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
390	!Down the FBD links b4 a warm reset is given
391	setx 0x8400000800, %g3, %g4 !! MCU0's FBD_CHANNEL_STATE_REG
392	mov 0x1, %g5
393	sllx %g5, 12, %g5 !! %g5 is 0x1000. MCU0/1/2/3's FBD_CHANNEL_STATE_REG is 0x1000 apart
394	stx %g0, [%g4]
395	add %g4, %g5, %g4
396	stx %g0, [%g4]
397	add %g4, %g5, %g4
398	stx %g0, [%g4]
399	add %g4, %g5, %g4
400	stx %g0, [%g4]
401
402	! AT 04/12/06: For DTM vector generation, JTAG asserts PB_RST to trigger
403	! WMR1 and WMR2. Hence, not trigger WMR here in boot code.
404	! In normal DTM runs, still want to issue the WMR.
405	#ifndef DTM_JTAG_POR
406
407	!Generate the warm reset
408	setx RESET_GEN, %g2, %g4
409	mov 0x1, %g3
410	stx %g3, [%g4] !!trigger a warm reset
411	#endif /* DTM_JTAG_POR */
412
413	#endif
414
415	continue_por:
416	#ifndef DTM_ENABLED /* Does not work for partial mode in DTM so removed for DTM */
417	setx 0x8400000280, %g2, %g3
418	ldx [%g3], %g4
419	stx %g4, [%g3]
420	#endif
421	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
422	!WRITE to ASI_VEC_MASK This will cause all threads started
423	!from now on to vector to 0000020
424	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
425	#ifdef BOOT_SLAVE_THREADS_FROM_MEMORY
426	programm_asi_vec_mask:
427	mov 1, %l0
428	mov 0x18, %l1
429	stxa %l0, [%l1]0x45 !set the vec mask to 1 this should cause
430	!fetches to 0x0000 for other threads
431	#endif
432
433
434	#ifdef DTM_ENABLED
435	#ifdef TOGGLE_ENFTP
436	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
437	!Set and release the ENFTP signal
438	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
439	#define SERDES_CONFIG_ENFTP_MASK 0x80000
440
441	setx SER_CONFIG_ADDR, %g3, %g2
442	ldx [%g2], %g4
443	setx SERDES_CONFIG_ENFTP_MASK, %g5, %g6
444	mov 0x1, %g5
445	sllx %g5, 12, %g5 !! %g5 is 0x1000. MCU0/1/2/3's FBD_CHANNEL_STATE_REG is 0x1000 apart
446	xor %g6, %g4, %g4
447
448
449	stx %g4, [%g2]
450	add %g2, %g5, %g2
451	stx %g4, [%g2]
452	add %g2, %g5, %g2
453	stx %g4, [%g2]
454	add %g2, %g5, %g2
455	stx %g4, [%g2]
456
457
458	setx SER_CONFIG_ADDR, %g3, %g2
459	ldx [%g2], %g4
460	setx SERDES_CONFIG_ENFTP_MASK, %g5, %g6
461	mov 0x1, %g5
462	sllx %g5, 12, %g5 !! %g5 is 0x1000. MCU0/1/2/3's FBD_CHANNEL_STATE_REG is 0x1000 apart
463
464	xor %g6, %g4, %g4
465
466
467	stx %g4, [%g2]
468	add %g2, %g5, %g2
469	stx %g4, [%g2]
470	add %g2, %g5, %g2
471	stx %g4, [%g2]
472	add %g2, %g5, %g2
473	stx %g4, [%g2]
474	#endif /* TOGGLE_ENFTP */
475	#endif /* DTM_ENABLED */
476
477	!! AT 04/12/06: Add DTM setup to bypass IOMMU, also disable scrambling.
478	! Note these are not wmr_protected, need to do this after WMR2.
479	! Then trigger user event to train PCI-E link.
480
481	#ifdef DTM_ENABLED
482	#ifdef SSI_VEC_DIAG_POST_WRM_PEU
483
484	programm_peu_reg_dtm:
485	#define PEU_IOMMU_CNTL_REG_ADDR 0x8800640000
486	#define PEU_IOMMU_DATA 0x0000000000000002
487
488	#define PEU_SYMBOL_TIMER_REG_ADDR 0x88006e2078
489	#define PEU_SYMBOL_TIMER_DATA 0x20
490
491	#define PEU_MAC_CTRL_REG_ADDR 0x88006e2060
492	#define PEU_MAC_CTRL_REG_SCRAMBLE_MASK 0xfffffffffffffffd
493	#define PEU_MAC_CTRL_REG_SCRAMBLE_DATA 0x0000000000000002
494
495	setx PEU_IOMMU_DATA, %g1, %g4
496	setx PEU_IOMMU_CNTL_REG_ADDR, %g1, %g2
497	stx %g4, [%g2]
498	nop
499
500	! Disable scrambling so that peu_mio_debug_txdata is meaningful.
501	programm_peu_scrambling_reg_dtm:
502	setx PEU_MAC_CTRL_REG_ADDR, %g1, %g2
503	setx PEU_MAC_CTRL_REG_SCRAMBLE_MASK, %g1, %g4
504	ldx [%g2], %g1
505	and %g1, %g4, %g3
506	setx PEU_MAC_CTRL_REG_SCRAMBLE_DATA, %g1, %g4
507	or %g3, %g4, %g4
508	stx %g4, [%g2]
509
510	! Now we need to create a user event for the tester to send
511	! sufficent FTS order sets
512
513	! Also need the tester to send one SKP order set
514	! Following user event does both
515
516	#ifdef DTM_PCI_USER_EVENT
517	!!!! StartDtm:
518	!!!!! x$EV trig_pc_d(1,expr(@VA(.RED_SEC.StartDtm)&0x0000ffffffffffff,16,16)) -> EnablePCIeIgCmd("STARTDTM", 0, 0, 0, 1)
519
520	! the above User Event does 25 FTSs and 1 SKP
521	#endif
522
523	#include "peu_init_dtm.h"
524
525	#endif
526	! end of ifdef SSI_VEC_DIAG_POST_WRM
527	#endif
528	! end of ifdef DTM_ENABLED
529
530
531	!!!! MCU Inits
532
533	!!!!!!!#if defined(NO_SLAM_INIT_MCUCTL)
534	#include "hboot_mcuctl_init.s"
535	!!!!!!!#endif
536
537
538	!!!! Partial Bank Enable
539
540	#ifdef BANK_SET_MASK_CSR
541	! Check bank enable status
542	setx 0x8000001028, %g3, %g2
543	ldx [%g2 + 0], %l1
544	sllx %l1, 0x4, %l1
545	and %l1, 1, %l1
546	brnz %l1, partial
547
548	! Set partial bank mode
549
550	sub %g2, 8, %g2
551	mov BANK_SET_MASK_CSR, %l1
552	stx %l1, [%g2 + 0]
553	stx %l1, [%g2 + 0x40]
554	stx %l1, [%g2 + 0x80]
555	stx %l1, [%g2 + 0xc0]
556	stx %l1, [%g2 + 0x100]
557	stx %l1, [%g2 + 0x140]
558	stx %l1, [%g2 + 0x180]
559	stx %l1, [%g2 + 0x1c0]
560
561	! Warm reset
562	setx 0x8900000808, %g3, %g4
563	mov 0x1, %g5
564	stx %g5, [%g4]
565
566	partial:
567	#endif
568
569	#ifdef SSI_VEC_DIAG_POST_WRM
570	#include SSI_VEC_DIAG_POST_WRM
571	#endif
572
573
574	!!!!!!!!!!!! Master Thread Inits END !!!!!!!!!!!!!!!!!!!!!!!!!!
575	!!!!!!!!!!!! END OF BOOTPROM INIT !!!!!!!!!!!!!!!!!!!!!!!!!!
576
577	#ifndef CMP_THREAD_START
578	ifelse(mpeval((HV_RED_TEXT_PA > 0xffffffff),2),1,
579	`setx nc_chip_master_thread, %g3, %g2',
580	`set nc_chip_master_thread, %g2')
581	jmp %g2
582	wr %g0, ASI_CMP_CORE, %asi
583	#else
584	ifelse(mpeval((HV_RED_TEXT_PA > 0xffffffff),2),1,
585	`setx chip_master_thread, %g3, %g2',
586	`set chip_master_thread, %g2')
587	jmp %g2
588	wr %g0, ASI_CMP_CORE, %asi
589	#endif
590
591	! No Code beyond this point