projects / OpenSPARC-T2-DV / blame
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1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: ccu_defines.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
| 39 | ! PLL_CTL 0x8300000000 | |
| 40 | ! RSVD0 63:34 | |
| 41 | ! PLL_CHAR_IN 33 | |
| 42 | ! CHANGE 32 | |
| 43 | ! ALIGN_SHIFT 31:30 | |
| 44 | ! SERDES_DTM2 29 | |
| 45 | ! SERDES_DTM1 28 | |
| 46 | ! ST_DELAY_A 27:26 | |
| 47 | ! ST_PHASE_HI 25 | |
| 48 | ! PLL_DIV4 24:18 | |
| 49 | ! PLL_DIV3 17:12 | |
| 50 | ! PLL_DIV2 11:6 | |
| 51 | ! PLL_DIV1 5:0 | |
| 52 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
| 53 | ||
| 54 | #ifndef PLL_CTL | |
| 55 | #define PLL_CTL 0x8300000000 | |
| 56 | #endif | |
| 57 | ||
| 58 | #ifndef RESET_GEN | |
| 59 | #define RESET_GEN 0x8900000808 | |
| 60 | #endif | |
| 61 | ||
| 62 | #ifndef RESET_STAT | |
| 63 | #define RESET_STAT 0x8900000810 | |
| 64 | #endif | |
| 65 | ||
| 66 | #ifdef CMPDR_RATIO_2_00 | |
| 67 | #define PLL_DIV1 0x1 | |
| 68 | #define PLL_DIV2 0x7 | |
| 69 | #define PLL_DIV3 0x1 | |
| 70 | #define PLL_DIV4 0x8 | |
| 71 | #define CHANGE 0x1 | |
| 72 | #endif | |
| 73 | ||
| 74 | #ifdef CMPDR_RATIO_2_25 | |
| 75 | #define PLL_DIV1 0x1 | |
| 76 | #define PLL_DIV2 0x8 | |
| 77 | #define PLL_DIV3 0x1 | |
| 78 | #define PLL_DIV4 0x9 | |
| 79 | #define CHANGE 0x1 | |
| 80 | #endif | |
| 81 | ||
| 82 | #ifdef CMPDR_RATIO_2_50 | |
| 83 | #define PLL_DIV1 0x1 | |
| 84 | #define PLL_DIV2 0x9 | |
| 85 | #define PLL_DIV3 0x1 | |
| 86 | #define PLL_DIV4 0xa | |
| 87 | #define CHANGE 0x1 | |
| 88 | #endif | |
| 89 | ||
| 90 | #ifdef CMPDR_RATIO_2_75 | |
| 91 | #define PLL_DIV1 0x1 | |
| 92 | #define PLL_DIV2 0xa | |
| 93 | #define PLL_DIV3 0x1 | |
| 94 | #define PLL_DIV4 0xb | |
| 95 | #define CHANGE 0x1 | |
| 96 | #endif | |
| 97 | ||
| 98 | #ifdef CMPDR_RATIO_3_00 | |
| 99 | #define PLL_DIV1 0x1 | |
| 100 | #define PLL_DIV2 0xb | |
| 101 | #define PLL_DIV3 0x1 | |
| 102 | #define PLL_DIV4 0xc | |
| 103 | #define CHANGE 0x1 | |
| 104 | #endif | |
| 105 | ||
| 106 | #ifdef CMPDR_RATIO_3_25 | |
| 107 | #define PLL_DIV1 0x1 | |
| 108 | #define PLL_DIV2 0xc | |
| 109 | #define PLL_DIV3 0x1 | |
| 110 | #define PLL_DIV4 0xd | |
| 111 | #define CHANGE 0x1 | |
| 112 | #endif | |
| 113 | ||
| 114 | #ifdef CMPDR_RATIO_3_50 | |
| 115 | #define PLL_DIV1 0x1 | |
| 116 | #define PLL_DIV2 0xd | |
| 117 | #define PLL_DIV3 0x1 | |
| 118 | #define PLL_DIV4 0xe | |
| 119 | #define CHANGE 0x1 | |
| 120 | #endif | |
| 121 | ||
| 122 | #ifdef CMPDR_RATIO_3_75 | |
| 123 | #define PLL_DIV1 0x1 | |
| 124 | #define PLL_DIV2 0xe | |
| 125 | #define PLL_DIV3 0x1 | |
| 126 | #define PLL_DIV4 0xf | |
| 127 | #define CHANGE 0x1 | |
| 128 | #endif | |
| 129 | ||
| 130 | #ifdef CMPDR_RATIO_4_00 | |
| 131 | #define PLL_DIV1 0x1 | |
| 132 | #define PLL_DIV2 0xf | |
| 133 | #define PLL_DIV3 0x1 | |
| 134 | #define PLL_DIV4 0x10 | |
| 135 | #define CHANGE 0x1 | |
| 136 | #endif | |
| 137 | ||
| 138 | #ifdef CMPDR_RATIO_4_25 | |
| 139 | #define PLL_DIV1 0x1 | |
| 140 | #define PLL_DIV2 0x10 | |
| 141 | #define PLL_DIV3 0x1 | |
| 142 | #define PLL_DIV4 0x11 | |
| 143 | #define CHANGE 0x1 | |
| 144 | #endif | |
| 145 | ||
| 146 | #ifdef CMPDR_RATIO_4_50 | |
| 147 | #define PLL_DIV1 0x1 | |
| 148 | #define PLL_DIV2 0x11 | |
| 149 | #define PLL_DIV3 0x1 | |
| 150 | #define PLL_DIV4 0x12 | |
| 151 | #define CHANGE 0x1 | |
| 152 | #endif | |
| 153 | ||
| 154 | ! AT 04/12/06: DTM Clock Ratios | |
| 155 | ||
| 156 | #ifdef CMPDR_RATIO_15 | |
| 157 | #define PLL_DIV1 0x0 | |
| 158 | #define PLL_DIV2 0xE | |
| 159 | #define PLL_DIV3 0x1 | |
| 160 | #define PLL_DIV4 0x0 | |
| 161 | #define CHANGE 0x1 | |
| 162 | #endif | |
| 163 | ||
| 164 | #ifdef CMPDR_RATIO_11 | |
| 165 | #define PLL_DIV1 0x0 | |
| 166 | #define PLL_DIV2 0xA | |
| 167 | #define PLL_DIV3 0x1 | |
| 168 | #define PLL_DIV4 0x0 | |
| 169 | #define CHANGE 0x1 | |
| 170 | #endif | |
| 171 | ||
| 172 | #ifdef CMPDR_RATIO_8 | |
| 173 | #define PLL_DIV1 0x0 | |
| 174 | #define PLL_DIV2 0x7 | |
| 175 | #define PLL_DIV3 0x1 | |
| 176 | #define PLL_DIV4 0x0 | |
| 177 | #define CHANGE 0x1 | |
| 178 | #endif | |
| 179 | ! END AT 04/12/06 | |
| 180 | ||
| 181 | #ifdef CHANGE | |
| 182 | #define WARM_RESET_INIT 1 | |
| 183 | #define CCU_REG_PROG 1 | |
| 184 | #endif | |
| 185 | ||
| 186 | #ifndef PLL_DIV1 | |
| 187 | #define PLL_DIV1 1 | |
| 188 | #endif | |
| 189 | ||
| 190 | #ifndef PLL_DIV2 | |
| 191 | #define PLL_DIV2 7 | |
| 192 | #endif | |
| 193 | ||
| 194 | #ifndef PLL_DIV3 | |
| 195 | #define PLL_DIV3 1 | |
| 196 | #endif | |
| 197 | ||
| 198 | #ifndef PLL_DIV4 | |
| 199 | #define PLL_DIV4 8 | |
| 200 | #endif | |
| 201 | ||
| 202 | #ifndef ST_PHASE_HI | |
| 203 | #define ST_PHASE_HI 0 | |
| 204 | #endif | |
| 205 | ||
| 206 | #ifndef ST_DELAY_A | |
| 207 | #define ST_DELAY_A 0 | |
| 208 | #endif | |
| 209 | ||
| 210 | #ifndef SERDES_DTM1 | |
| 211 | ! AT 04/12/06 | |
| 212 | #ifndef DTM_ENABLED | |
| 213 | #define SERDES_DTM1 0 | |
| 214 | #else | |
| 215 | #define SERDES_DTM1 1 | |
| 216 | #endif | |
| 217 | #endif | |
| 218 | ||
| 219 | #ifndef SERDES_DTM2 | |
| 220 | ! AT 04/12/06 | |
| 221 | #ifndef DTM_ENABLED | |
| 222 | #define SERDES_DTM2 0 | |
| 223 | #else | |
| 224 | #define SERDES_DTM2 1 | |
| 225 | #endif | |
| 226 | #endif | |
| 227 | ||
| 228 | #ifndef ALIGN_SHIFT | |
| 229 | #define ALIGN_SHIFT 0 | |
| 230 | #endif | |
| 231 | ||
| 232 | #ifndef CHANGE | |
| 233 | #define CHANGE 1 | |
| 234 | #endif | |
| 235 | ||
| 236 | #ifndef PLL_CHAR_IN | |
| 237 | #define PLL_CHAR_IN 0 | |
| 238 | #endif | |
| 239 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
| 240 | ! PLL_CTL 0x8300000000 | |
| 241 | ! RSVD0 63:34 | |
| 242 | ! PLL_CHAR_IN 33 | |
| 243 | ! CHANGE 32 | |
| 244 | ! ALIGN_SHIFT 31:30 | |
| 245 | ! SERDES_DTM2 29 | |
| 246 | ! SERDES_DTM1 28 | |
| 247 | ! ST_DELAY_A 27:26 | |
| 248 | ! ST_PHASE_HI 25 | |
| 249 | ! PLL_DIV4 24:18 | |
| 250 | ! PLL_DIV3 17:12 | |
| 251 | ! PLL_DIV2 11:6 | |
| 252 | ! PLL_DIV1 5:0 | |
| 253 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
| 254 | ||
| 255 | #ifndef CREGS_CCU_CTL_REG_R64 | |
| 256 | #define CREGS_CCU_CTL_REG_R64 (\ | |
| 257 | (PLL_DIV1) | (PLL_DIV2 << 6) | (PLL_DIV3 << 12) | (PLL_DIV4 << 18) |\ | |
| 258 | (ST_PHASE_HI << 25) | (ST_DELAY_A << 26) | (SERDES_DTM1 << 28) |\ | |
| 259 | (SERDES_DTM2 << 29) | (ALIGN_SHIFT << 30) | (CHANGE << 32) |\ | |
| 260 | (PLL_CHAR_IN << 33)) | |
| 261 | #endif | |
| 262 | ||
| 263 | define(cregs_ccu_ctl_reg_r64, `0x'dnl | |
| 264 | mpeval(CREGS_CCU_CTL_REG_R64, 16, 8)) |