projects / OpenSPARC-T2-DV / blame
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1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: dmaept_defines.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #include "peu_defines.h" | |
| 39 | ||
| 40 | #define DMAEPT_ENG1 0x100 | |
| 41 | #define DMAEPT_ENG2 0x200 | |
| 42 | #define DMAEPT_ENG3 0x300 | |
| 43 | #define DMAEPT_ENG4 0x400 | |
| 44 | ||
| 45 | #define DMAEPT_DATA_ADDR_UPPER 0x00 | |
| 46 | #define DMAEPT_DATA_ADDR_LOWER 0x04 | |
| 47 | #define DMAEPT_PATTERN 0x08 | |
| 48 | #define DMAEPT_ENDING_INTERRUPT 0x0C | |
| 49 | #define DMAEPT_OPERATION 0x10 | |
| 50 | #define DMAEPT_MAX_PYLD 0x2C | |
| 51 | #define DMAEPT_TAG 0x28 | |
| 52 | #define DMAEPT_INTERRUPT_ACK 0x24 | |
| 53 | #define DMAEPT_STATUS 0x14 | |
| 54 | #define DMAEPT_DATA_MSCMPR_OFFSET 0x18 | |
| 55 | #define DMAEPT_DATA_MSCMPR_VALUE_UPPER 0x1C | |
| 56 | #define DMAEPT_DATA_MSCMPR_VALUE_LOWER 0x20 | |
| 57 | #define DMAEPT_MSI_ADDR_UPPER 0x30 | |
| 58 | #define DMAEPT_MSI_ADDR_LOWER 0x34 | |
| 59 | #define DMAEPT_MSI_DATA 0x38 | |
| 60 | ||
| 61 | #define DMAEPT_INTERRUPT_ACK_INTA eval(1 << 3) | |
| 62 | #define DMAEPT_INTERRUPT_ACK_INTB eval(1 << 2) | |
| 63 | #define DMAEPT_INTERRUPT_ACK_INTC eval(1 << 1) | |
| 64 | #define DMAEPT_INTERRUPT_ACK_INTD eval(1 << 0) | |
| 65 | ||
| 66 | #define DMAEPT_ENDING_INTERRUPT_NONE eval(0 << 16) | |
| 67 | #define DMAEPT_ENDING_INTERRUPT_INTA eval(1 << 16) | |
| 68 | #define DMAEPT_ENDING_INTERRUPT_INTB eval(2 << 16) | |
| 69 | #define DMAEPT_ENDING_INTERRUPT_INTC eval(3 << 16) | |
| 70 | #define DMAEPT_ENDING_INTERRUPT_INTD eval(4 << 16) | |
| 71 | #define DMAEPT_ENDING_INTERRUPT_MSI eval(5 << 16) | |
| 72 | ||
| 73 | #define DMAEPT_OPERATION_MR eval(1 << 24) | |
| 74 | #define DMAEPT_OPERATION_MW eval(2 << 24) | |
| 75 | ||
| 76 | #define CFG0_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA) | |
| 77 | #define CFG0_CMDSTS_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA + 0x04) | |
| 78 | #define CFG0_BAR0_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA + 0x10) | |
| 79 | #define CFG0_BAR1_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA + 0x14) | |
| 80 | #define CFG0_BAR2_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA + 0x18) | |
| 81 | #define CFG0_BAR3_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA + 0x1c) | |
| 82 | #define CFG0_BAR4_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA + 0x20) | |
| 83 | #define CFG0_BAR5_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA + 0x24) | |
| 84 | ||
| 85 | #define DMAEPT_BAR0 0x00000000 | |
| 86 | #define DMAEPT_MEM_SIZE 0x20000 | |
| 87 | #ifdef BOBO_USE_MEM32 | |
| 88 | /* Below should be 0xc100000000 - PART0_BASE + DMAEPT_BAR2 for mem 32 PCI-E accesses */ | |
| 89 | #define BOBO_PA 0xbf00020000 | |
| 90 | #else | |
| 91 | /* Below should be 0xc800000000 - PART0_BASE + DMAEPT_BAR0 for mem 64 PCI-E accesses */ | |
| 92 | #define BOBO_PA 0xc600000000 | |
| 93 | #endif |