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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: enable_file.h | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define POWERON_RESET_ENABLE 0x1 | |
39 | #define WATCHDOG_RESET_ENABLE 0x1 | |
40 | #define EXTERNAL_RESET_ENABLE 0x1 | |
41 | #define SOFTWARE_RESET_ENABLE 0x1 | |
42 | #define REDMODE_ENABLE 0x1 | |
43 | #define RESERVED0_ENABLE 0x1 | |
44 | #define RESERVED1_ENABLE 0x1 | |
45 | #define INSTRUCTION_ACCESS_EXCEPTION_ENABLE 0x1 | |
46 | #define IA_MMU_MISS_ENABLE 0x1 | |
47 | #define INSTRUCTION_ACCESS_ERROR_ENABLE 0x1 | |
48 | #define RESERVED2_ENABLE 0x1 | |
49 | #define RESERVED3_ENABLE 0x1 | |
50 | #define RESERVED4_ENABLE 0x1 | |
51 | #define RESERVED5_ENABLE 0x1 | |
52 | #define RESERVED6_ENABLE 0x1 | |
53 | #define ENABLE_T0_Reserved_0x01 | |
54 | #define ENABLE_HT0_Reserved_0x01 | |
55 | #define ENABLE_T0_Reserved_0x02 | |
56 | #define ENABLE_HT0_Watchdog_Reset_0x02 | |
57 | #define ENABLE_T0_Reserved_0x03 | |
58 | #define ENABLE_HT0_Reserved_0x03 | |
59 | #define ENABLE_T0_Reserved_0x04 | |
60 | #define ENABLE_HT0_Reserved_0x04 | |
61 | #define ENABLE_T0_Reserved_0x05 | |
62 | #define ENABLE_HT0_Reserved_0x05 | |
63 | #define ENABLE_T0_Reserved_0x06 | |
64 | #define ENABLE_HT0_Reserved_0x06 | |
65 | #define ENABLE_T0_Reserved_0x07 | |
66 | #define ENABLE_HT0_Store_Error_0x07 | |
67 | #define ENABLE_T0_Instruction_access_exception_0x08 | |
68 | #define ENABLE_HT0_IAE_privilege_violation_0x08 | |
69 | #define ENABLE_T0_Instruction_Access_MMU_Miss_0x09 | |
70 | #define ENABLE_HT0_Instruction_Access_MMU_Miss_0x09 | |
71 | #define ENABLE_T0_Instruction_access_error_0x0a | |
72 | #define ENABLE_HT0_Instruction_access_error_0x0a | |
73 | #define ENABLE_T0_Reserved_0x0b | |
74 | #define ENABLE_HT0_IAE_unauth_access_0x0b | |
75 | #define ENABLE_T0_Reserved_0x0c | |
76 | #define ENABLE_HT0_IAE_nfo_page_0x0c | |
77 | #define ENABLE_T0_Reserved_0x0d | |
78 | #define ENABLE_HT0_Instruction_access_range_0x0d | |
79 | #define ENABLE_T0_Reserved_0x0e | |
80 | #define ENABLE_HT0_Reserved_0x0e | |
81 | #define ENABLE_T0_Reserved_0x0f | |
82 | #define ENABLE_HT0_Reserved_0x0f | |
83 | #define ENABLE_T0_Illegal_instruction_0x10 | |
84 | #define ENABLE_HT0_Illegal_instruction_0x10 | |
85 | #define ENABLE_T0_Privileged_opcode_0x11 | |
86 | #define ENABLE_HT0_Privileged_opcode_0x11 | |
87 | #define ENABLE_T0_Unimplemented_LDD_0x12 | |
88 | #define ENABLE_HT0_Unimplemented_LDD_0x12 | |
89 | #define ENABLE_T0_Unimplemented_STD_0x13 | |
90 | #define ENABLE_HT0_Unimplemented_STD_0x13 | |
91 | #define ENABLE_T0_Reserved_0x14 | |
92 | #define ENABLE_HT0_DAE_invalid_asi_0x14 | |
93 | #define ENABLE_T0_Reserved_0x15 | |
94 | #define ENABLE_HT0_DAE_privilege_violation_0x15 | |
95 | #define ENABLE_T0_Reserved_0x16 | |
96 | #define ENABLE_HT0_DAE_nc_page_0x16 | |
97 | #define ENABLE_T0_Reserved_0x17 | |
98 | #define ENABLE_HT0_DAE_nfo_page_0x17 | |
99 | #define ENABLE_T0_Reserved_0x18 | |
100 | #define ENABLE_HT0_Reserved_0x18 | |
101 | #define ENABLE_T0_Reserved_0x19 | |
102 | #define ENABLE_HT0_Reserved_0x19 | |
103 | #define ENABLE_T0_Reserved_0x1a | |
104 | #define ENABLE_HT0_Reserved_0x1a | |
105 | #define ENABLE_T0_Reserved_0x1b | |
106 | #define ENABLE_HT0_Reserved_0x1b | |
107 | #define ENABLE_T0_Reserved_0x1c | |
108 | #define ENABLE_HT0_Reserved_0x1c | |
109 | #define ENABLE_T0_Reserved_0x1d | |
110 | #define ENABLE_HT0_Reserved_0x1d | |
111 | #define ENABLE_T0_Reserved_0x1e | |
112 | #define ENABLE_HT0_Reserved_0x1e | |
113 | #define ENABLE_T0_Reserved_0x1f | |
114 | #define ENABLE_HT0_Reserved_0x1f | |
115 | #define ENABLE_T0_Fp_disabled_0x20 | |
116 | #define ENABLE_HT0_Fp_disabled_0x20 | |
117 | #define ENABLE_T0_Fp_exception_ieee_754_0x21 | |
118 | #define ENABLE_HT0_Fp_exception_ieee_754_0x21 | |
119 | #define ENABLE_T0_Fp_exception_other_0x22 | |
120 | #define ENABLE_HT0_Fp_exception_other_0x22 | |
121 | #define ENABLE_T0_Tag_Overflow_0x23 | |
122 | #define ENABLE_HT0_Tag_Overflow_0x23 | |
123 | #define ENABLE_T0_Clean_Window_0x24 | |
124 | #define ENABLE_HT0_Clean_Window_0x24 | |
125 | #define ENABLE_T0_Division_By_Zero_0x28 | |
126 | #define ENABLE_HT0_Division_By_Zero_0x28 | |
127 | #define ENABLE_T0_Reserved_0x29 | |
128 | #define ENABLE_HT0_Reserved_0x29 | |
129 | #define ENABLE_T0_Reserved_0x2a | |
130 | #define ENABLE_HT0_Instruction_Invalid_TSB_Entry_0x2a | |
131 | #define ENABLE_T0_Reserved_0x2b | |
132 | #define ENABLE_HT0_Data_Invalid_TSB_Entry_0x2b | |
133 | #define ENABLE_T0_Reserved_0x2c | |
134 | #define ENABLE_HT0_Reserved_0x2c | |
135 | #define ENABLE_T0_Reserved_0x2d | |
136 | #define ENABLE_HT0_Reserved_0x2d | |
137 | #define ENABLE_T0_Reserved_0x2e | |
138 | #define ENABLE_HT0_mem_address_range_0x2e | |
139 | #define ENABLE_T0_Reserved_0x2f | |
140 | #define ENABLE_HT0_Reserved_0x2f | |
141 | #define ENABLE_T0_Data_Access_Exception_0x30 | |
142 | #define ENABLE_HT0_DAE_so_page_0x30 | |
143 | #define ENABLE_T0_Reserved_0x31 | |
144 | #define ENABLE_HT0_Reserved_0x31 | |
145 | #define ENABLE_T0_Data_access_error_0x32 | |
146 | #define ENABLE_HT0_Data_access_error_0x32 | |
147 | #define ENABLE_T0_Reserved_0x33 | |
148 | #define ENABLE_HT0_Reserved_0x33 | |
149 | #define ENABLE_T0_Mem_Address_Not_Aligned_0x34 | |
150 | #define ENABLE_HT0_Mem_Address_Not_Aligned_0x34 | |
151 | #define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35 | |
152 | #define ENABLE_HT0_Lddf_Mem_Address_Not_Aligned_0x35 | |
153 | #define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36 | |
154 | #define ENABLE_HT0_Stdf_Mem_Address_Not_Aligned_0x36 | |
155 | #define ENABLE_T0_Privileged_Action_0x37 | |
156 | #define ENABLE_HT0_Privileged_Action_0x37 | |
157 | #define ENABLE_T0_Reserved_0x38 | |
158 | #define ENABLE_HT0_Reserved_0x38 | |
159 | #define ENABLE_T0_Reserved_0x39 | |
160 | #define ENABLE_HT0_Reserved_0x39 | |
161 | #define ENABLE_T0_Reserved_0x3a | |
162 | #define ENABLE_HT0_Reserved_0x3a | |
163 | #define ENABLE_T0_Reserved_0x3b | |
164 | #define ENABLE_HT0_Reserved_0x3b | |
165 | #define ENABLE_T0_Reserved_0x3c | |
166 | #define ENABLE_HT0_Control_Word_Queue_Interrupt_0x3c | |
167 | #define ENABLE_T0_Reserved_0x3d | |
168 | #define ENABLE_HT0_Modular_Arithmetic_Interrupt_0x3d | |
169 | #define ENABLE_T0_Reserved_0x3e | |
170 | #define ENABLE_HT0_Reserved_0x3e | |
171 | #define ENABLE_T0_Reserved_0x3f | |
172 | #define ENABLE_HT0_Reserved_0x3f | |
173 | #define ENABLE_T0_Reserved_0x40 | |
174 | #define ENABLE_HT0_Sw_Recoverable_Error_0x40 | |
175 | #define ENABLE_T0_Interrupt_Level_1_0x41 | |
176 | #define ENABLE_HT0_Interrupt_Level_1_0x41 | |
177 | #define ENABLE_T0_Interrupt_Level_2_0x42 | |
178 | #define ENABLE_HT0_Interrupt_Level_2_0x42 | |
179 | #define ENABLE_T0_Interrupt_Level_3_0x43 | |
180 | #define ENABLE_HT0_Interrupt_Level_3_0x43 | |
181 | #define ENABLE_T0_Interrupt_Level_4_0x44 | |
182 | #define ENABLE_HT0_Interrupt_Level_4_0x44 | |
183 | #define ENABLE_T0_Interrupt_Level_5_0x45 | |
184 | #define ENABLE_HT0_Interrupt_Level_5_0x45 | |
185 | #define ENABLE_T0_Interrupt_Level_6_0x46 | |
186 | #define ENABLE_HT0_Interrupt_Level_6_0x46 | |
187 | #define ENABLE_T0_Interrupt_Level_7_0x47 | |
188 | #define ENABLE_HT0_Interrupt_Level_7_0x47 | |
189 | #define ENABLE_T0_Interrupt_Level_8_0x48 | |
190 | #define ENABLE_HT0_Interrupt_Level_8_0x48 | |
191 | #define ENABLE_T0_Interrupt_Level_9_0x49 | |
192 | #define ENABLE_HT0_Interrupt_Level_9_0x49 | |
193 | #define ENABLE_T0_Interrupt_Level_10_0x4a | |
194 | #define ENABLE_HT0_Interrupt_Level_10_0x4a | |
195 | #define ENABLE_T0_Interrupt_Level_11_0x4b | |
196 | #define ENABLE_HT0_Interrupt_Level_11_0x4b | |
197 | #define ENABLE_T0_Interrupt_Level_12_0x4c | |
198 | #define ENABLE_HT0_Interrupt_Level_12_0x4c | |
199 | #define ENABLE_T0_Interrupt_Level_13_0x4d | |
200 | #define ENABLE_HT0_Interrupt_Level_13_0x4d | |
201 | #define ENABLE_T0_Interrupt_Level_14_0x4e | |
202 | #define ENABLE_HT0_Interrupt_Level_14_0x4e | |
203 | #define ENABLE_T0_Interrupt_Level_15_0x4f | |
204 | #define ENABLE_HT0_Interrupt_Level_15_0x4f | |
205 | #define ENABLE_T0_Reserved_0x50 | |
206 | #define ENABLE_HT0_Reserved_0x50 | |
207 | #define ENABLE_T0_Reserved_0x51 | |
208 | #define ENABLE_HT0_Reserved_0x51 | |
209 | #define ENABLE_T0_Reserved_0x52 | |
210 | #define ENABLE_HT0_Reserved_0x52 | |
211 | #define ENABLE_T0_Reserved_0x53 | |
212 | #define ENABLE_HT0_Reserved_0x53 | |
213 | #define ENABLE_T0_Reserved_0x54 | |
214 | #define ENABLE_HT0_Reserved_0x54 | |
215 | #define ENABLE_T0_Reserved_0x55 | |
216 | #define ENABLE_HT0_Reserved_0x55 | |
217 | #define ENABLE_T0_Reserved_0x56 | |
218 | #define ENABLE_HT0_Reserved_0x56 | |
219 | #define ENABLE_T0_Reserved_0x57 | |
220 | #define ENABLE_HT0_Reserved_0x57 | |
221 | #define ENABLE_T0_Reserved_0x58 | |
222 | #define ENABLE_HT0_Reserved_0x58 | |
223 | #define ENABLE_T0_Reserved_0x59 | |
224 | #define ENABLE_HT0_Reserved_0x59 | |
225 | #define ENABLE_T0_Reserved_0x5a | |
226 | #define ENABLE_HT0_Reserved_0x5a | |
227 | #define ENABLE_T0_Reserved_0x5b | |
228 | #define ENABLE_HT0_Reserved_0x5b | |
229 | #define ENABLE_T0_Reserved_0x5c | |
230 | #define ENABLE_HT0_Reserved_0x5c | |
231 | #define ENABLE_T0_Reserved_0x5d | |
232 | #define ENABLE_HT0_Reserved_0x5d | |
233 | #define ENABLE_T0_Reserved_0x5e | |
234 | #define ENABLE_HT0_Hstick_Match_0x5e | |
235 | #define ENABLE_T0_Reserved_0x5f | |
236 | #define ENABLE_HT0_Trap_Level_Zero_0x5f | |
237 | #define ENABLE_T0_Interrupt_0x60 | |
238 | #define ENABLE_HT0_Interrupt_0x60 | |
239 | #define ENABLE_T0_Reserved_0x61 | |
240 | #define ENABLE_HT0_PA_Watchpoint_0x61 | |
241 | #define ENABLE_T0_VA_Watchpoint_0x62 | |
242 | #define ENABLE_HT0_VA_Watchpoint_0x62 | |
243 | #define ENABLE_T0_fast_instr_access_MMU_miss_0x64 | |
244 | #define ENABLE_HT0_fast_instr_access_MMU_miss_0x64 | |
245 | #define ENABLE_T0_fast_data_access_MMU_miss_0x68 | |
246 | #define ENABLE_HT0_fast_data_access_MMU_miss_0x68 | |
247 | #define ENABLE_T0_data_access_protection_0x6c | |
248 | #define ENABLE_HT0_data_access_protection_0x6c | |
249 | #define ENABLE_T0_Window_Spill_0_Normal_0x80 | |
250 | #define ENABLE_HT0_Window_Spill_0_Normal_0x80 | |
251 | #define ENABLE_T0_Window_Spill_1_Normal_0x84 | |
252 | #define ENABLE_HT0_Window_Spill_1_Normal_0x84 | |
253 | #define ENABLE_T0_Window_Spill_2_Normal_0x88 | |
254 | #define ENABLE_HT0_Window_Spill_2_Normal_0x88 | |
255 | #define ENABLE_T0_Window_Spill_3_Normal_0x8c | |
256 | #define ENABLE_HT0_Window_Spill_3_Normal_0x8c | |
257 | #define ENABLE_T0_Window_Spill_4_Normal_0x90 | |
258 | #define ENABLE_HT0_Window_Spill_4_Normal_0x90 | |
259 | #define ENABLE_T0_Window_Spill_5_Normal_0x94 | |
260 | #define ENABLE_HT0_Window_Spill_5_Normal_0x94 | |
261 | #define ENABLE_T0_Window_Spill_6_Normal_0x98 | |
262 | #define ENABLE_HT0_Window_Spill_6_Normal_0x98 | |
263 | #define ENABLE_T0_Window_Spill_7_Normal_0x9c | |
264 | #define ENABLE_HT0_Window_Spill_7_Normal_0x9c | |
265 | #define ENABLE_T0_Window_Spill_0_Other_0xa0 | |
266 | #define ENABLE_HT0_Window_Spill_0_Other_0xa0 | |
267 | #define ENABLE_T0_Window_Spill_1_Other_0xa4 | |
268 | #define ENABLE_HT0_Window_Spill_1_Other_0xa4 | |
269 | #define ENABLE_T0_Window_Spill_2_Other_0xa8 | |
270 | #define ENABLE_HT0_Window_Spill_2_Other_0xa8 | |
271 | #define ENABLE_T0_Window_Spill_3_Other_0xac | |
272 | #define ENABLE_HT0_Window_Spill_3_Other_0xac | |
273 | #define ENABLE_T0_Window_Spill_4_Other_0xb0 | |
274 | #define ENABLE_HT0_Window_Spill_4_Other_0xb0 | |
275 | #define ENABLE_T0_Window_Spill_5_Other_0xb4 | |
276 | #define ENABLE_HT0_Window_Spill_5_Other_0xb4 | |
277 | #define ENABLE_T0_Window_Spill_6_Other_0xb8 | |
278 | #define ENABLE_HT0_Window_Spill_6_Other_0xb8 | |
279 | #define ENABLE_T0_Window_Spill_7_Other_0xbc | |
280 | #define ENABLE_HT0_Window_Spill_7_Other_0xbc | |
281 | #define ENABLE_T0_Window_Fill_0_Normal_0xc0 | |
282 | #define ENABLE_HT0_Window_Fill_0_Normal_0xc0 | |
283 | #define ENABLE_T0_Window_Fill_1_Normal_0xc4 | |
284 | #define ENABLE_HT0_Window_Fill_1_Normal_0xc4 | |
285 | #define ENABLE_T0_Window_Fill_2_Normal_0xc8 | |
286 | #define ENABLE_HT0_Window_Fill_2_Normal_0xc8 | |
287 | #define ENABLE_T0_Window_Fill_3_Normal_0xcc | |
288 | #define ENABLE_HT0_Window_Fill_3_Normal_0xcc | |
289 | #define ENABLE_T0_Window_Fill_4_Normal_0xd0 | |
290 | #define ENABLE_HT0_Window_Fill_4_Normal_0xd0 | |
291 | #define ENABLE_T0_Window_Fill_5_Normal_0xd4 | |
292 | #define ENABLE_HT0_Window_Fill_5_Normal_0xd4 | |
293 | #define ENABLE_T0_Window_Fill_6_Normal_0xd8 | |
294 | #define ENABLE_HT0_Window_Fill_6_Normal_0xd8 | |
295 | #define ENABLE_T0_Window_Fill_7_Normal_0xdc | |
296 | #define ENABLE_HT0_Window_Fill_7_Normal_0xdc | |
297 | #define ENABLE_T0_Window_Fill_0_Other_0xe0 | |
298 | #define ENABLE_HT0_Window_Fill_0_Other_0xe0 | |
299 | #define ENABLE_T0_Window_Fill_1_Other_0xe4 | |
300 | #define ENABLE_HT0_Window_Fill_1_Other_0xe4 | |
301 | #define ENABLE_T0_Window_Fill_2_Other_0xe8 | |
302 | #define ENABLE_HT0_Window_Fill_2_Other_0xe8 | |
303 | #define ENABLE_T0_Window_Fill_3_Other_0xec | |
304 | #define ENABLE_HT0_Window_Fill_3_Other_0xec | |
305 | #define ENABLE_T0_Window_Fill_4_Other_0xf0 | |
306 | #define ENABLE_HT0_Window_Fill_4_Other_0xf0 | |
307 | #define ENABLE_T0_Window_Fill_5_Other_0xf4 | |
308 | #define ENABLE_HT0_Window_Fill_5_Other_0xf4 | |
309 | #define ENABLE_T0_Window_Fill_6_Other_0xf8 | |
310 | #define ENABLE_HT0_Window_Fill_6_Other_0xf8 | |
311 | #define ENABLE_T0_Window_Fill_7_Other_0xfc | |
312 | #define ENABLE_HT0_Window_Fill_7_Other_0xfc | |
313 | #define PRIVILEGED_OPCODE_ENABLE 0x1 | |
314 | #define UNIMPLEMENTED_LDD_ENABLE 0x1 | |
315 | #define UNIMPLEMENTED_STD_ENABLE 0x1 | |
316 | #define RESERVED7_ENABLE 0x1 | |
317 | #define RESERVED8_ENABLE 0x1 | |
318 | #define RESERVED9_ENABLE 0x1 | |
319 | #define RESERVED10_ENABLE 0x1 | |
320 | #define RESERVED11_ENABLE 0x1 | |
321 | #define RESERVED12_ENABLE 0x1 | |
322 | #define RESERVED13_ENABLE 0x1 | |
323 | #define RESERVED14_ENABLE 0x1 | |
324 | #define RESERVED15_ENABLE 0x1 | |
325 | #define RESERVED16_ENABLE 0x1 | |
326 | #define RESERVED17_ENABLE 0x1 | |
327 | #define RESERVED18_ENABLE 0x1 | |
328 | #define FP_DISABLED_ENABLE 0x1 | |
329 | #define FP_IEEE_754_ENABLE 0x1 | |
330 | #define FP_EXCP_OTHER_ENABLE 0x1 | |
331 | #define TAG_OVERFLOW_ENABLE 0x1 | |
332 | #define CLEAN_WIN_ENABLE 0x1 | |
333 | #define DIV_ZERO_ENABLE 0x1 | |
334 | #define INT_PROC_ERROR_ENABLE 0x1 | |
335 | #define RESERVED19_ENABLE 0x1 | |
336 | #define RESERVED20_ENABLE 0x1 | |
337 | #define RESERVED21_ENABLE 0x1 | |
338 | #define RESERVED22_ENABLE 0x1 | |
339 | #define RESERVED23_ENABLE 0x1 | |
340 | #define RESERVED24_ENABLE 0x1 | |
341 | #define DATA_ACCESS_EXCEPTION_ENABLE 0x1 | |
342 | #define DA_MMU_MISS_ENABLE 0x1 | |
343 | #define DATA_ACCESS_ERROR_ENABLE 0x1 | |
344 | #define DATA_PROT_ENABLE 0x1 | |
345 | #define MEM_NONALIGNED_ENABLE 0x1 | |
346 | #define LDDF_MEM_NONALIGNED_ENABLE 0x1 | |
347 | #define STDF_MEM_NONALIGNED_ENABLE 0x1 | |
348 | #define PRIVILEGED_ACTION_ENABLE 0x1 | |
349 | #define LDQF_MEM_NONALIGNED_ENABLE 0x1 | |
350 | #define STQF_MEM_NONALIGNED_ENABLE 0x1 | |
351 | #define RESERVED25_ENABLE 0x1 | |
352 | #define RESERVED26_ENABLE 0x1 | |
353 | #define RESERVED27_ENABLE 0x1 | |
354 | #define RESERVED28_ENABLE 0x1 | |
355 | #define RESERVED29_ENABLE 0x1 | |
356 | #define RESERVED30_ENABLE 0x1 | |
357 | #define ASYNC_DATA_ERROR_ENABLE 0x1 | |
358 | #define INTERRUPT_LEVEL_1_ENABLE 0x1 | |
359 | #define INTERRUPT_LEVEL_2_ENABLE 0x1 | |
360 | #define INTERRUPT_LEVEL_3_ENABLE 0x1 | |
361 | #define INTERRUPT_LEVEL_4_ENABLE 0x1 | |
362 | #define INTERRUPT_LEVEL_5_ENABLE 0x1 | |
363 | #define INTERRUPT_LEVEL_6_ENABLE 0x1 | |
364 | #define INTERRUPT_LEVEL_7_ENABLE 0x1 | |
365 | #define INTERRUPT_LEVEL_8_ENABLE 0x1 | |
366 | #define INTERRUPT_LEVEL_9_ENABLE 0x1 | |
367 | #define INTERRUPT_LEVEL_10_ENABLE 0x1 | |
368 | #define INTERRUPT_LEVEL_11_ENABLE 0x1 | |
369 | #define INTERRUPT_LEVEL_12_ENABLE 0x1 | |
370 | #define INTERRUPT_LEVEL_13_ENABLE 0x1 | |
371 | #define INTERRUPT_LEVEL_14_ENABLE 0x1 | |
372 | #define INTERRUPT_LEVEL_15_ENABLE 0x1 | |
373 | #define RESERVED31_ENABLE 0x1 | |
374 | #define RESERVED32_ENABLE 0x1 | |
375 | #define RESERVED33_ENABLE 0x1 | |
376 | #define RESERVED34_ENABLE 0x1 | |
377 | #define RESERVED35_ENABLE 0x1 | |
378 | #define RESERVED36_ENABLE 0x1 | |
379 | #define RESERVED37_ENABLE 0x1 | |
380 | #define RESERVED38_ENABLE 0x1 | |
381 | #define RESERVED39_ENABLE 0x1 | |
382 | #define RESERVED40_ENABLE 0x1 | |
383 | #define RESERVED41_ENABLE 0x1 | |
384 | #define RESERVED42_ENABLE 0x1 | |
385 | #define RESERVED43_ENABLE 0x1 | |
386 | #define RESERVED44_ENABLE 0x1 | |
387 | #define RESERVED45_ENABLE 0x1 | |
388 | #define RESERVED46_ENABLE 0x1 | |
389 | #define IMPL_DEP_XCPN_0_ENABLE 0x1 | |
390 | #define PA_WATCHPOINT_ENABLE 0x1 | |
391 | #define VA_WATCHPOINT_ENABLE 0x1 | |
392 | #define IA_FAST_MMU_MISS_ENABLE 0x1 | |
393 | #define DA_FAST_MMU_MISS_ENABLE 0x1 | |
394 | #define FAST_DATA_PROT_ENABLE 0x1 | |
395 | #define SPILL_0_NORMAL_ENABLE 0x1 | |
396 | #define SPILL_1_NORMAL_ENABLE 0x1 | |
397 | #define SPILL_2_NORMAL_ENABLE 0x1 | |
398 | #define SPILL_3_NORMAL_ENABLE 0x1 | |
399 | #define SPILL_4_NORMAL_ENABLE 0x1 | |
400 | #define SPILL_5_NORMAL_ENABLE 0x1 | |
401 | #define SPILL_6_NORMAL_ENABLE 0x1 | |
402 | #define SPILL_7_NORMAL_ENABLE 0x1 | |
403 | #define SPILL_0_OTHER_ENABLE 0x1 | |
404 | #define SPILL_1_OTHER_ENABLE 0x1 | |
405 | #define SPILL_2_OTHER_ENABLE 0x1 | |
406 | #define SPILL_3_OTHER_ENABLE 0x1 | |
407 | #define SPILL_4_OTHER_ENABLE 0x1 | |
408 | #define SPILL_5_OTHER_ENABLE 0x1 | |
409 | #define SPILL_6_OTHER_ENABLE 0x1 | |
410 | #define SPILL_7_OTHER_ENABLE 0x1 | |
411 | #define FILL_0_NORMAL_ENABLE 0x1 | |
412 | #define FILL_1_NORMAL_ENABLE 0x1 | |
413 | #define FILL_2_NORMAL_ENABLE 0x1 | |
414 | #define FILL_3_NORMAL_ENABLE 0x1 | |
415 | #define FILL_4_NORMAL_ENABLE 0x1 | |
416 | #define FILL_5_NORMAL_ENABLE 0x1 | |
417 | #define FILL_6_NORMAL_ENABLE 0x1 | |
418 | #define FILL_7_NORMAL_ENABLE 0x1 | |
419 | #define FILL_0_OTHER_ENABLE 0x1 | |
420 | #define FILL_1_OTHER_ENABLE 0x1 | |
421 | #define FILL_2_OTHER_ENABLE 0x1 | |
422 | #define FILL_3_OTHER_ENABLE 0x1 | |
423 | #define FILL_4_OTHER_ENABLE 0x1 | |
424 | #define FILL_5_OTHER_ENABLE 0x1 | |
425 | #define FILL_6_OTHER_ENABLE 0x1 | |
426 | #define FILL_7_OTHER_ENABLE 0x1 | |
427 | #define TICC_256_ENABLE 0x1 | |
428 | #define TICC_257_ENABLE 0x1 | |
429 | #define TICC_258_ENABLE 0x1 | |
430 | #define TICC_259_ENABLE 0x1 | |
431 | #define TICC_260_ENABLE 0x1 | |
432 | #define TICC_261_ENABLE 0x1 | |
433 | #define TICC_262_ENABLE 0x1 | |
434 | #define TICC_263_ENABLE 0x1 | |
435 | #define TICC_264_ENABLE 0x1 | |
436 | #define TICC_265_ENABLE 0x1 | |
437 | #define TICC_266_ENABLE 0x1 | |
438 | #define TICC_267_ENABLE 0x1 | |
439 | #define TICC_268_ENABLE 0x1 | |
440 | #define TICC_269_ENABLE 0x1 | |
441 | #define TICC_270_ENABLE 0x1 | |
442 | #define TICC_271_ENABLE 0x1 | |
443 | #define TICC_272_ENABLE 0x1 | |
444 | #define TICC_273_ENABLE 0x1 | |
445 | #define TICC_274_ENABLE 0x1 | |
446 | #define TICC_275_ENABLE 0x1 | |
447 | #define TICC_276_ENABLE 0x1 | |
448 | #define TICC_277_ENABLE 0x1 | |
449 | #define TICC_278_ENABLE 0x1 | |
450 | #define TICC_279_ENABLE 0x1 | |
451 | #define TICC_280_ENABLE 0x1 | |
452 | #define TICC_281_ENABLE 0x1 | |
453 | #define TICC_282_ENABLE 0x1 | |
454 | #define TICC_283_ENABLE 0x1 | |
455 | #define TICC_284_ENABLE 0x1 | |
456 | #define TICC_285_ENABLE 0x1 | |
457 | #define TICC_286_ENABLE 0x1 | |
458 | #define TICC_287_ENABLE 0x1 | |
459 | #define TICC_288_ENABLE 0x1 | |
460 | #define TICC_289_ENABLE 0x1 | |
461 | #define TICC_290_ENABLE 0x1 | |
462 | #define TICC_291_ENABLE 0x1 | |
463 | #define TICC_292_ENABLE 0x1 | |
464 | #define TICC_293_ENABLE 0x1 | |
465 | #define TICC_294_ENABLE 0x1 | |
466 | #define TICC_295_ENABLE 0x1 | |
467 | #define TICC_296_ENABLE 0x1 | |
468 | #define TICC_297_ENABLE 0x1 | |
469 | #define TICC_298_ENABLE 0x1 | |
470 | #define TICC_299_ENABLE 0x1 | |
471 | #define TICC_300_ENABLE 0x1 | |
472 | #define TICC_301_ENABLE 0x1 | |
473 | #define TICC_302_ENABLE 0x1 | |
474 | #define TICC_303_ENABLE 0x1 | |
475 | #define TICC_304_ENABLE 0x1 | |
476 | #define TICC_305_ENABLE 0x1 | |
477 | #define TICC_306_ENABLE 0x1 | |
478 | #define TICC_307_ENABLE 0x1 | |
479 | #define TICC_308_ENABLE 0x1 | |
480 | #define TICC_309_ENABLE 0x1 | |
481 | #define TICC_310_ENABLE 0x1 | |
482 | #define TICC_311_ENABLE 0x1 | |
483 | #define TICC_312_ENABLE 0x1 | |
484 | #define TICC_313_ENABLE 0x1 | |
485 | #define TICC_314_ENABLE 0x1 | |
486 | #define TICC_315_ENABLE 0x1 | |
487 | #define TICC_316_ENABLE 0x1 | |
488 | #define TICC_317_ENABLE 0x1 | |
489 | #define TICC_318_ENABLE 0x1 | |
490 | #define TICC_319_ENABLE 0x1 | |
491 | #define TICC_320_ENABLE 0x1 | |
492 | #define TICC_321_ENABLE 0x1 | |
493 | #define TICC_322_ENABLE 0x1 | |
494 | #define TICC_323_ENABLE 0x1 | |
495 | #define TICC_324_ENABLE 0x1 | |
496 | #define TICC_325_ENABLE 0x1 | |
497 | #define TICC_326_ENABLE 0x1 | |
498 | #define TICC_327_ENABLE 0x1 | |
499 | #define TICC_328_ENABLE 0x1 | |
500 | #define TICC_329_ENABLE 0x1 | |
501 | #define TICC_330_ENABLE 0x1 | |
502 | #define TICC_331_ENABLE 0x1 | |
503 | #define TICC_332_ENABLE 0x1 | |
504 | #define TICC_333_ENABLE 0x1 | |
505 | #define TICC_334_ENABLE 0x1 | |
506 | #define TICC_335_ENABLE 0x1 | |
507 | #define TICC_336_ENABLE 0x1 | |
508 | #define TICC_337_ENABLE 0x1 | |
509 | #define TICC_338_ENABLE 0x1 | |
510 | #define TICC_339_ENABLE 0x1 | |
511 | #define TICC_340_ENABLE 0x1 | |
512 | #define TICC_341_ENABLE 0x1 | |
513 | #define TICC_342_ENABLE 0x1 | |
514 | #define TICC_343_ENABLE 0x1 | |
515 | #define TICC_344_ENABLE 0x1 | |
516 | #define TICC_345_ENABLE 0x1 | |
517 | #define TICC_346_ENABLE 0x1 | |
518 | #define TICC_347_ENABLE 0x1 | |
519 | #define TICC_348_ENABLE 0x1 | |
520 | #define TICC_349_ENABLE 0x1 | |
521 | #define TICC_350_ENABLE 0x1 | |
522 | #define TICC_351_ENABLE 0x1 | |
523 | #define TICC_352_ENABLE 0x1 | |
524 | #define TICC_353_ENABLE 0x1 | |
525 | #define TICC_354_ENABLE 0x1 | |
526 | #define TICC_355_ENABLE 0x1 | |
527 | #define TICC_356_ENABLE 0x1 | |
528 | #define TICC_357_ENABLE 0x1 | |
529 | #define TICC_358_ENABLE 0x1 | |
530 | #define TICC_359_ENABLE 0x1 | |
531 | #define TICC_360_ENABLE 0x1 | |
532 | #define TICC_361_ENABLE 0x1 | |
533 | #define TICC_362_ENABLE 0x1 | |
534 | #define TICC_363_ENABLE 0x1 | |
535 | #define TICC_364_ENABLE 0x1 | |
536 | #define TICC_365_ENABLE 0x1 | |
537 | #define TICC_366_ENABLE 0x1 | |
538 | #define TICC_367_ENABLE 0x1 | |
539 | #define TICC_368_ENABLE 0x1 | |
540 | #define TICC_369_ENABLE 0x1 | |
541 | #define TICC_370_ENABLE 0x1 | |
542 | #define TICC_371_ENABLE 0x1 | |
543 | #define TICC_372_ENABLE 0x1 | |
544 | #define TICC_373_ENABLE 0x1 | |
545 | #define TICC_374_ENABLE 0x1 | |
546 | #define TICC_375_ENABLE 0x1 | |
547 | #define TICC_376_ENABLE 0x1 | |
548 | #define TICC_377_ENABLE 0x1 | |
549 | #define TICC_378_ENABLE 0x1 | |
550 | #define TICC_379_ENABLE 0x1 | |
551 | #define TICC_380_ENABLE 0x1 | |
552 | #define TICC_381_ENABLE 0x1 | |
553 | #define TICC_382_ENABLE 0x1 | |
554 | #define TICC_383_ENABLE 0x1 | |
555 | ||
556 | #define ENABLE_HT0_Trap_Instruction_134 0x1 | |
557 | ||
558 | #define H_T0_PThreadMutexLock_0x110 | |
559 | #define My_T0_PThreadMutexLock_0x110 \ | |
560 | done ; \ | |
561 | nop |