projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
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| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: err_defines.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #ifndef __ERR_DEFINES_H__ | |
| 39 | #define __ERR_DEFINES_H__ | |
| 40 | ||
| 41 | #ifndef ERR_INJ_IMDU | |
| 42 | ||
| 43 | #define ERR_INJ_IMDU 0 | |
| 44 | #endif | |
| 45 | ||
| 46 | #ifndef ERR_INJ_IMTU | |
| 47 | #define ERR_INJ_IMTU 0 | |
| 48 | #endif | |
| 49 | ||
| 50 | #ifndef ERR_INJ_DMDU | |
| 51 | #define ERR_INJ_DMDU 0 | |
| 52 | #endif | |
| 53 | ||
| 54 | #ifndef ERR_INJ_DMTU | |
| 55 | #define ERR_INJ_DMTU 0 | |
| 56 | #endif | |
| 57 | ||
| 58 | #ifndef ERR_INJ_IRFU | |
| 59 | #define ERR_INJ_IRFU 0 | |
| 60 | #endif | |
| 61 | ||
| 62 | #ifndef ERR_INJ_FRFU | |
| 63 | #define ERR_INJ_FRFU 0 | |
| 64 | #endif | |
| 65 | ||
| 66 | #ifndef ERR_INJ_SCAU | |
| 67 | #define ERR_INJ_SCAU 0 | |
| 68 | #endif | |
| 69 | ||
| 70 | #ifndef ERR_INJ_TCCU | |
| 71 | #define ERR_INJ_TCCU 0 | |
| 72 | #endif | |
| 73 | ||
| 74 | #ifndef ERR_INJ_TSAU | |
| 75 | #define ERR_INJ_TSAU 0 | |
| 76 | #endif | |
| 77 | ||
| 78 | #ifndef ERR_INJ_MRAU | |
| 79 | #define ERR_INJ_MRAU 0 | |
| 80 | #endif | |
| 81 | ||
| 82 | #ifndef ERR_INJ_STAU | |
| 83 | #define ERR_INJ_STAU 0 | |
| 84 | #endif | |
| 85 | ||
| 86 | #ifndef ERR_INJ_STDU | |
| 87 | #define ERR_INJ_STDU 0 | |
| 88 | #endif | |
| 89 | ||
| 90 | #ifndef ERR_INJ_ECCMASK | |
| 91 | #define ERR_INJ_ECCMASK 0x00 | |
| 92 | #endif | |
| 93 | ||
| 94 | #ifndef ERR_INJ_ENB | |
| 95 | #define ERR_INJ_ENB (\ | |
| 96 | ERR_INJ_STDU | ERR_INJ_STAU | ERR_INJ_MRAU | ERR_INJ_TSAU | ERR_INJ_TCCU |\ | |
| 97 | ERR_INJ_SCAU | ERR_INJ_FRFU | ERR_INJ_IRFU |\ | |
| 98 | ERR_INJ_DMTU | ERR_INJ_DMDU | ERR_INJ_IMTU | ERR_INJ_IMDU) | |
| 99 | ||
| 100 | #endif | |
| 101 | ||
| 102 | #ifndef ERR_INJ_REG_DATA | |
| 103 | #define ERR_INJ_REG_DATA (\ | |
| 104 | ERR_INJ_ECCMASK | (ERR_INJ_STDU << 17) | (ERR_INJ_STAU << 19) |\ | |
| 105 | (ERR_INJ_MRAU << 20) | (ERR_INJ_TSAU << 21) | (ERR_INJ_TCCU << 22) |\ | |
| 106 | (ERR_INJ_SCAU << 23) | (ERR_INJ_FRFU << 24) | (ERR_INJ_IRFU << 25) |\ | |
| 107 | (ERR_INJ_DMTU << 26) | (ERR_INJ_DMDU << 27) | (ERR_INJ_IMTU << 28) |\ | |
| 108 | (ERR_INJ_IMDU << 29) | (ERR_INJ_ENB << 31)) | |
| 109 | #endif | |
| 110 | ||
| 111 | #ifndef CERER_CWQL2ND | |
| 112 | #define CERER_CWQL2ND 0 | |
| 113 | #endif | |
| 114 | ||
| 115 | #ifndef CERER_CWQL2U | |
| 116 | #define CERER_CWQL2U 0 | |
| 117 | #endif | |
| 118 | ||
| 119 | #ifndef CERER_CWQL2C | |
| 120 | #define CERER_CWQL2C 0 | |
| 121 | #endif | |
| 122 | ||
| 123 | #ifndef CERER_MAL2ND | |
| 124 | #define CERER_MAL2ND 0 | |
| 125 | #endif | |
| 126 | ||
| 127 | #ifndef CERER_MAL2U | |
| 128 | #define CERER_MAL2U 0 | |
| 129 | #endif | |
| 130 | ||
| 131 | #ifndef CERER_MAL2C | |
| 132 | #define CERER_MAL2C 0 | |
| 133 | #endif | |
| 134 | ||
| 135 | #ifndef CERER_TCCU | |
| 136 | #define CERER_TCCU 0 | |
| 137 | #endif | |
| 138 | ||
| 139 | #ifndef CERER_TCCD | |
| 140 | #define CERER_TCCD 0 | |
| 141 | #endif | |
| 142 | ||
| 143 | #ifndef CERER_MAMU | |
| 144 | #define CERER_MAMU 0 | |
| 145 | #endif | |
| 146 | ||
| 147 | #ifndef CERER_SBDPU_SBDIOU | |
| 148 | #define CERER_SBDPU_SBDIOU 0 | |
| 149 | #endif | |
| 150 | ||
| 151 | #ifndef CERER_SBDPC | |
| 152 | #define CERER_SBDPC 0 | |
| 153 | #endif | |
| 154 | ||
| 155 | #ifndef CERER_DCDP | |
| 156 | #define CERER_DCDP 0 | |
| 157 | #endif | |
| 158 | ||
| 159 | #ifndef CERER_DCTM | |
| 160 | #define CERER_DCTM 0 | |
| 161 | #endif | |
| 162 | ||
| 163 | #ifndef CERER_DCTP | |
| 164 | #define CERER_DCTP 0 | |
| 165 | #endif | |
| 166 | ||
| 167 | #ifndef CERER_DCVP | |
| 168 | #define CERER_DCVP 0 | |
| 169 | #endif | |
| 170 | ||
| 171 | #ifndef CERER_ICDP | |
| 172 | #define CERER_ICDP 0 | |
| 173 | #endif | |
| 174 | ||
| 175 | #ifndef CERER_ICTM | |
| 176 | #define CERER_ICTM 0 | |
| 177 | #endif | |
| 178 | ||
| 179 | #ifndef CERER_ICTP | |
| 180 | #define CERER_ICTP 0 | |
| 181 | #endif | |
| 182 | ||
| 183 | #ifndef CERER_ICVP | |
| 184 | #define CERER_ICVP 0 | |
| 185 | #endif | |
| 186 | ||
| 187 | #ifndef CERER_L2ND | |
| 188 | #define CERER_L2ND 0 | |
| 189 | #endif | |
| 190 | ||
| 191 | #ifndef CERER_L2U | |
| 192 | #define CERER_L2U 0 | |
| 193 | #endif | |
| 194 | ||
| 195 | #ifndef CERER_L2C | |
| 196 | #define CERER_L2C 0 | |
| 197 | #endif | |
| 198 | ||
| 199 | #ifndef CERER_SBAPP | |
| 200 | #define CERER_SBAPP 0 | |
| 201 | #endif | |
| 202 | ||
| 203 | #ifndef CERER_TCUP | |
| 204 | #define CERER_TCUP 0 | |
| 205 | #endif | |
| 206 | ||
| 207 | #ifndef CERER_TCCP | |
| 208 | #define CERER_TCCP 0 | |
| 209 | #endif | |
| 210 | ||
| 211 | #ifndef CERER_SCAU | |
| 212 | #define CERER_SCAU 0 | |
| 213 | #endif | |
| 214 | ||
| 215 | #ifndef CERER_SCAC | |
| 216 | #define CERER_SCAC 0 | |
| 217 | #endif | |
| 218 | ||
| 219 | #ifndef CERER_TSAU | |
| 220 | #define CERER_TSAU 0 | |
| 221 | #endif | |
| 222 | ||
| 223 | #ifndef CERER_TSAC | |
| 224 | #define CERER_TSAC 0 | |
| 225 | #endif | |
| 226 | ||
| 227 | #ifndef CERER_MRAU | |
| 228 | #define CERER_MRAU 0 | |
| 229 | #endif | |
| 230 | ||
| 231 | #ifndef CERER_SBDLU | |
| 232 | #define CERER_SBDLU 0 | |
| 233 | #endif | |
| 234 | ||
| 235 | #ifndef CERER_SBDLC | |
| 236 | #define CERER_SBDLC 0 | |
| 237 | #endif | |
| 238 | ||
| 239 | #ifndef CERER_DCL2ND | |
| 240 | #define CERER_DCL2ND 0 | |
| 241 | #endif | |
| 242 | ||
| 243 | #ifndef CERER_DCL2U | |
| 244 | #define CERER_DCL2U 0 | |
| 245 | #endif | |
| 246 | ||
| 247 | #ifndef CERER_DCL2C | |
| 248 | #define CERER_DCL2C 0 | |
| 249 | #endif | |
| 250 | ||
| 251 | #ifndef CERER_DTDP | |
| 252 | #define CERER_DTDP 0 | |
| 253 | #endif | |
| 254 | ||
| 255 | #ifndef CERER_DTTM | |
| 256 | #define CERER_DTTM 0 | |
| 257 | #endif | |
| 258 | ||
| 259 | #ifndef CERER_DTTP | |
| 260 | #define CERER_DTTP 0 | |
| 261 | #endif | |
| 262 | ||
| 263 | #ifndef CERER_FRF | |
| 264 | #define CERER_FRF 0 | |
| 265 | #endif | |
| 266 | ||
| 267 | #ifndef CERER_IRF | |
| 268 | #define CERER_IRF 0 | |
| 269 | #endif | |
| 270 | ||
| 271 | #ifndef CERER_ICL2ND | |
| 272 | #define CERER_ICL2ND 0 | |
| 273 | #endif | |
| 274 | ||
| 275 | #ifndef CERER_ICL2U | |
| 276 | #define CERER_ICL2U 0 | |
| 277 | #endif | |
| 278 | ||
| 279 | #ifndef CERER_ICL2C | |
| 280 | #define CERER_ICL2C 0 | |
| 281 | #endif | |
| 282 | ||
| 283 | #ifndef CERER_HWTWL2 | |
| 284 | #define CERER_HWTWL2 0 | |
| 285 | #endif | |
| 286 | ||
| 287 | #ifndef CERER_HWTWMU | |
| 288 | #define CERER_HWTWMU 0 | |
| 289 | #endif | |
| 290 | ||
| 291 | #ifndef CERER_ITTM | |
| 292 | #define CERER_ITTM 0 | |
| 293 | #endif | |
| 294 | ||
| 295 | #ifndef CERER_ITDP | |
| 296 | #define CERER_ITDP 0 | |
| 297 | #endif | |
| 298 | ||
| 299 | #ifndef CERER_ITTP | |
| 300 | #define CERER_ITTP 0 | |
| 301 | #endif | |
| 302 | ||
| 303 | #define CERER_ENB (\ | |
| 304 | CERER_CWQL2ND | CERER_CWQL2U | CERER_CWQL2C |\ | |
| 305 | CERER_MAL2ND | CERER_MAL2U | CERER_MAL2C |\ | |
| 306 | CERER_TCCU | CERER_TCCD | CERER_MAMU |\ | |
| 307 | CERER_SBDPU_SBDIOU | CERER_SBDPC | CERER_DCDP |\ | |
| 308 | CERER_DCTM | CERER_DCTP | CERER_DCVP |\ | |
| 309 | CERER_ICDP | CERER_ICTM | CERER_ICTP |\ | |
| 310 | CERER_ICVP | CERER_L2ND | CERER_L2U |\ | |
| 311 | CERER_L2C | CERER_SBAPP | CERER_TCUP |\ | |
| 312 | CERER_TCCP | CERER_SCAU | CERER_SCAC |\ | |
| 313 | CERER_TSAU | CERER_TSAC | CERER_MRAU |\ | |
| 314 | CERER_SBDLU | CERER_SBDLC | CERER_DCL2ND |\ | |
| 315 | CERER_DCL2U | CERER_DCL2C | CERER_DTDP |\ | |
| 316 | CERER_DTTM | CERER_DTTP | CERER_FRF |\ | |
| 317 | CERER_IRF | CERER_ICL2ND | CERER_ICL2U |\ | |
| 318 | CERER_ICL2C | CERER_HWTWL2 | CERER_HWTWMU |\ | |
| 319 | CERER_ITTM | CERER_ITDP | CERER_ITTP) | |
| 320 | ||
| 321 | #if (CERER_ENB == 0x0) | |
| 322 | #define CERER_DATA 0xecf5c1f3f8bfffff | |
| 323 | #else | |
| 324 | #define CERER_DATA (\ | |
| 325 | CERER_CWQL2ND | (CERER_CWQL2U << 1) | (CERER_CWQL2C << 2) |\ | |
| 326 | (CERER_MAL2ND << 3) | (CERER_MAL2U << 4) | (CERER_MAL2C << 5) |\ | |
| 327 | (CERER_TCCU << 6) | (CERER_TCCD << 7) | (CERER_MAMU << 8) |\ | |
| 328 | (CERER_SBDPU_SBDIOU << 9) | (CERER_SBDPC << 10) | (CERER_DCDP << 11) |\ | |
| 329 | (CERER_DCTM << 12) | (CERER_DCTP << 13) | (CERER_DCVP << 14) |\ | |
| 330 | (CERER_ICDP << 15) | (CERER_ICTM << 16) | (CERER_ICTP << 17) |\ | |
| 331 | (CERER_ICVP << 18) | (CERER_L2ND << 19) | (CERER_L2U << 20) |\ | |
| 332 | (CERER_L2C << 21) | (CERER_SBAPP << 23) | (CERER_TCUP << 27) |\ | |
| 333 | (CERER_TCCP << 28) | (CERER_SCAU << 29) | (CERER_SCAC << 30) |\ | |
| 334 | (CERER_TSAU << 31) | (CERER_TSAC << 32) | (CERER_MRAU << 33) |\ | |
| 335 | (CERER_SBDLU << 36) | (CERER_SBDLC << 37) | (CERER_DCL2ND << 38) |\ | |
| 336 | (CERER_DCL2U << 39) | (CERER_DCL2C << 40) | (CERER_DTDP << 46) |\ | |
| 337 | (CERER_DTTM << 47) | (CERER_DTTP << 48) | (CERER_FRF << 50) |\ | |
| 338 | (CERER_IRF << 52) | (CERER_ICL2ND << 53) | (CERER_ICL2U << 54) |\ | |
| 339 | (CERER_ICL2C << 55) | (CERER_HWTWL2 << 58) | (CERER_HWTWMU << 59) |\ | |
| 340 | (CERER_ITTM << 61) | (CERER_ITDP << 62) | (CERER_ITTP << 63)) | |
| 341 | #endif | |
| 342 | ||
| 343 | ||
| 344 | ||
| 345 | #ifndef CETER_PSCCE | |
| 346 | #define CETER_PSCCE 1 | |
| 347 | #endif | |
| 348 | ||
| 349 | #ifndef CETER_DE | |
| 350 | #define CETER_DE 1 | |
| 351 | #endif | |
| 352 | ||
| 353 | #ifndef CETER_DHCCE | |
| 354 | #define CETER_DHCCE 1 | |
| 355 | #endif | |
| 356 | ||
| 357 | #ifndef CETER_DATA | |
| 358 | #define CETER_DATA (\ | |
| 359 | CETER_DHCCE | (CETER_DE << 1) | (CETER_PSCCE << 2)) | |
| 360 | #endif | |
| 361 | ||
| 362 | #ifdef INC_SOC_ERR_TRAPS | |
| 363 | #define H_HT0_Sw_Recoverable_Error_0x40 Soc_Recoverable_Sw_error_trap | |
| 364 | #define H_HT0_Hw_Corrected_Error_0x63 Soc_Corrected_Hw_error_trap | |
| 365 | #define H_HT0_Data_access_error_0x32 Soc_Precise_data_access_error_trap | |
| 366 | #endif | |
| 367 | ||
| 368 | ||
| 369 | #ifdef INC_ERR_TRAPS | |
| 370 | #define H_HT0_Instruction_Access_MMU_Error_0x71 inst_access_mmu_error_handler | |
| 371 | #define H_HT0_Instruction_access_error_0x0a inst_access_error_handler | |
| 372 | #ifndef H_HT0_Internal_Processor_Error_0x29 | |
| 373 | #define H_HT0_Internal_Processor_Error_0x29 int_proc_err_handler | |
| 374 | #endif | |
| 375 | #define H_HT0_Data_Access_MMU_Error_0x72 data_access_mmu_error_handler | |
| 376 | #define H_HT0_Data_access_error_0x32 data_access_error_handler | |
| 377 | #define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler | |
| 378 | #define H_HT0_Sw_Recoverable_Error_0x40 sw_recoverable_error_handler | |
| 379 | #define H_HT0_Store_Error_0x07 store_error_handler | |
| 380 | #endif | |
| 381 | ||
| 382 | #define ISFSR_ITTM 0x1 | |
| 383 | #define ISFSR_ITTP 0x2 | |
| 384 | #define ISFSR_ITDP 0x3 | |
| 385 | #define ISFSR_ITMU 0x4 | |
| 386 | #define ISFSR_ITL2U 0x5 | |
| 387 | #define ISFSR_ITL2ND 0x6 | |
| 388 | #define ISFSR_ICL2U 0x1 | |
| 389 | #define ISFSR_ICL2ND 0x2 | |
| 390 | ||
| 391 | #define DSFSR_IRFU 0x1 | |
| 392 | #define DSFSR_IRFC 0x2 | |
| 393 | #define DSFSR_FRFU 0x3 | |
| 394 | #define DSFSR_FRFC 0x4 | |
| 395 | #define DSFSR_SBDLC 0x5 | |
| 396 | #define DSFSR_SBDLU 0x6 | |
| 397 | #define DSFSR_MRAU 0x7 | |
| 398 | #define DSFSR_TSAC 0x8 | |
| 399 | #define DSFSR_TSAU 0x9 | |
| 400 | #define DSFSR_SCAC 0x10 | |
| 401 | #define DSFSR_SCAU 0x11 | |
| 402 | #define DSFSR_TCCP 0x12 | |
| 403 | #define DSFSR_TCCU 0x13 | |
| 404 | #define DSFSR_DTTM 0x1 | |
| 405 | #define DSFSR_DTTP 0x2 | |
| 406 | #define DSFSR_DTDP 0x3 | |
| 407 | #define DSFSR_DTMU 0x4 | |
| 408 | #define DSFSR_DTL2U 0x5 | |
| 409 | #define DSFSR_DTL2ND 0x6 | |
| 410 | #define DSFSR_DCL2U 0x1 | |
| 411 | #define DSFSR_DCL2ND 0x2 | |
| 412 | #define DSFSR_SOCC 0x3 | |
| 413 | #define DSFSR_SOCU 0x4 | |
| 414 | ||
| 415 | #define DESR_ICVP 0x1 | |
| 416 | #define DESR_ICTP 0x2 | |
| 417 | #define DESR_ICTM 0x3 | |
| 418 | #define DESR_ICDP 0x4 | |
| 419 | #define DESR_DCVP 0x5 | |
| 420 | #define DESR_DCTP 0x6 | |
| 421 | #define DESR_DCTM 0x7 | |
| 422 | #define DESR_DCDP 0x8 | |
| 423 | #define DESR_HCE_L2C 0x9 | |
| 424 | #define DESR_SBDPC 0xa | |
| 425 | #define DESR_SBDPU 0x6 | |
| 426 | #define DESR_TCCD 0xd | |
| 427 | #define DESR_TCCU 0xe | |
| 428 | #define DESR_MAMU 0x7 | |
| 429 | #define DESR_MAL2C 0x8 | |
| 430 | #define DESR_MAL2U 0x9 | |
| 431 | #define DESR_MAL2ND 0xa | |
| 432 | #define DESR_CWQL2C 0xb | |
| 433 | #define DESR_CWQL2U 0xc | |
| 434 | #define DESR_CWQL2ND 0xd | |
| 435 | #define DESR_L2U 0x10 | |
| 436 | #define DESR_L2ND 0x11 | |
| 437 | #define DESR_ITL2C 0x1 | |
| 438 | #define DESR_ICL2C 0x2 | |
| 439 | #define DESR_DTL2C 0x3 | |
| 440 | #define DESR_DCL2C 0x4 | |
| 441 | #define DESR_SOCC 0x12 | |
| 442 | #define DESR_SOCU 0x13 | |
| 443 | #define DESR_SRE_L2C 0x14 | |
| 444 | ||
| 445 | #define DFESR_USER_PRIV 0x00 | |
| 446 | #define DFESR_SUP_PRIV 0x1 | |
| 447 | #define DFESR_HP_PRIV 0x2 | |
| 448 | ||
| 449 | #define ASI_NUCLEUS_QUAD_LDD 0x24 | |
| 450 | #define ASI_SEI 0x43 | |
| 451 | #define ASI_LSU_CONTROL 0x45 | |
| 452 | #define ASI_DCACHE_DATA 0x46 | |
| 453 | #define ASI_DCACHE_TAG 0x47 | |
| 454 | #define ASI_SEE 0x4B | |
| 455 | #define ASI_SES 0x4C | |
| 456 | #define ASI_SEA 0x4D | |
| 457 | #define ASI_ITLB_DATA_ACCESS 0x55 | |
| 458 | #define ASI_ITLB_TAG_READ 0x56 | |
| 459 | #define ASI_DMMU 0x58 | |
| 460 | #define ASI_DTLB_DATA_ACCESS 0x5D | |
| 461 | #define ASI_DTLB_TAG_READ 0x5E | |
| 462 | #define ASI_ICACHE_INSTR 0x66 | |
| 463 | #define ASI_ICACHE_TAG 0x67 | |
| 464 | #define ASI_PRIMARY 0x80 | |
| 465 | ||
| 466 | #define VA_ASI_ITLB_TAG_ACCESS 0x30 | |
| 467 | #define VA_ASI_DTLB_TAG_ACCESS 0x30 | |
| 468 | ||
| 469 | #define SEI_EN 31 | |
| 470 | #define SEI_SSHOT 30 | |
| 471 | #define SEI_IMD 29 | |
| 472 | #define SEI_IMT 28 | |
| 473 | #define SEI_DMD 27 | |
| 474 | #define SEI_DMT 26 | |
| 475 | #define SEI_IRF 25 | |
| 476 | #define SEI_FRF 24 | |
| 477 | ||
| 478 | #define SES_INIT_VALUE 0x10000000 | |
| 479 | #define SES_MEU 31 | |
| 480 | #define SES_MEC 30 | |
| 481 | #define SES_IMDU 25 | |
| 482 | #define SES_IMTU 24 | |
| 483 | #define SES_DMDU 23 | |
| 484 | #define SES_DMTU 22 | |
| 485 | #define SES_IDC 21 | |
| 486 | #define SES_ITC 20 | |
| 487 | #define SES_DDC 19 | |
| 488 | #define SES_DTC 18 | |
| 489 | #define SES_IRC 17 | |
| 490 | #define SES_IRU 16 | |
| 491 | #define SES_FRC 15 | |
| 492 | #define SES_FRU 14 | |
| 493 | #define SES_LDAU 13 | |
| 494 | #define SES_NCU 12 | |
| 495 | #define SES_DMSU 11 | |
| 496 | #define SES_MAU 9 | |
| 497 | ||
| 498 | #define TT_Instruction_Access_Error 0xa | |
| 499 | #define TT_FP_Exception_Other 0x22 | |
| 500 | #define TT_Internal_Processor_Error 0x29 | |
| 501 | #define TT_Data_Access_Error 0x32 | |
| 502 | #define TT_Corrected_ECC 0x63 | |
| 503 | #define TT_Sw_Correctable_ECC 0x40 | |
| 504 | #define TT_Fast_IMMU_Miss 0x64 | |
| 505 | #define TT_MA_Interrupt 0x74 | |
| 506 | #define TT_Data_Error 0x78 | |
| 507 | ||
| 508 | #define EXECUTED 0xeeced | |
| 509 | ||
| 510 | #define L2CS_PA0 0xA900000000 | |
| 511 | #define L2CS_PA1 0xB900000000 | |
| 512 | ||
| 513 | #define L2EE_PA0 0xAA00000000 | |
| 514 | #define L2EE_PA1 0xBA00000000 | |
| 515 | #define L2ES_PA0 0xAB00000000 | |
| 516 | #define L2ES_PA1 0xBB00000000 | |
| 517 | #define L2EA_PA0 0xAC00000000 | |
| 518 | #define L2EA_PA1 0xBC00000000 | |
| 519 | #define L2EI_PA0 0xAD00000000 | |
| 520 | #define L2EI_PA1 0xBD00000000 | |
| 521 | ||
| 522 | #define L2ES_MEU 63 | |
| 523 | #define L2ES_MEC 62 | |
| 524 | #define L2ES_RW 61 | |
| 525 | #define L2ES_MODA 60 | |
| 526 | #define L2ES_VCID 54 | |
| 527 | #define L2ES_TID L2ES_VCID | |
| 528 | #define L2ES_LDAC 53 | |
| 529 | #define L2ES_LDAU 52 | |
| 530 | #define L2ES_LDWC 51 | |
| 531 | #define L2ES_LDWU 50 | |
| 532 | #define L2ES_LDRC 49 | |
| 533 | #define L2ES_LDRU 48 | |
| 534 | #define L2ES_LDSC 47 | |
| 535 | #define L2ES_LDSU 46 | |
| 536 | #define L2ES_LTC 45 | |
| 537 | #define L2ES_LRF 44 | |
| 538 | #define L2ES_LRU L2ES_LRF | |
| 539 | #define L2ES_LVF 43 | |
| 540 | #define L2ES_LVU L2ES_LVF | |
| 541 | #define L2ES_DAC 42 | |
| 542 | #define L2ES_DAU 41 | |
| 543 | #define L2ES_DRC 40 | |
| 544 | #define L2ES_DRU 39 | |
| 545 | #define L2ES_DSC 38 | |
| 546 | #define L2ES_DSU 37 | |
| 547 | #define L2ES_VEC 36 | |
| 548 | #define L2ES_VEU 35 | |
| 549 | #define L2ES_LVC 34 | |
| 550 | ||
| 551 | #define DRAM_CSR_STEP 4096 | |
| 552 | #define DRAM_ES_PA 0x8400000280 | |
| 553 | #define DRAM_EI_PA 0x8400000290 | |
| 554 | ||
| 555 | #define DRAM_EI_ENB 31 | |
| 556 | #define DRAM_EI_SSHOT 30 | |
| 557 | ||
| 558 | #define DRAM_ES_MEU 63 | |
| 559 | #define DRAM_ES_MEC 62 | |
| 560 | #define DRAM_ES_DAC 61 | |
| 561 | #define DRAM_ES_DAU 60 | |
| 562 | #define DRAM_ES_DSC 59 | |
| 563 | #define DRAM_ES_DSU 58 | |
| 564 | #define DRAM_ES_DBU 57 | |
| 565 | ||
| 566 | #define DRAM_ES_MEB 56 | |
| 567 | #define DRAM_ES_FBU 55 | |
| 568 | #define DRAM_ES_FBR 54 | |
| 569 | ||
| 570 | ||
| 571 | #define JBI_ERR_INJECT 0x8000004800 | |
| 572 | #define JBI_ERR_CONFIG 0x8000010000 | |
| 573 | #define JBI_ERROR_LOG 0x8000010020 | |
| 574 | #define JBI_ERROR_OVF 0x8000010028 | |
| 575 | #define JBI_LOG_ENB 0x8000010030 | |
| 576 | #define JBI_SIG_ENB 0x8000010038 | |
| 577 | #define JBI_TRANS_TIMEOUT 0x8000010090 | |
| 578 | ||
| 579 | #define IOB_INT_MAN_ERR 0x9800000008 | |
| 580 | #define IOB_INT_CTL_ERR 0x9800000408 | |
| 581 | #define IOB_RESET_STATUS 0x9800000810 | |
| 582 | ||
| 583 | #define JBI_ERR_APAR 28 | |
| 584 | #define JBI_ERR_DPAR_WR 15 | |
| 585 | #define JBI_ERR_DPAR_RD 14 | |
| 586 | #define JBI_ERR_REP_UE 12 | |
| 587 | #define JBI_ERR_NONEX_RD 8 | |
| 588 | #define JBI_ERR_READ_TO 5 | |
| 589 | ||
| 590 | #define SSI_TIMEOUT 0xff00010088 | |
| 591 | #define SSI_LOG 0xff00000018 | |
| 592 | ||
| 593 | #define SOC_ESR_REG 0x8000003000 | |
| 594 | #define SOC_ELE_REG 0x8000003008 | |
| 595 | #define SOC_EIE_REG 0x8000003010 | |
| 596 | #define SOC_EJR_REG 0x8000003018 | |
| 597 | #define SOC_FEE_REG 0x8000003020 | |
| 598 | #define SOC_PER_REG 0x8000003028 | |
| 599 | #define SOC_SII_SYN_REG 0x8000003030 | |
| 600 | #define SOC_NCU_SYN_REG 0x8000003038 | |
| 601 | ||
| 602 | #define SiiNiuCtagUe 0 | |
| 603 | #define SiiDmuCtagUe 1 | |
| 604 | #define SiiNiuCtagCe 2 | |
| 605 | #define SiiDmuCtagCe 3 | |
| 606 | #define SiiNiuAParity 4 | |
| 607 | #define SiiDmuDParity 5 | |
| 608 | #define SiiNiuDParity 6 | |
| 609 | #define SiiDmuAParity 7 | |
| 610 | #define DmuInternal 8 | |
| 611 | #define DmuNcuCredit 9 | |
| 612 | #define DmuCtagCe 10 | |
| 613 | #define DmuCtagUe 11 | |
| 614 | #define DmuSiiCredit 12 | |
| 615 | #define DmuDataParity 13 | |
| 616 | #define NcuDataParity 14 | |
| 617 | #define NcuMondoTable 15 | |
| 618 | #define NcuMondoFifo 16 | |
| 619 | #define NcuIntTable 17 | |
| 620 | #define NcuPcxData 18 | |
| 621 | #define NcuPcxUe 19 | |
| 622 | #define NcuCpxUe 20 | |
| 623 | #define NcuDmuUe 21 | |
| 624 | #define NcuCtagUe 22 | |
| 625 | #define NcuCtagCe 23 | |
| 626 | #define TestMode 24 | |
| 627 | #define SioCtagUe 25 | |
| 628 | #define SioCtagCe 26 | |
| 629 | #define NiuCtagCe 27 | |
| 630 | #define NiuCtagUe 28 | |
| 631 | #define NiuDataParity 29 | |
| 632 | #define Mcu0Fbu 30 | |
| 633 | #define Mcu0Fbr 31 | |
| 634 | #define Mcu0Ecc 32 | |
| 635 | #define Mcu1Fbu 33 | |
| 636 | #define Mcu1Fbr 34 | |
| 637 | #define Mcu1Ecc 35 | |
| 638 | #define Mcu2Fbu 36 | |
| 639 | #define Mcu2Fbr 37 | |
| 640 | #define Mcu2Ecc 38 | |
| 641 | #define Mcu3Fbu 39 | |
| 642 | #define Mcu3Fbr 40 | |
| 643 | #define Mcu3Ecc 41 | |
| 644 | #define NcuDmuCredit 42 | |
| 645 | ||
| 646 | #define SOC_SII_ERR_SYND_REG 0x8000003030 | |
| 647 | #define SOC_NCU_ERR_SYND_REG 0x8000003038 | |
| 648 | ||
| 649 | ||
| 650 | ||
| 651 | #define DRAM_ERR_ADDR_REG_PA_0 0x8400000288 | |
| 652 | #define DRAM_ERR_ADDR_REG_PA_1 0x8400001288 | |
| 653 | #define DRAM_ERR_ADDR_REG_PA_2 0x8400002288 | |
| 654 | #define DRAM_ERR_ADDR_REG_PA_3 0x8400003288 | |
| 655 | ||
| 656 | #define DRAM_ERR_CNT_REG_PA_0 0x8400000298 | |
| 657 | #define DRAM_ERR_CNT_REG_PA_1 0x8400001298 | |
| 658 | #define DRAM_ERR_CNT_REG_PA_2 0x8400002298 | |
| 659 | #define DRAM_ERR_CNT_REG_PA_3 0x8400003298 | |
| 660 | ||
| 661 | #define DRAM_FBR_CNT_REG_PA_0 0x8400000c10 | |
| 662 | #define DRAM_FBR_CNT_REG_PA_1 0x8400001c10 | |
| 663 | #define DRAM_FBR_CNT_REG_PA_2 0x8400002c10 | |
| 664 | #define DRAM_FBR_CNT_REG_PA_3 0x8400003c10 | |
| 665 | ||
| 666 | #define DRAM_FBD_ERR_SYND_REG_PA_0 0x8400000c00 | |
| 667 | #define DRAM_FBD_ERR_SYND_REG_PA_1 0x8400001c00 | |
| 668 | #define DRAM_FBD_ERR_SYND_REG_PA_2 0x8400002c00 | |
| 669 | #define DRAM_FBD_ERR_SYND_REG_PA_3 0x8400003c00 | |
| 670 | ||
| 671 | ||
| 672 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA_0 0x8400000c08 | |
| 673 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA_1 0x8400001c08 | |
| 674 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA_2 0x8400002c08 | |
| 675 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA_3 0x8400003c08 | |
| 676 | ||
| 677 | #endif /* __ERR_DEFINES_H__ */ |