[OpenSPARC-T2-DV] / verif / diag / assembly / include / immu_miss_handler_ext.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: immu_miss_handler_ext.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
immu_miss_handler:  	

#ifdef EX_TRAPCHECK
	! extended trapcheck returns traptype
	mov	0x64,	%o0
#endif
	mov	ASI_IMMU_TAG_ACCESS_VAL, %g7
	ldxa	[%g7] ASI_IMMU_TAG_REG, %g6		! get va/context from tag-access

#ifdef USE_SOFTWARE_PTR_CALC

    ! SW Implementation of PTR register calQlations

iconfig_0:
    ! Load ZERO CTX TSB_CONFIG address in %g7
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %g7

immu_tsbptr_calc:
!Uses g1-g5, Expects TSB_CONFIG address in %g7, va in %g6, REsults in %g1
!Leave %g6 intact
#include <mmu_ptr_calc.s>

#else
    
    mov ASI_ITSB_PTR_0, %g7

immu_tsbptr_calc:

	ldxa	[%g7] ASI_ITSB_PTR, %g1		

#endif

#ifdef MIMIC_SOLARIS
	srlx	%g0, %g0, %g0
	brnz	%g0, HT0_Fast_Instr_Access_MMU_Miss_0x64
	sll	%g0, %g0, %g0
	xor	%g0, %g0, %g0
#endif
	
iload_entry:
	ldda	[%g1] ASI_NUCLEUS_QUAD_LDD, %g4		! load tte from tsb
	srlx	%g5, 63, %g2                        ! Check valid bit ..
	brz,a	%g2, immu_check_for_ptr_chase
	cmp	%g4, -1			                        ! if all 1's, follow link
	ldxa	[%g0] ASI_IMMU_TAG_REG, %g2		! get va/context from tag-target
#ifdef IMMU_HAS_SHARED_CTXT
check_immu_has_shared_ctx:
    ! If this TSB has use_ctxt bits set, then mask context
    ! 1. Get TSB config (%g7 has TSB_CONFIG addr OR TSB_PTR addr)
#ifndef USE_SOFTWARE_PTR_CALC
    sllx %g6, 51, %g3
    brz,a %g3, compare_ttetag_i            ! Ignore shared ctx for nucleus
	stxa %g0, [%g0]ASI_SCRATCHPAD          ! Save decision for later
    sub %g7, 0x20, %g3                     ! %g3 has TSB config ADDR
#else 
    mov %g7, %g3                           ! %g3 has TSB config ADDR
#endif
    ldxa [%g3] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 
check_use_ctx_i:
    srlx %g3, 61, %g3
    and %g3, 3, %g3                         ! %g3 has use_ctx bits ..
    brz %g3, compare_ttetag_i
	stxa %g3, [%g0]ASI_SCRATCHPAD          ! Save decision for later
mask_ctx_i:
    sethi %hi(0x1fff0000), %g1
    sllx %g1, 32, %g1                       ! Create mask for ctxt in tag target
    andn %g2, %g1, %g2                      ! Masked tag target (%g2) 
    andn %g4, %g1, %g4                      ! Masked tte tag (%g4)
#endif
compare_ttetag_i:
	cmp	%g2, %g4
	be	%xcc, immu_trap_done
	mov	0x80, %g1		                    ! offset (VA) for patrition id

    andcc %g5, 0x4, %g1                       ! Check TTE size for mask
	bz,a	%xcc, immu_check_for_ptr_chase      ! size <5 .. no masking reqd
	cmp	%g4, -1			                        ! if all 1's, follow link
    andn %g2, 0x3f, %g2                     ! mask out bits 22:27
	cmp	%g2, %g4                            ! Now compare masked tag target
	be	%xcc, immu_trap_done
	mov	0x80, %g1		                    ! offset (VA) for patrition id

immu_check_for_ptr_chase:    
	be,a	%xcc, immu_ptr_chase
    nop

    !! Look up all config registers (1-3)
    
#ifdef USE_SOFTWARE_PTR_CALC
    !! Gotta do SW table walk through the 3 remaing configs ..
    ! Expect %g7 to stll have addr of last config register
    ! and %g6 should have va/context from tag access register
    ! Normalize %g7
    sllx %g6, 51, %g5
    brnz,a %g5, 1f
    sub %g7, 0x20, %g7     ! this executes only if branch taken

1:
    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1
    bl,a immu_tsbptr_calc
iconfig_1:
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1, %g7

    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2
    bl,a immu_tsbptr_calc
iconfig_2:
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2, %g7

    cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3
    bl,a immu_tsbptr_calc
iconfig_3:
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g7

#else
    ! %g7 contains last pointer used ..
1:
iconfig_1:
	cmp	%g7, ASI_ITSB_PTR_1
	bge,a	%xcc, iconfig_2
	cmp	%g7, ASI_ITSB_PTR_2
	mov	ASI_ITSB_PTR_1, %g7
	ldxa	[%g7] ASI_ITSB_PTR, %g1
	ba,a	iload_entry
iconfig_2:
	bge,a	%xcc, iconfig_3
	cmp	%g7, ASI_ITSB_PTR_3
	mov	ASI_ITSB_PTR_2, %g7
	ldxa	[%g7] ASI_ITSB_PTR, %g1
	ba,a	iload_entry
iconfig_3:
	bge 	%xcc, ino_tte_in_tsb
	mov	ASI_ITSB_PTR_3, %g7
	ldxa	[%g7] ASI_ITSB_PTR, %g1
	ba,a	iload_entry
    
#endif

ino_tte_in_tsb:
    nop

! done if TT=0x9, otherwise error
#if defined(KAOS_SIMULATION) 
	ba	check_for_immu_sigsegv
	nop
#endif	
#ifdef IMMU_SKIP_IF_NO_TTE
    done
    nop
#endif	

itsb_failing_noptr:   
 	ta	T_BAD_TRAP
	nop
	
! Preserve g6/g7 !!
immu_ptr_chase:
 	or 	%g5, %g0, %g3           ! %g3 is link-reg
immu_ptr_chase_loop:
	ldda	[%g3] ASI_NUCLEUS_QUAD_LDD, %g4		! load tte from tsb
	srlx	%g5, 63, %g2
	brz	%g2, ifollow_link
	nop
	ldxa	[%g0] ASI_IMMU_TAG_REG, %g2		! get va/context from tag-target
#ifdef IMMU_HAS_SHARED_CTXT
check_immu_has_shared_ctx_l:
    ! If this TSB has use_ctxt bits set, then mask context
    ! 1. Get TSB config (%g7 has TSB_CONFIG addr OR TSB_PTR addr)
#ifndef USE_SOFTWARE_PTR_CALC
    sllx %g6, 51, %g1
    brz,a %g1, compare_ttetag_i            ! Ignore shared ctx for nucleus
	stxa %g0, [%g0]ASI_SCRATCHPAD          ! Save decision for later
    sub %g7, 0x20, %g1                     ! %g1 has TSB config ADDR
#else 
    mov %g7, %g1                           ! %g1 has TSB config ADDR
#endif
    ldxa [%g1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1 
check_use_ctx_il:
    srlx %g1, 61, %g1
    and %g1, 3, %g1                         ! %g1 has use_ctx bits ..
    brz %g1, compare_ttetag_il
	stxa %g1, [%g0]ASI_SCRATCHPAD          ! Save decision for later
mask_ctx_il:
    sethi %hi(0x1fff0000), %g1
    sllx %g1, 32, %g1                        ! Create mask for ctxt in tag target

    andn %g2, %g1, %g2                      ! Masked tag target (%g2) 
    andn %g4, %g1, %g4                      ! Masked tte tag (%g4)
#endif
compare_ttetag_il:
	cmp	%g2, %g4
	be	%xcc, immu_trap_done
	mov	0x80, %g1		                    ! offset (VA) for patrition id

    andcc %g5, 0x4, %g1                     ! Check TTE size for mask
	bz	%xcc, ifollow_link                  ! size <5 .. no masking reqd
    andn %g2, 0x3f, %g2                     ! mask out bits 22:27
	cmp	%g2, %g4                            ! Now compare masked tag target
	be	%xcc, immu_trap_done
	mov	0x80, %g1		                    ! offset (VA) for patrition id
                                            ! DONT USE G1 until PA is done

ifollow_link:
	ldx	[%g3+16], %g3
	cmp	%g3, -1
	bne	%xcc, immu_ptr_chase_loop ! keep chasing pointer
	nop
    
inext_tsb:
    ! Look up the Next TSB, until done with all TSBs ?
#ifdef USE_SOFTWARE_PTR_CALC
    ! Compare with TSB_CONFIG_3 for ctx0 and TSB_CONFIG_3+0x20 for ctx!0
    mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g4
    sllx %g6, 51, %g5
    brnz,a %g5, 2f
    sub %g7, 0x20, %g7
2:  
    cmp %g7, %g4
    bl 1b
    nop
    
#else
    cmp %g7, ASI_ITSB_PTR_3
    bl 1b
    nop
#endif

! finished pointer chasing, go to bad_trap
ipointer_chase_unsuccessful: ! done if TT=0x9, otherwise error	
#if defined(KAOS_SIMULATION) 
	ba	check_for_immu_sigsegv
	nop
#endif	
#ifdef IMMU_SKIP_IF_NO_TTE
    done
	nop
#endif

ipage_fault_ptr:

 	ta	T_BAD_TRAP
	nop
	

immu_trap_done:
#ifdef IMMU_HAS_SHARED_CTXT
    ! %g6 has the unmasked tag access
    ldxa [%g0]ASI_SCRATCHPAD, %g3           ! Do we need to force ctxt ?
    brz %g3, done_forcing_ctxt_i            ! Nope
    cmp %g3, 1                              ! Which one ?
    movne %xcc, 0x8, %g3                    ! ctxt_0
    move %xcc, 0x108, %g3                   ! ctxt_1
force_ctxt_i:
    ldxa [%g3]ASI_PRIMARY_CONTEXT_REG, %g3  ! Get ctxt value
    srlx %g6, 13, %g2
    sllx %g2, 13, %g2                       ! Clear ctxt from tag-access
    or %g3, %g2, %g2                        ! Stuff in masked tag-access
	mov	ASI_IMMU_TAG_ACCESS_VAL, %g3        
    stxa %g2, [%g3]0x50                     ! Save forced ctx in tag-access
done_forcing_ctxt_i:
#endif
#ifdef SOME_TSB_PANOTRA
    ! Figure out if Offset should be added.
    ! %g7 contains TSB VA if SW ptr calc, and PTR address if HW_PTR_CALC
    ! %g6 contains ASI_IMMU_TAG_REG value
#ifndef USE_SOFTWARE_PTR_CALC
    sllx %g6, 51, %g3
    brz,a %g3, .+8
    sub %g7, 0x20, %g7      ! extra subtract for Z ctx 
    sub %g7, 0x20, %g7    
#endif
    ldxa [%g7] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
check_ranotpa_i:
    and %g3, 0x100, %g3         ! Is RANOTPA 1 ?
    brz,a %g3, loaded_itlb
	stxa	%g5, [ %g0 ] ASI_ITLB_DATA_IN	! data-in
#endif
xlate_ratopa_i:
	! add partition base to data-in
	setx	partition_base_list, %g3, %g2	! for partition base
	ldxa	[%g1] ASI_PARTITION_ID, %g3		! partition id
	sllx	%g3, 3, %g3		! offset - partition list
	ldx	[%g2 + %g3], %g1
	add	%g5, %g1, %g5
	stxa	%g5, [ %g0 ] ASI_ITLB_DATA_IN	! data-in
loaded_itlb:

#ifdef H_T0_fast_instr_access_MMU_miss_Ext
	setx	H_T0_fast_instr_access_MMU_miss_Ext, %g4, %g5
	jmp	%g5
	nop
#else
	retry 
#endif
	

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!	
! Instr_Real_Tran_Miss_0x3e code here
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!    
    
immu_real_miss_handler:
	
	mov	0x30, %g7
	ldxa	[%g7] 0x50, %g2		! get ra from tag-access

	mov	%g2, %g4
	mov	%g0, %g1		! %g1 will contain partition base

#ifndef DISABLE_PART_LIMIT_CHECK
	mov	%g4, %g2
	srlx	%g2, 33, %g2		! check to see if ra exceeds 8GB limit
	cmp	%g2, %g0
	tne	%xcc, T_BAD_TRAP
#endif

	! add partition base to data-in
	setx	partition_base_list, %g1, %g2	! for partition base
	mov	ASI_PARTITION_ID_VAL, %g1		! offset (VA) for patrition id
	ldxa	[%g1] ASI_PARTITION_ID, %g3		! partition id
	sllx	%g3, 3, %g3		! offset - partition list
	ldx	[%g2 + %g3], %g1

immu_real_skip_part_base:
#ifdef REAL_DATA_ATTR
        setx    REAL_INST_ATTR, %g2, %g5 ! user defined attributes
#else
#ifndef SUN4V
	setx	0x8000000000000020, %g2, %g5 ! CP
#else
	setx	0x8000000000000400, %g2, %g5 ! CP
#endif
#endif

	srlx	%g4, 13, %g4		! get rid of garbage in context field
	sllx	%g4, 13, %g4
	or	%g4, %g5, %g5
	add	%g5, %g1, %g5
	mov	ASI_IMMU_TAG_ACCESS_VAL, %g7


	mov	0x400, %g6
	stxa	%g4, [ %g7 ] ASI_IMMU_TAG_REG	! {tag-access, data-in}
	stxa	%g5, [ %g6 ] ASI_ITLB_DATA_IN
	retry 

#if defined(KAOS_SIMULATION)	
check_for_immu_sigsegv: 


        rdpr    %tpc, %g1            !get va
        set     0xffffe000, %g2
        andcc   %g1, %g2, %g3        ! check first page 
        be      1f
        nop
        cmp     %g2, %g3             ! check last page
        bne     bad_trap
        nop
1:      
        add     %o7, 8, %g1
        wrpr    %g1, %tnpc 
        done
        nop

.global illegal_trap_handler
illegal_trap_handler:

        rdpr     %tpc, %g2

	ta       0x2e
        cmp      %o1, 0	
        setx     ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_0,THR_0_PARTID), %g3, %g1
	be,a     1f
	nop 
        cmp      %o1, 1
        setx     ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_1,THR_1_PARTID), %g3, %g1
	be,a     1f
	nop 
        cmp      %o1, 2
        setx     ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_2,THR_2_PARTID), %g3, %g1
	be,a     1f
	nop 
        cmp      %o1, 3
        setx     ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_3,THR_3_PARTID), %g3, %g1
	be,a     1f
	nop
        cmp      %o1, 4
        setx     ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_4,THR_4_PARTID), %g3, %g1
	be,a     1f
	nop 
        cmp      %o1, 5
        setx     ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_5,THR_5_PARTID), %g3, %g1
	be,a     1f
	nop 
        cmp      %o1, 6
        setx     ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_6,THR_6_PARTID), %g3, %g1
	be,a     1f
	nop 
        cmp      %o1, 7
        setx     ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_7,THR_7_PARTID), %g3, %g1
	be,a     1f
	nop
	ta       0x1
	nop

1:      stx      %g2, [%g1]

        mov     0x08, %g1
        ldxa    [%g1] 0x21, %o1
        mov     0x10, %g1
        ldxa    [%g1] 0x21, %o2 
        set     0x1, %o3
        set     0x0, %o4
        setx    handle_ill_trap, %g1, %o5

        ta 0x2a

        nop
		
#endif
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: immu_miss_handler_ext.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	immu_miss_handler:
	39
	40	#ifdef EX_TRAPCHECK
	41	! extended trapcheck returns traptype
	42	mov 0x64, %o0
	43	#endif
	44	mov ASI_IMMU_TAG_ACCESS_VAL, %g7
	45	ldxa [%g7] ASI_IMMU_TAG_REG, %g6 ! get va/context from tag-access
	46
	47	#ifdef USE_SOFTWARE_PTR_CALC
	48
	49	! SW Implementation of PTR register calQlations
	50
	51	iconfig_0:
	52	! Load ZERO CTX TSB_CONFIG address in %g7
	53	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %g7
	54
	55	immu_tsbptr_calc:
	56	!Uses g1-g5, Expects TSB_CONFIG address in %g7, va in %g6, REsults in %g1
	57	!Leave %g6 intact
	58	#include <mmu_ptr_calc.s>
	59
	60	#else
	61
	62	mov ASI_ITSB_PTR_0, %g7
	63
	64	immu_tsbptr_calc:
65
66	ldxa [%g7] ASI_ITSB_PTR, %g1
67
68	#endif
69
70	#ifdef MIMIC_SOLARIS
71	srlx %g0, %g0, %g0
72	brnz %g0, HT0_Fast_Instr_Access_MMU_Miss_0x64
73	sll %g0, %g0, %g0
74	xor %g0, %g0, %g0
75	#endif
76
77	iload_entry:
78	ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4 ! load tte from tsb
79	srlx %g5, 63, %g2 ! Check valid bit ..
80	brz,a %g2, immu_check_for_ptr_chase
81	cmp %g4, -1 ! if all 1's, follow link
82	ldxa [%g0] ASI_IMMU_TAG_REG, %g2 ! get va/context from tag-target
83	#ifdef IMMU_HAS_SHARED_CTXT
84	check_immu_has_shared_ctx:
85	! If this TSB has use_ctxt bits set, then mask context
86	! 1. Get TSB config (%g7 has TSB_CONFIG addr OR TSB_PTR addr)
87	#ifndef USE_SOFTWARE_PTR_CALC
88	sllx %g6, 51, %g3
89	brz,a %g3, compare_ttetag_i ! Ignore shared ctx for nucleus
90	stxa %g0, [%g0]ASI_SCRATCHPAD ! Save decision for later
91	sub %g7, 0x20, %g3 ! %g3 has TSB config ADDR
92	#else
93	mov %g7, %g3 ! %g3 has TSB config ADDR
94	#endif
95	ldxa [%g3] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
96	check_use_ctx_i:
97	srlx %g3, 61, %g3
98	and %g3, 3, %g3 ! %g3 has use_ctx bits ..
99	brz %g3, compare_ttetag_i
100	stxa %g3, [%g0]ASI_SCRATCHPAD ! Save decision for later
101	mask_ctx_i:
102	sethi %hi(0x1fff0000), %g1
103	sllx %g1, 32, %g1 ! Create mask for ctxt in tag target
104	andn %g2, %g1, %g2 ! Masked tag target (%g2)
105	andn %g4, %g1, %g4 ! Masked tte tag (%g4)
106	#endif
107	compare_ttetag_i:
108	cmp %g2, %g4
109	be %xcc, immu_trap_done
110	mov 0x80, %g1 ! offset (VA) for patrition id
111
112	andcc %g5, 0x4, %g1 ! Check TTE size for mask
113	bz,a %xcc, immu_check_for_ptr_chase ! size <5 .. no masking reqd
114	cmp %g4, -1 ! if all 1's, follow link
115	andn %g2, 0x3f, %g2 ! mask out bits 22:27
116	cmp %g2, %g4 ! Now compare masked tag target
117	be %xcc, immu_trap_done
118	mov 0x80, %g1 ! offset (VA) for patrition id
119
120	immu_check_for_ptr_chase:
121	be,a %xcc, immu_ptr_chase
122	nop
123
124	!! Look up all config registers (1-3)
125
126	#ifdef USE_SOFTWARE_PTR_CALC
127	!! Gotta do SW table walk through the 3 remaing configs ..
128	! Expect %g7 to stll have addr of last config register
129	! and %g6 should have va/context from tag access register
130	! Normalize %g7
131	sllx %g6, 51, %g5
132	brnz,a %g5, 1f
133	sub %g7, 0x20, %g7 ! this executes only if branch taken
134
135	1:
136	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1
137	bl,a immu_tsbptr_calc
138	iconfig_1:
139	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1, %g7
140
141	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2
142	bl,a immu_tsbptr_calc
143	iconfig_2:
144	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2, %g7
145
146	cmp %g7, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3
147	bl,a immu_tsbptr_calc
148	iconfig_3:
149	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g7
150
151	#else
152	! %g7 contains last pointer used ..
153	1:
154	iconfig_1:
155	cmp %g7, ASI_ITSB_PTR_1
156	bge,a %xcc, iconfig_2
157	cmp %g7, ASI_ITSB_PTR_2
158	mov ASI_ITSB_PTR_1, %g7
159	ldxa [%g7] ASI_ITSB_PTR, %g1
160	ba,a iload_entry
161	iconfig_2:
162	bge,a %xcc, iconfig_3
163	cmp %g7, ASI_ITSB_PTR_3
164	mov ASI_ITSB_PTR_2, %g7
165	ldxa [%g7] ASI_ITSB_PTR, %g1
166	ba,a iload_entry
167	iconfig_3:
168	bge %xcc, ino_tte_in_tsb
169	mov ASI_ITSB_PTR_3, %g7
170	ldxa [%g7] ASI_ITSB_PTR, %g1
171	ba,a iload_entry
172
173	#endif
174
175	ino_tte_in_tsb:
176	nop
177
178	! done if TT=0x9, otherwise error
179	#if defined(KAOS_SIMULATION)
180	ba check_for_immu_sigsegv
181	nop
182	#endif
183	#ifdef IMMU_SKIP_IF_NO_TTE
184	done
185	nop
186	#endif
187
188	itsb_failing_noptr:
189	ta T_BAD_TRAP
190	nop
191
192	! Preserve g6/g7 !!
193	immu_ptr_chase:
194	or %g5, %g0, %g3 ! %g3 is link-reg
195	immu_ptr_chase_loop:
196	ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! load tte from tsb
197	srlx %g5, 63, %g2
198	brz %g2, ifollow_link
199	nop
200	ldxa [%g0] ASI_IMMU_TAG_REG, %g2 ! get va/context from tag-target
201	#ifdef IMMU_HAS_SHARED_CTXT
202	check_immu_has_shared_ctx_l:
203	! If this TSB has use_ctxt bits set, then mask context
204	! 1. Get TSB config (%g7 has TSB_CONFIG addr OR TSB_PTR addr)
205	#ifndef USE_SOFTWARE_PTR_CALC
206	sllx %g6, 51, %g1
207	brz,a %g1, compare_ttetag_i ! Ignore shared ctx for nucleus
208	stxa %g0, [%g0]ASI_SCRATCHPAD ! Save decision for later
209	sub %g7, 0x20, %g1 ! %g1 has TSB config ADDR
210	#else
211	mov %g7, %g1 ! %g1 has TSB config ADDR
212	#endif
213	ldxa [%g1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g1
214	check_use_ctx_il:
215	srlx %g1, 61, %g1
216	and %g1, 3, %g1 ! %g1 has use_ctx bits ..
217	brz %g1, compare_ttetag_il
218	stxa %g1, [%g0]ASI_SCRATCHPAD ! Save decision for later
219	mask_ctx_il:
220	sethi %hi(0x1fff0000), %g1
221	sllx %g1, 32, %g1 ! Create mask for ctxt in tag target
222
223	andn %g2, %g1, %g2 ! Masked tag target (%g2)
224	andn %g4, %g1, %g4 ! Masked tte tag (%g4)
225	#endif
226	compare_ttetag_il:
227	cmp %g2, %g4
228	be %xcc, immu_trap_done
229	mov 0x80, %g1 ! offset (VA) for patrition id
230
231	andcc %g5, 0x4, %g1 ! Check TTE size for mask
232	bz %xcc, ifollow_link ! size <5 .. no masking reqd
233	andn %g2, 0x3f, %g2 ! mask out bits 22:27
234	cmp %g2, %g4 ! Now compare masked tag target
235	be %xcc, immu_trap_done
236	mov 0x80, %g1 ! offset (VA) for patrition id
237	! DONT USE G1 until PA is done
238
239	ifollow_link:
240	ldx [%g3+16], %g3
241	cmp %g3, -1
242	bne %xcc, immu_ptr_chase_loop ! keep chasing pointer
243	nop
244
245	inext_tsb:
246	! Look up the Next TSB, until done with all TSBs ?
247	#ifdef USE_SOFTWARE_PTR_CALC
248	! Compare with TSB_CONFIG_3 for ctx0 and TSB_CONFIG_3+0x20 for ctx!0
249	mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %g4
250	sllx %g6, 51, %g5
251	brnz,a %g5, 2f
252	sub %g7, 0x20, %g7
253	2:
254	cmp %g7, %g4
255	bl 1b
256	nop
257
258	#else
259	cmp %g7, ASI_ITSB_PTR_3
260	bl 1b
261	nop
262	#endif
263
264	! finished pointer chasing, go to bad_trap
265	ipointer_chase_unsuccessful: ! done if TT=0x9, otherwise error
266	#if defined(KAOS_SIMULATION)
267	ba check_for_immu_sigsegv
268	nop
269	#endif
270	#ifdef IMMU_SKIP_IF_NO_TTE
271	done
272	nop
273	#endif
274
275	ipage_fault_ptr:
276
277	ta T_BAD_TRAP
278	nop
279
280
281	immu_trap_done:
282	#ifdef IMMU_HAS_SHARED_CTXT
283	! %g6 has the unmasked tag access
284	ldxa [%g0]ASI_SCRATCHPAD, %g3 ! Do we need to force ctxt ?
285	brz %g3, done_forcing_ctxt_i ! Nope
286	cmp %g3, 1 ! Which one ?
287	movne %xcc, 0x8, %g3 ! ctxt_0
288	move %xcc, 0x108, %g3 ! ctxt_1
289	force_ctxt_i:
290	ldxa [%g3]ASI_PRIMARY_CONTEXT_REG, %g3 ! Get ctxt value
291	srlx %g6, 13, %g2
292	sllx %g2, 13, %g2 ! Clear ctxt from tag-access
293	or %g3, %g2, %g2 ! Stuff in masked tag-access
294	mov ASI_IMMU_TAG_ACCESS_VAL, %g3
295	stxa %g2, [%g3]0x50 ! Save forced ctx in tag-access
296	done_forcing_ctxt_i:
297	#endif
298	#ifdef SOME_TSB_PANOTRA
299	! Figure out if Offset should be added.
300	! %g7 contains TSB VA if SW ptr calc, and PTR address if HW_PTR_CALC
301	! %g6 contains ASI_IMMU_TAG_REG value
302	#ifndef USE_SOFTWARE_PTR_CALC
303	sllx %g6, 51, %g3
304	brz,a %g3, .+8
305	sub %g7, 0x20, %g7 ! extra subtract for Z ctx
306	sub %g7, 0x20, %g7
307	#endif
308	ldxa [%g7] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
309	check_ranotpa_i:
310	and %g3, 0x100, %g3 ! Is RANOTPA 1 ?
311	brz,a %g3, loaded_itlb
312	stxa %g5, [ %g0 ] ASI_ITLB_DATA_IN ! data-in
313	#endif
314	xlate_ratopa_i:
315	! add partition base to data-in
316	setx partition_base_list, %g3, %g2 ! for partition base
317	ldxa [%g1] ASI_PARTITION_ID, %g3 ! partition id
318	sllx %g3, 3, %g3 ! offset - partition list
319	ldx [%g2 + %g3], %g1
320	add %g5, %g1, %g5
321	stxa %g5, [ %g0 ] ASI_ITLB_DATA_IN ! data-in
322	loaded_itlb:
323
324	#ifdef H_T0_fast_instr_access_MMU_miss_Ext
325	setx H_T0_fast_instr_access_MMU_miss_Ext, %g4, %g5
326	jmp %g5
327	nop
328	#else
329	retry
330	#endif
331
332
333
334
335	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
336	! Instr_Real_Tran_Miss_0x3e code here
337	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
338
339	immu_real_miss_handler:
340
341	mov 0x30, %g7
342	ldxa [%g7] 0x50, %g2 ! get ra from tag-access
343
344	mov %g2, %g4
345	mov %g0, %g1 ! %g1 will contain partition base
346
347	#ifndef DISABLE_PART_LIMIT_CHECK
348	mov %g4, %g2
349	srlx %g2, 33, %g2 ! check to see if ra exceeds 8GB limit
350	cmp %g2, %g0
351	tne %xcc, T_BAD_TRAP
352	#endif
353
354	! add partition base to data-in
355	setx partition_base_list, %g1, %g2 ! for partition base
356	mov ASI_PARTITION_ID_VAL, %g1 ! offset (VA) for patrition id
357	ldxa [%g1] ASI_PARTITION_ID, %g3 ! partition id
358	sllx %g3, 3, %g3 ! offset - partition list
359	ldx [%g2 + %g3], %g1
360
361	immu_real_skip_part_base:
362	#ifdef REAL_DATA_ATTR
363	setx REAL_INST_ATTR, %g2, %g5 ! user defined attributes
364	#else
365	#ifndef SUN4V
366	setx 0x8000000000000020, %g2, %g5 ! CP
367	#else
368	setx 0x8000000000000400, %g2, %g5 ! CP
369	#endif
370	#endif
371
372	srlx %g4, 13, %g4 ! get rid of garbage in context field
373	sllx %g4, 13, %g4
374	or %g4, %g5, %g5
375	add %g5, %g1, %g5
376	mov ASI_IMMU_TAG_ACCESS_VAL, %g7
377
378
379	mov 0x400, %g6
380	stxa %g4, [ %g7 ] ASI_IMMU_TAG_REG ! {tag-access, data-in}
381	stxa %g5, [ %g6 ] ASI_ITLB_DATA_IN
382	retry
383
384	#if defined(KAOS_SIMULATION)
385	check_for_immu_sigsegv:
386
387
388	rdpr %tpc, %g1 !get va
389	set 0xffffe000, %g2
390	andcc %g1, %g2, %g3 ! check first page
391	be 1f
392	nop
393	cmp %g2, %g3 ! check last page
394	bne bad_trap
395	nop
396	1:
397	add %o7, 8, %g1
398	wrpr %g1, %tnpc
399	done
400	nop
401
402	.global illegal_trap_handler
403	illegal_trap_handler:
404
405	rdpr %tpc, %g2
406
407	ta 0x2e
408	cmp %o1, 0
409	setx ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_0,THR_0_PARTID), %g3, %g1
410	be,a 1f
411	nop
412	cmp %o1, 1
413	setx ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_1,THR_1_PARTID), %g3, %g1
414	be,a 1f
415	nop
416	cmp %o1, 2
417	setx ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_2,THR_2_PARTID), %g3, %g1
418	be,a 1f
419	nop
420	cmp %o1, 3
421	setx ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_3,THR_3_PARTID), %g3, %g1
422	be,a 1f
423	nop
424	cmp %o1, 4
425	setx ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_4,THR_4_PARTID), %g3, %g1
426	be,a 1f
427	nop
428	cmp %o1, 5
429	setx ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_5,THR_5_PARTID), %g3, %g1
430	be,a 1f
431	nop
432	cmp %o1, 6
433	setx ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_6,THR_6_PARTID), %g3, %g1
434	be,a 1f
435	nop
436	cmp %o1, 7
437	setx ra2pa(LOCAL_SUPERVISOR_SECTION_DATA_PA_7,THR_7_PARTID), %g3, %g1
438	be,a 1f
439	nop
440	ta 0x1
441	nop
442
443	1: stx %g2, [%g1]
444
445	mov 0x08, %g1
446	ldxa [%g1] 0x21, %o1
447	mov 0x10, %g1
448	ldxa [%g1] 0x21, %o2
449	set 0x1, %o3
450	set 0x0, %o4
451	setx handle_ill_trap, %g1, %o5
452
453	ta 0x2a
454
455	nop
456
457	#endif