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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / interrupt0x60_defines.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt0x60_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
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22*
23* For the avoidance of doubt, and except that if any non-GPL license
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36* ========== Copyright Header End ============================================
37*/
38#ifndef INTERRUPT0x60_DEFINES_H
39#define INTERRUPT0x60_DEFINES_H 1
40
41#define H_HT0_Interrupt_0x60
42/* Note: Must preserve %o7, so save it temporarily in %g7 */
43#define My_HT0_Interrupt_0x60 \
44 mov %o7, %g7; \
45 call intr0x60_handler; \
46 nop
47
48
49/*
50 * This is tightly linked with interrupt0x60_init.s
51 *
52 * Here are the supported CPP macros. In all cases,
53 * <I> stands for an index, allowing multiple uniquely-named macros.
54 * <IVN> stands for an interrupt vector number, 0-63.
55 * <M> stands for PIU mondo number (20-59, 62, 63).
56 * <T> stands for a thread number (0-63).
57 *
58 * INTR0x60_BAD_IV=<IVN>
59 * If defined, interrupt vector <IVN> is used in INT_MAN
60 * and MONDO_INT_VEC for any interrupts that are not allowed.
61 * If not defined, interrupt vector 9 will be used.
62 *
63 * INTR0x60_BAD_THREAD=<T>
64 * If defined, thread <T> is used in INT_MAN
65 * for any interrupts that are not allowed.
66 * If not defined, thread 0 will be used.
67 *
68 *
69 *
70 * INTR0x60_CC_IV_<I>=<IVN> (<I> = 0-47)
71 * If defined, interrupt vector <IVN> is permitted to be used
72 * for cross-call interrupts. (Max of 48 interrupt vectors can
73 * be used for this purpose; could be increased if needed.)
74 *
75 * INTR0x60_CC_DEST_ALL
76 * If defined, allow cross-call interrupts to all threads.
77 * If not defined, check the target thread against
78 * INTR0x60_CC_DEST_<T>
79 *
80 * INTR0x60_CC_DEST_<T>
81 * Ignored if INTR0x60_CC_DEST_ALL is defined.
82 * If defined to a non-zero value,
83 * allow cross-call interrupts to thread <T>
84 * If not defined, or defined as zero,
85 * do not allow cross-call interrupts to thread <T>
86 *
87 * INTR0x60_CC_EXTRA_HANDLER
88 * If defined (as assembler code), the code will be executed
89 * at the end of the trap handler in hyperprivileged mode.
90 * The code can assume %g1 is the current thread,
91 * and %g2 is the received interrupt vector number.
92 *
93 *
94 *
95 * INTR0x60_MONDO_IV=<IVN>
96 * If defined, interrupt vector <IVN> is used for mondo interrupts
97 * (INTx, MSI, PCIe power management). If not defined, mondo
98 * interrupts will be assigned to INTR0x60_BAD_IV.
99 *
100 * INTR0x60_MONDO_<M>_V=1
101 * If defined to a non-zero value, mondo <M> will be dispatched to
102 * a thread. Otherwise, mondo <M> will not be dispatched. Used to
103 * set up the PIU Interrupt Mapping Registers.
104 *
105 * INTR0x60_MONDO_<M>_MODE=1
106 * If defined to a non-zero value, mondo <M> will bear data (MDO_MODE).
107 * Otherwise, mondo <M> will not bear data. Used to set up
108 * the PIU Interrupt Mapping Registers.
109 *
110 * INTR0x60_MONDO_BAD_THREAD=<T>
111 * If defined, any unused mondo will be assigned to thread <T>.
112 * Otherwise, any unused mondo will be assigned to INTR0x60_BAD_THREAD.
113 * Used to set up the PIU Interrupt Mapping Registers when
114 * INTR0x60_MONDO_<M>_THREAD is not defined.
115 *
116 * INTR0x60_MONDO_<M>_THREAD=<T>
117 * If defined, mondo <M> will be assigned to thread <T>.
118 * Otherwise, mondo <M> will be assigned to INTR0x60_MONDO_BAD_THREAD.
119 * Used to set up the PIU Interrupt Mapping Registers.
120 *
121 * INTR0x60_MONDO_<M>_CNTRL=<N> (<N> = 0-3)
122 * If defined, mondo <M> will be assigned to interrupt controller <N>.
123 * Otherwise, mondo <M> will be assigned to interrupt controller 0.
124 * Used to set up the PIU Interrupt Mapping Registers.
125 *
126 * INTR0x60_MONDO_<M>_DMAEPT_ENGINE=<N> (<N> = 1-4)
127 * Unused for Denali endpoint; used for DMAEPT/PEP (FC_NO_PEU_VERA).
128 * If defined, mondo <M> will be generated by DMA engine <N>.
129 * Default is 1+modulo(<M>,4).
130 * Used when clearing INTX.
131 *
132 * INTR0x60_MSI_<I>_NUM=<MSI> (<I> = 0-7, <MSI> = 0-255)
133 * INTR0x60_MSI_<I>_EQN=<EQN> (<I> = 0-7, <EQN> = 0-35)
134 * If defined, MSI <MSI> will be written to event queue <EQN>.
135 * Otherwise, MSI <MSI> will be treated as an error.
136 * Note that INTR0x60_MONDO_<M>_* must be defined, where
137 * <M> is equal to <EQN> plus 24.
138 * Used to set up the PIU MSI Mapping Registers.
139 *
140 * INTR0x60_PM_PME_EQN=<EQN> (<EQN> = 0-35)
141 * If defined, PM_PME messages will be written to event queue <EQN>.
142 * Otherwise, PM_PME messages will be treated as an error.
143 * Note that INTR0x60_MONDO_<M>_* must be defined, where
144 * <M> is equal to <EQN> plus 24.
145 * Used to set up the PIU PM_PME Mapping Registers.
146 *
147 * INTR0x60_PME_TO_ACK_EQN=<EQN> (<EQN> = 0-35)
148 * If defined, PME_TO_ACK messages will be written to event queue <EQN>.
149 * Otherwise, PME_TO_ACK messages will be treated as an error.
150 * Note that INTR0x60_MONDO_<M>_* must be defined, where
151 * <M> is equal to <EQN> plus 24.
152 * Used to set up the PIU PME_TO_ACK Mapping Registers.
153 *
154 * INTR0x60_EVENT_QUEUE_BASE
155 * Label of data area for the event queue.
156 * Must be 512KB aligned (19 lowest bits must be 0).
157 * Must be defined if using MSI, PM_PME or PME_TO_ACK.
158 *
159 * INTR0x60_MSI_START_ADDRESS
160 * Starting PCI-E address for MSI messages.
161 * Must be 64KB aligned (16 lowest bits must be 0).
162 * Must be defined if using MSI.
163 *
164 * INTR0x60_INTX_DEASSERT_TIMEOUT
165 * Maximum number of iterations while waiting for
166 * the interrupt status bit in PCI_E_INTX_STATUS_ADDR
167 * to be cleared after requesting the PCI-E endpoint
168 * to send the deassert message.
169 *
170 * INTR0x60_INT<x>_EXTRA_HANDLER (<x> = A, B, C or D)
171 * If defined (as assembler code), the code will be executed
172 * at the end of the trap handler in hyperprivileged mode.
173 * The code can assume %g1 is the current thread, and
174 * %g2 is the received interrupt vector number.
175 *
176 * INTR0x60_MSI_<I>_EXTRA_HANDLER_WHILE_BUSY
177 * If defined (as assembler code), the code will be executed
178 * in the trap handler in hyperprivileged mode while the
179 * mondo busy flag (MONDO_INT_ABUSY) is still asserted.
180 * The code can assume %g1 is the current thread,
181 * %g2 is the received interrupt vector number, and
182 * %g3 is the mondo number.
183 *
184 * INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
185 * If defined (as assembler code), the code will be executed
186 * in the trap handler in hyperprivileged mode while the
187 * event queue is disabled.
188 * The code can assume %g1 is the current thread,
189 * %g2 is the received interrupt vector number, and
190 * %g3 is the mondo number.
191 *
192 * INTR0x60_MSI_EXTRA_HANDLER
193 * If defined (as assembler code), the code will be executed
194 * at the end of the trap handler in hyperprivileged mode.
195 * The code can assume %g1 is the current thread,
196 * %g2 is the received interrupt vector number, and
197 * %g3 is the mondo number.
198 *
199 * INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED
200 * If defined (as assembler code), the code will be executed
201 * in the trap handler in hyperprivileged mode while the
202 * event queue is disabled.
203 * The code can assume %g1 is the current thread,
204 * %g2 is the received interrupt vector number, and
205 * %g3 is the mondo number.
206 *
207 * INTR0x60_PM_PME_EXTRA_HANDLER
208 * If defined (as assembler code), the code will be executed
209 * at the end of the trap handler in hyperprivileged mode.
210 * The code can assume %g1 is the current thread,
211 * %g2 is the received interrupt vector number, and
212 * %g3 is the mondo number.
213 *
214 * INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED
215 * If defined (as assembler code), the code will be executed
216 * in the trap handler in hyperprivileged mode while the
217 * event queue is disabled.
218 * The code can assume %g1 is the current thread,
219 * %g2 is the received interrupt vector number, and
220 * %g3 is the mondo number.
221 *
222 * INTR0x60_PME_TO_ACK_EXTRA_HANDLER
223 * If defined (as assembler code), the code will be executed
224 * at the end of the trap handler in hyperprivileged mode.
225 * The code can assume %g1 is the current thread,
226 * %g2 is the received interrupt vector number, and
227 * %g3 is the mondo number.
228 *
229 *
230 *
231 * INTR0x60_NIU_RX_IV_<I>=<IVN> (<I> = 0-15)
232 * If defined, interrupts coming from NIU Logical Device Group <IVN>
233 * are permitted and will be assigned to interrupt vector <IVN>.
234 * The interrupt must be caused by RX DMA.
235 * (Max of 16 interrupt vectors can be used for this purpose;
236 * could be increased if needed.)
237 * NOTE: The interrupt vector number is always the same
238 * as the Logical Device Group. The System Interrupt
239 * Data register in the NIU for the LDG will be
240 * initialized to <IVN>+64
241 *
242 * INTR0x60_NIU_RX_DMA_<I>=<N> (<I> = 0-15; <N> = 0-15)
243 * Must be defined if INTR0x60_NIU_RX_IV_<I> is defined (same <I>).
244 * Interrupts coming from NIU RX DMA Channel <N>
245 * will be assigned to the NIU Logical Device Group specified
246 * by INTR0x60_NIU_RX_IV_<I> (same <I>).
247 *
248 * INTR0x60_NIU_RX_THREAD_<I>=<T> (<I> = 0-15)
249 * If defined, interrupts coming from NIU Logical Device Group
250 * specified by INTR0x60_NIU_RX_IV_<I> (same <I>) will be sent to
251 * thread <T>. If not defined, those interrupts
252 * will be sent to INTR0x60_NIU_BAD_THREAD.
253 *
254 * INTR0x60_NIU_RX_EXTRA_HANDLER
255 * If defined (as assembler code), the code will be executed
256 * at the end of the trap handler in hyperprivileged mode.
257 * The code can assume %g1 is the current thread,
258 * %g2 is the received interrupt vector number, and
259 * %g3 is the RX DMA channel number.
260 *
261 * INTR0x60_NIU_RX_FATAL_HANDLER
262 * If defined (as assembler code), the code will be executed
263 * (in hyperprivileged mode) as soon as the trap handler
264 * determines that the NIU RX interrupt was caused by a
265 * fatal error. The code must finish with a "retry" instruction.
266 * The code can assume %g1 is the current thread,
267 * %g2 is the received interrupt vector number,
268 * %g3 is the RX DMA channel number,
269 * %g4 is the address of the RX_DMA_CTL_STAT register, and
270 * %g5 is the value of the RX_DMA_CTL_STAT register.
271 *
272 * INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL
273 * If defined, and the trap handler determines that the
274 * NIU RX interrupt was caused by a fatal error, the RX DMA
275 * channel will be reset in a way that is compatible with
276 * the tsotool NIU RX interrupt macro. Afterward, the
277 * INTR0x60_NIU_RX_EXTRA_HANDLER code (if any) will be executed.
278 * INTR0x60_NIU_RX_FATAL_HANDLER preempts this macro.
279 * If the trap handler determines that an NIU RX interrupt was
280 * caused by a fatal error and neither INTR0x60_NIU_RX_FATAL_HANDLER
281 * nor INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL are defined, then the
282 * trap handler will execute EXIT_BAD.
283 *
284 *
285 *
286 * INTR0x60_NIU_TX_IV_<I>=<IVN> (<I> = 0-15)
287 * If defined, interrupts coming from NIU Logical Device Group <IVN>
288 * are permitted and will be assigned to interrupt vector <IVN>.
289 * The interrupt must be caused by TX DMA.
290 * (Max of 16 interrupt vectors can be used for this purpose;
291 * could be increased if needed.)
292 * NOTE: The interrupt vector number is always the same
293 * as the Logical Device Group. The System Interrupt
294 * Data register in the NIU for the LDG will be
295 * initialized to <IVN>+64
296 *
297 * INTR0x60_NIU_TX_DMA_<I>=<N> (<I> = 0-15; <N> = 0-15)
298 * Must be defined if INTR0x60_NIU_TX_IV_<I> is defined (same <I>).
299 * Interrupts coming from NIU TX DMA Channel <N>
300 * will be assigned to the NIU Logical Device Group specified
301 * by INTR0x60_NIU_TX_IV_<I> (same <I>).
302 *
303 * INTR0x60_NIU_TX_THREAD_<I>=<T> (<I> = 0-15)
304 * If defined, interrupts coming from NIU Logical Device Group
305 * specified by INTR0x60_NIU_TX_IV_<I> (same <I>) will be sent to
306 * thread <T>. If not defined, those interrupts
307 * will be sent to INTR0x60_NIU_BAD_THREAD.
308 *
309 * INTR0x60_NIU_TX_EXTRA_HANDLER
310 * If defined (as assembler code), the code will be executed
311 * at the end of the trap handler in hyperprivileged mode.
312 * The code can assume %g1 is the current thread,
313 * %g2 is the received interrupt vector number, and
314 * %g3 is the TX DMA channel number.
315 *
316 *
317 *
318 * INTR0x60_SSI_ERR_IV=<IVN>
319 * If defined, interrupt vector <IVN> is used for SSI error
320 * interrupts. If not defined, SSI error interrupts will
321 * be assigned to INTR0x60_BAD_IV.
322 *
323 * INTR0x60_SSI_ERR_THREAD=<T>
324 * If defined, thread <T> is used for SSI error
325 * interrupts. If not defined, SSI error interrupts will
326 * be assigned to INTR0x60_BAD_THREAD.
327 *
328 * INTR0x60_SSI_ERR_EXTRA_HANDLER
329 * If defined (as assembler code), the code will be executed
330 * at the end of the trap handler in hyperprivileged mode.
331 * The code can assume %g1 is the current thread, and
332 * %g2 is the received interrupt vector number
333 *
334 *
335 *
336 * INTR0x60_SSI_INT_IV=<IVN>
337 * If defined, interrupt vector <IVN> is used for SSI_EXT_INT_L
338 * interrupts. If not defined, SSI_EXT_INT_L interrupts will
339 * be assigned to INTR0x60_BAD_IV.
340 *
341 * INTR0x60_SSI_INT_THREAD=<T>
342 * If defined, thread <T> is used for SSI_EXT_INT_L
343 * interrupts. If not defined, SSI_EXT_INT_L interrupts will
344 * be assigned to INTR0x60_BAD_THREAD.
345 *
346 * INTR0x60_SSI_INT_EXTRA_HANDLER
347 * If defined (as assembler code), the code will be executed
348 * at the end of the trap handler in hyperprivileged mode.
349 * The code can assume %g1 is the current thread, and
350 * %g2 is the received interrupt vector number
351 *
352 */
353
354#ifndef INTR0x60_BAD_IV
355#define INTR0x60_BAD_IV 9
356#endif /* INTR0x60_BAD_IV */
357
358#ifndef INTR0x60_BAD_THREAD
359#define INTR0x60_BAD_THREAD 0
360#endif /* INTR0x60_BAD_THREAD */
361
362#ifndef INTR0x60_MONDO_BAD_THREAD
363#define INTR0x60_MONDO_BAD_THREAD INTR0x60_BAD_THREAD
364#endif /* INTR0x60_MONDO_BAD_THREAD */
365
366#ifndef INTR0x60_NIU_BAD_THREAD
367#define INTR0x60_NIU_BAD_THREAD INTR0x60_BAD_THREAD
368#endif /* INTR0x60_NIU_BAD_THREAD */
369
370
371/****************************************/
372#ifndef INTR0x60_SSI_ERR_IV
373#define INTR0x60_SSI_ERR_IV INTR0x60_BAD_IV
374#endif /* INTR0x60_SSI_ERR_IV */
375
376#ifndef INTR0x60_SSI_ERR_THREAD
377#define INTR0x60_SSI_ERR_THREAD INTR0x60_BAD_THREAD
378#endif /* INTR0x60_SSI_ERR_THREAD */
379
380#ifndef INTR0x60_SSI_INT_IV
381#define INTR0x60_SSI_INT_IV INTR0x60_BAD_IV
382#endif /* INTR0x60_SSI_INT_IV */
383
384#ifndef INTR0x60_SSI_INT_THREAD
385#define INTR0x60_SSI_INT_THREAD INTR0x60_BAD_THREAD
386#endif /* INTR0x60_SSI_INT_THREAD */
387
388
389
390/****************************************/
391#if INTR0x60_MONDO_20_MODE
392#define INTR0x60_MONDO_20_MODE 1
393#else
394#define INTR0x60_MONDO_20_MODE 0
395#endif /* INTR0x60_MONDO_20_MODE */
396
397#if INTR0x60_MONDO_20_V
398#define INTR0x60_MONDO_20_V 1
399#else
400#define INTR0x60_MONDO_20_V 0
401#endif /* INTR0x60_MONDO_20_V */
402
403#ifndef INTR0x60_MONDO_20_THREAD
404#define INTR0x60_MONDO_20_THREAD INTR0x60_MONDO_BAD_THREAD
405#endif /* INTR0x60_MONDO_20_THREAD */
406
407#ifndef INTR0x60_MONDO_20_CNTRL
408#define INTR0x60_MONDO_20_CNTRL 0
409#endif /* INTR0x60_MONDO_20_CNTRL */
410
411#ifndef INTR0x60_MONDO_20_DMAEPT_ENGINE
412#define INTR0x60_MONDO_20_DMAEPT_ENGINE 1
413#endif /* INTR0x60_MONDO_20_DMAEPT_ENGINE */
414
415
416/****************************************/
417#if INTR0x60_MONDO_21_MODE
418#define INTR0x60_MONDO_21_MODE 1
419#else
420#define INTR0x60_MONDO_21_MODE 0
421#endif /* INTR0x60_MONDO_21_MODE */
422
423#if INTR0x60_MONDO_21_V
424#define INTR0x60_MONDO_21_V 1
425#else
426#define INTR0x60_MONDO_21_V 0
427#endif /* INTR0x60_MONDO_21_V */
428
429#ifndef INTR0x60_MONDO_21_THREAD
430#define INTR0x60_MONDO_21_THREAD INTR0x60_MONDO_BAD_THREAD
431#endif /* INTR0x60_MONDO_21_THREAD */
432
433#ifndef INTR0x60_MONDO_21_CNTRL
434#define INTR0x60_MONDO_21_CNTRL 0
435#endif /* INTR0x60_MONDO_21_CNTRL */
436
437#ifndef INTR0x60_MONDO_21_DMAEPT_ENGINE
438#define INTR0x60_MONDO_21_DMAEPT_ENGINE 2
439#endif /* INTR0x60_MONDO_21_DMAEPT_ENGINE */
440
441
442/****************************************/
443#if INTR0x60_MONDO_22_MODE
444#define INTR0x60_MONDO_22_MODE 1
445#else
446#define INTR0x60_MONDO_22_MODE 0
447#endif /* INTR0x60_MONDO_22_MODE */
448
449#if INTR0x60_MONDO_22_V
450#define INTR0x60_MONDO_22_V 1
451#else
452#define INTR0x60_MONDO_22_V 0
453#endif /* INTR0x60_MONDO_22_V */
454
455#ifndef INTR0x60_MONDO_22_THREAD
456#define INTR0x60_MONDO_22_THREAD INTR0x60_MONDO_BAD_THREAD
457#endif /* INTR0x60_MONDO_22_THREAD */
458
459#ifndef INTR0x60_MONDO_22_CNTRL
460#define INTR0x60_MONDO_22_CNTRL 0
461#endif /* INTR0x60_MONDO_22_CNTRL */
462
463#ifndef INTR0x60_MONDO_22_DMAEPT_ENGINE
464#define INTR0x60_MONDO_22_DMAEPT_ENGINE 3
465#endif /* INTR0x60_MONDO_22_DMAEPT_ENGINE */
466
467
468/****************************************/
469#if INTR0x60_MONDO_23_MODE
470#define INTR0x60_MONDO_23_MODE 1
471#else
472#define INTR0x60_MONDO_23_MODE 0
473#endif /* INTR0x60_MONDO_23_MODE */
474
475#if INTR0x60_MONDO_23_V
476#define INTR0x60_MONDO_23_V 1
477#else
478#define INTR0x60_MONDO_23_V 0
479#endif /* INTR0x60_MONDO_23_V */
480
481#ifndef INTR0x60_MONDO_23_THREAD
482#define INTR0x60_MONDO_23_THREAD INTR0x60_MONDO_BAD_THREAD
483#endif /* INTR0x60_MONDO_23_THREAD */
484
485#ifndef INTR0x60_MONDO_23_CNTRL
486#define INTR0x60_MONDO_23_CNTRL 0
487#endif /* INTR0x60_MONDO_23_CNTRL */
488
489#ifndef INTR0x60_MONDO_23_DMAEPT_ENGINE
490#define INTR0x60_MONDO_23_DMAEPT_ENGINE 4
491#endif /* INTR0x60_MONDO_23_DMAEPT_ENGINE */
492
493
494/****************************************/
495#if INTR0x60_MONDO_24_MODE
496#define INTR0x60_MONDO_24_MODE 1
497#else
498#define INTR0x60_MONDO_24_MODE 0
499#endif /* INTR0x60_MONDO_24_MODE */
500
501#if INTR0x60_MONDO_24_V
502#define INTR0x60_MONDO_24_V 1
503#else
504#define INTR0x60_MONDO_24_V 0
505#endif /* INTR0x60_MONDO_24_V */
506
507#ifndef INTR0x60_MONDO_24_THREAD
508#define INTR0x60_MONDO_24_THREAD INTR0x60_MONDO_BAD_THREAD
509#endif /* INTR0x60_MONDO_24_THREAD */
510
511#ifndef INTR0x60_MONDO_24_CNTRL
512#define INTR0x60_MONDO_24_CNTRL 0
513#endif /* INTR0x60_MONDO_24_CNTRL */
514
515#ifndef INTR0x60_MONDO_24_DMAEPT_ENGINE
516#define INTR0x60_MONDO_24_DMAEPT_ENGINE 1
517#endif /* INTR0x60_MONDO_24_DMAEPT_ENGINE */
518
519
520/****************************************/
521#if INTR0x60_MONDO_25_MODE
522#define INTR0x60_MONDO_25_MODE 1
523#else
524#define INTR0x60_MONDO_25_MODE 0
525#endif /* INTR0x60_MONDO_25_MODE */
526
527#if INTR0x60_MONDO_25_V
528#define INTR0x60_MONDO_25_V 1
529#else
530#define INTR0x60_MONDO_25_V 0
531#endif /* INTR0x60_MONDO_25_V */
532
533#ifndef INTR0x60_MONDO_25_THREAD
534#define INTR0x60_MONDO_25_THREAD INTR0x60_MONDO_BAD_THREAD
535#endif /* INTR0x60_MONDO_25_THREAD */
536
537#ifndef INTR0x60_MONDO_25_CNTRL
538#define INTR0x60_MONDO_25_CNTRL 0
539#endif /* INTR0x60_MONDO_25_CNTRL */
540
541#ifndef INTR0x60_MONDO_25_DMAEPT_ENGINE
542#define INTR0x60_MONDO_25_DMAEPT_ENGINE 2
543#endif /* INTR0x60_MONDO_25_DMAEPT_ENGINE */
544
545
546/****************************************/
547#if INTR0x60_MONDO_26_MODE
548#define INTR0x60_MONDO_26_MODE 1
549#else
550#define INTR0x60_MONDO_26_MODE 0
551#endif /* INTR0x60_MONDO_26_MODE */
552
553#if INTR0x60_MONDO_26_V
554#define INTR0x60_MONDO_26_V 1
555#else
556#define INTR0x60_MONDO_26_V 0
557#endif /* INTR0x60_MONDO_26_V */
558
559#ifndef INTR0x60_MONDO_26_THREAD
560#define INTR0x60_MONDO_26_THREAD INTR0x60_MONDO_BAD_THREAD
561#endif /* INTR0x60_MONDO_26_THREAD */
562
563#ifndef INTR0x60_MONDO_26_CNTRL
564#define INTR0x60_MONDO_26_CNTRL 0
565#endif /* INTR0x60_MONDO_26_CNTRL */
566
567#ifndef INTR0x60_MONDO_26_DMAEPT_ENGINE
568#define INTR0x60_MONDO_26_DMAEPT_ENGINE 3
569#endif /* INTR0x60_MONDO_26_DMAEPT_ENGINE */
570
571
572/****************************************/
573#if INTR0x60_MONDO_27_MODE
574#define INTR0x60_MONDO_27_MODE 1
575#else
576#define INTR0x60_MONDO_27_MODE 0
577#endif /* INTR0x60_MONDO_27_MODE */
578
579#if INTR0x60_MONDO_27_V
580#define INTR0x60_MONDO_27_V 1
581#else
582#define INTR0x60_MONDO_27_V 0
583#endif /* INTR0x60_MONDO_27_V */
584
585#ifndef INTR0x60_MONDO_27_THREAD
586#define INTR0x60_MONDO_27_THREAD INTR0x60_MONDO_BAD_THREAD
587#endif /* INTR0x60_MONDO_27_THREAD */
588
589#ifndef INTR0x60_MONDO_27_CNTRL
590#define INTR0x60_MONDO_27_CNTRL 0
591#endif /* INTR0x60_MONDO_27_CNTRL */
592
593#ifndef INTR0x60_MONDO_27_DMAEPT_ENGINE
594#define INTR0x60_MONDO_27_DMAEPT_ENGINE 4
595#endif /* INTR0x60_MONDO_27_DMAEPT_ENGINE */
596
597
598/****************************************/
599#if INTR0x60_MONDO_28_MODE
600#define INTR0x60_MONDO_28_MODE 1
601#else
602#define INTR0x60_MONDO_28_MODE 0
603#endif /* INTR0x60_MONDO_28_MODE */
604
605#if INTR0x60_MONDO_28_V
606#define INTR0x60_MONDO_28_V 1
607#else
608#define INTR0x60_MONDO_28_V 0
609#endif /* INTR0x60_MONDO_28_V */
610
611#ifndef INTR0x60_MONDO_28_THREAD
612#define INTR0x60_MONDO_28_THREAD INTR0x60_MONDO_BAD_THREAD
613#endif /* INTR0x60_MONDO_28_THREAD */
614
615#ifndef INTR0x60_MONDO_28_CNTRL
616#define INTR0x60_MONDO_28_CNTRL 0
617#endif /* INTR0x60_MONDO_28_CNTRL */
618
619#ifndef INTR0x60_MONDO_28_DMAEPT_ENGINE
620#define INTR0x60_MONDO_28_DMAEPT_ENGINE 1
621#endif /* INTR0x60_MONDO_28_DMAEPT_ENGINE */
622
623
624/****************************************/
625#if INTR0x60_MONDO_29_MODE
626#define INTR0x60_MONDO_29_MODE 1
627#else
628#define INTR0x60_MONDO_29_MODE 0
629#endif /* INTR0x60_MONDO_29_MODE */
630
631#if INTR0x60_MONDO_29_V
632#define INTR0x60_MONDO_29_V 1
633#else
634#define INTR0x60_MONDO_29_V 0
635#endif /* INTR0x60_MONDO_29_V */
636
637#ifndef INTR0x60_MONDO_29_THREAD
638#define INTR0x60_MONDO_29_THREAD INTR0x60_MONDO_BAD_THREAD
639#endif /* INTR0x60_MONDO_29_THREAD */
640
641#ifndef INTR0x60_MONDO_29_CNTRL
642#define INTR0x60_MONDO_29_CNTRL 0
643#endif /* INTR0x60_MONDO_29_CNTRL */
644
645#ifndef INTR0x60_MONDO_29_DMAEPT_ENGINE
646#define INTR0x60_MONDO_29_DMAEPT_ENGINE 2
647#endif /* INTR0x60_MONDO_29_DMAEPT_ENGINE */
648
649
650/****************************************/
651#if INTR0x60_MONDO_30_MODE
652#define INTR0x60_MONDO_30_MODE 1
653#else
654#define INTR0x60_MONDO_30_MODE 0
655#endif /* INTR0x60_MONDO_30_MODE */
656
657#if INTR0x60_MONDO_30_V
658#define INTR0x60_MONDO_30_V 1
659#else
660#define INTR0x60_MONDO_30_V 0
661#endif /* INTR0x60_MONDO_30_V */
662
663#ifndef INTR0x60_MONDO_30_THREAD
664#define INTR0x60_MONDO_30_THREAD INTR0x60_MONDO_BAD_THREAD
665#endif /* INTR0x60_MONDO_30_THREAD */
666
667#ifndef INTR0x60_MONDO_30_CNTRL
668#define INTR0x60_MONDO_30_CNTRL 0
669#endif /* INTR0x60_MONDO_30_CNTRL */
670
671#ifndef INTR0x60_MONDO_30_DMAEPT_ENGINE
672#define INTR0x60_MONDO_30_DMAEPT_ENGINE 3
673#endif /* INTR0x60_MONDO_30_DMAEPT_ENGINE */
674
675
676/****************************************/
677#if INTR0x60_MONDO_31_MODE
678#define INTR0x60_MONDO_31_MODE 1
679#else
680#define INTR0x60_MONDO_31_MODE 0
681#endif /* INTR0x60_MONDO_31_MODE */
682
683#if INTR0x60_MONDO_31_V
684#define INTR0x60_MONDO_31_V 1
685#else
686#define INTR0x60_MONDO_31_V 0
687#endif /* INTR0x60_MONDO_31_V */
688
689#ifndef INTR0x60_MONDO_31_THREAD
690#define INTR0x60_MONDO_31_THREAD INTR0x60_MONDO_BAD_THREAD
691#endif /* INTR0x60_MONDO_31_THREAD */
692
693#ifndef INTR0x60_MONDO_31_CNTRL
694#define INTR0x60_MONDO_31_CNTRL 0
695#endif /* INTR0x60_MONDO_31_CNTRL */
696
697#ifndef INTR0x60_MONDO_31_DMAEPT_ENGINE
698#define INTR0x60_MONDO_31_DMAEPT_ENGINE 4
699#endif /* INTR0x60_MONDO_31_DMAEPT_ENGINE */
700
701
702/****************************************/
703#if INTR0x60_MONDO_32_MODE
704#define INTR0x60_MONDO_32_MODE 1
705#else
706#define INTR0x60_MONDO_32_MODE 0
707#endif /* INTR0x60_MONDO_32_MODE */
708
709#if INTR0x60_MONDO_32_V
710#define INTR0x60_MONDO_32_V 1
711#else
712#define INTR0x60_MONDO_32_V 0
713#endif /* INTR0x60_MONDO_32_V */
714
715#ifndef INTR0x60_MONDO_32_THREAD
716#define INTR0x60_MONDO_32_THREAD INTR0x60_MONDO_BAD_THREAD
717#endif /* INTR0x60_MONDO_32_THREAD */
718
719#ifndef INTR0x60_MONDO_32_CNTRL
720#define INTR0x60_MONDO_32_CNTRL 0
721#endif /* INTR0x60_MONDO_32_CNTRL */
722
723#ifndef INTR0x60_MONDO_32_DMAEPT_ENGINE
724#define INTR0x60_MONDO_32_DMAEPT_ENGINE 1
725#endif /* INTR0x60_MONDO_32_DMAEPT_ENGINE */
726
727
728/****************************************/
729#if INTR0x60_MONDO_33_MODE
730#define INTR0x60_MONDO_33_MODE 1
731#else
732#define INTR0x60_MONDO_33_MODE 0
733#endif /* INTR0x60_MONDO_33_MODE */
734
735#if INTR0x60_MONDO_33_V
736#define INTR0x60_MONDO_33_V 1
737#else
738#define INTR0x60_MONDO_33_V 0
739#endif /* INTR0x60_MONDO_33_V */
740
741#ifndef INTR0x60_MONDO_33_THREAD
742#define INTR0x60_MONDO_33_THREAD INTR0x60_MONDO_BAD_THREAD
743#endif /* INTR0x60_MONDO_33_THREAD */
744
745#ifndef INTR0x60_MONDO_33_CNTRL
746#define INTR0x60_MONDO_33_CNTRL 0
747#endif /* INTR0x60_MONDO_33_CNTRL */
748
749#ifndef INTR0x60_MONDO_33_DMAEPT_ENGINE
750#define INTR0x60_MONDO_33_DMAEPT_ENGINE 2
751#endif /* INTR0x60_MONDO_33_DMAEPT_ENGINE */
752
753
754/****************************************/
755#if INTR0x60_MONDO_34_MODE
756#define INTR0x60_MONDO_34_MODE 1
757#else
758#define INTR0x60_MONDO_34_MODE 0
759#endif /* INTR0x60_MONDO_34_MODE */
760
761#if INTR0x60_MONDO_34_V
762#define INTR0x60_MONDO_34_V 1
763#else
764#define INTR0x60_MONDO_34_V 0
765#endif /* INTR0x60_MONDO_34_V */
766
767#ifndef INTR0x60_MONDO_34_THREAD
768#define INTR0x60_MONDO_34_THREAD INTR0x60_MONDO_BAD_THREAD
769#endif /* INTR0x60_MONDO_34_THREAD */
770
771#ifndef INTR0x60_MONDO_34_CNTRL
772#define INTR0x60_MONDO_34_CNTRL 0
773#endif /* INTR0x60_MONDO_34_CNTRL */
774
775#ifndef INTR0x60_MONDO_34_DMAEPT_ENGINE
776#define INTR0x60_MONDO_34_DMAEPT_ENGINE 3
777#endif /* INTR0x60_MONDO_34_DMAEPT_ENGINE */
778
779
780/****************************************/
781#if INTR0x60_MONDO_35_MODE
782#define INTR0x60_MONDO_35_MODE 1
783#else
784#define INTR0x60_MONDO_35_MODE 0
785#endif /* INTR0x60_MONDO_35_MODE */
786
787#if INTR0x60_MONDO_35_V
788#define INTR0x60_MONDO_35_V 1
789#else
790#define INTR0x60_MONDO_35_V 0
791#endif /* INTR0x60_MONDO_35_V */
792
793#ifndef INTR0x60_MONDO_35_THREAD
794#define INTR0x60_MONDO_35_THREAD INTR0x60_MONDO_BAD_THREAD
795#endif /* INTR0x60_MONDO_35_THREAD */
796
797#ifndef INTR0x60_MONDO_35_CNTRL
798#define INTR0x60_MONDO_35_CNTRL 0
799#endif /* INTR0x60_MONDO_35_CNTRL */
800
801#ifndef INTR0x60_MONDO_35_DMAEPT_ENGINE
802#define INTR0x60_MONDO_35_DMAEPT_ENGINE 4
803#endif /* INTR0x60_MONDO_35_DMAEPT_ENGINE */
804
805
806/****************************************/
807#if INTR0x60_MONDO_36_MODE
808#define INTR0x60_MONDO_36_MODE 1
809#else
810#define INTR0x60_MONDO_36_MODE 0
811#endif /* INTR0x60_MONDO_36_MODE */
812
813#if INTR0x60_MONDO_36_V
814#define INTR0x60_MONDO_36_V 1
815#else
816#define INTR0x60_MONDO_36_V 0
817#endif /* INTR0x60_MONDO_36_V */
818
819#ifndef INTR0x60_MONDO_36_THREAD
820#define INTR0x60_MONDO_36_THREAD INTR0x60_MONDO_BAD_THREAD
821#endif /* INTR0x60_MONDO_36_THREAD */
822
823#ifndef INTR0x60_MONDO_36_CNTRL
824#define INTR0x60_MONDO_36_CNTRL 0
825#endif /* INTR0x60_MONDO_36_CNTRL */
826
827#ifndef INTR0x60_MONDO_36_DMAEPT_ENGINE
828#define INTR0x60_MONDO_36_DMAEPT_ENGINE 1
829#endif /* INTR0x60_MONDO_36_DMAEPT_ENGINE */
830
831
832/****************************************/
833#if INTR0x60_MONDO_37_MODE
834#define INTR0x60_MONDO_37_MODE 1
835#else
836#define INTR0x60_MONDO_37_MODE 0
837#endif /* INTR0x60_MONDO_37_MODE */
838
839#if INTR0x60_MONDO_37_V
840#define INTR0x60_MONDO_37_V 1
841#else
842#define INTR0x60_MONDO_37_V 0
843#endif /* INTR0x60_MONDO_37_V */
844
845#ifndef INTR0x60_MONDO_37_THREAD
846#define INTR0x60_MONDO_37_THREAD INTR0x60_MONDO_BAD_THREAD
847#endif /* INTR0x60_MONDO_37_THREAD */
848
849#ifndef INTR0x60_MONDO_37_CNTRL
850#define INTR0x60_MONDO_37_CNTRL 0
851#endif /* INTR0x60_MONDO_37_CNTRL */
852
853#ifndef INTR0x60_MONDO_37_DMAEPT_ENGINE
854#define INTR0x60_MONDO_37_DMAEPT_ENGINE 2
855#endif /* INTR0x60_MONDO_37_DMAEPT_ENGINE */
856
857
858/****************************************/
859#if INTR0x60_MONDO_38_MODE
860#define INTR0x60_MONDO_38_MODE 1
861#else
862#define INTR0x60_MONDO_38_MODE 0
863#endif /* INTR0x60_MONDO_38_MODE */
864
865#if INTR0x60_MONDO_38_V
866#define INTR0x60_MONDO_38_V 1
867#else
868#define INTR0x60_MONDO_38_V 0
869#endif /* INTR0x60_MONDO_38_V */
870
871#ifndef INTR0x60_MONDO_38_THREAD
872#define INTR0x60_MONDO_38_THREAD INTR0x60_MONDO_BAD_THREAD
873#endif /* INTR0x60_MONDO_38_THREAD */
874
875#ifndef INTR0x60_MONDO_38_CNTRL
876#define INTR0x60_MONDO_38_CNTRL 0
877#endif /* INTR0x60_MONDO_38_CNTRL */
878
879#ifndef INTR0x60_MONDO_38_DMAEPT_ENGINE
880#define INTR0x60_MONDO_38_DMAEPT_ENGINE 3
881#endif /* INTR0x60_MONDO_38_DMAEPT_ENGINE */
882
883
884/****************************************/
885#if INTR0x60_MONDO_39_MODE
886#define INTR0x60_MONDO_39_MODE 1
887#else
888#define INTR0x60_MONDO_39_MODE 0
889#endif /* INTR0x60_MONDO_39_MODE */
890
891#if INTR0x60_MONDO_39_V
892#define INTR0x60_MONDO_39_V 1
893#else
894#define INTR0x60_MONDO_39_V 0
895#endif /* INTR0x60_MONDO_39_V */
896
897#ifndef INTR0x60_MONDO_39_THREAD
898#define INTR0x60_MONDO_39_THREAD INTR0x60_MONDO_BAD_THREAD
899#endif /* INTR0x60_MONDO_39_THREAD */
900
901#ifndef INTR0x60_MONDO_39_CNTRL
902#define INTR0x60_MONDO_39_CNTRL 0
903#endif /* INTR0x60_MONDO_39_CNTRL */
904
905#ifndef INTR0x60_MONDO_39_DMAEPT_ENGINE
906#define INTR0x60_MONDO_39_DMAEPT_ENGINE 4
907#endif /* INTR0x60_MONDO_39_DMAEPT_ENGINE */
908
909
910/****************************************/
911#if INTR0x60_MONDO_40_MODE
912#define INTR0x60_MONDO_40_MODE 1
913#else
914#define INTR0x60_MONDO_40_MODE 0
915#endif /* INTR0x60_MONDO_40_MODE */
916
917#if INTR0x60_MONDO_40_V
918#define INTR0x60_MONDO_40_V 1
919#else
920#define INTR0x60_MONDO_40_V 0
921#endif /* INTR0x60_MONDO_40_V */
922
923#ifndef INTR0x60_MONDO_40_THREAD
924#define INTR0x60_MONDO_40_THREAD INTR0x60_MONDO_BAD_THREAD
925#endif /* INTR0x60_MONDO_40_THREAD */
926
927#ifndef INTR0x60_MONDO_40_CNTRL
928#define INTR0x60_MONDO_40_CNTRL 0
929#endif /* INTR0x60_MONDO_40_CNTRL */
930
931#ifndef INTR0x60_MONDO_40_DMAEPT_ENGINE
932#define INTR0x60_MONDO_40_DMAEPT_ENGINE 1
933#endif /* INTR0x60_MONDO_40_DMAEPT_ENGINE */
934
935
936/****************************************/
937#if INTR0x60_MONDO_41_MODE
938#define INTR0x60_MONDO_41_MODE 1
939#else
940#define INTR0x60_MONDO_41_MODE 0
941#endif /* INTR0x60_MONDO_41_MODE */
942
943#if INTR0x60_MONDO_41_V
944#define INTR0x60_MONDO_41_V 1
945#else
946#define INTR0x60_MONDO_41_V 0
947#endif /* INTR0x60_MONDO_41_V */
948
949#ifndef INTR0x60_MONDO_41_THREAD
950#define INTR0x60_MONDO_41_THREAD INTR0x60_MONDO_BAD_THREAD
951#endif /* INTR0x60_MONDO_41_THREAD */
952
953#ifndef INTR0x60_MONDO_41_CNTRL
954#define INTR0x60_MONDO_41_CNTRL 0
955#endif /* INTR0x60_MONDO_41_CNTRL */
956
957#ifndef INTR0x60_MONDO_41_DMAEPT_ENGINE
958#define INTR0x60_MONDO_41_DMAEPT_ENGINE 2
959#endif /* INTR0x60_MONDO_41_DMAEPT_ENGINE */
960
961
962/****************************************/
963#if INTR0x60_MONDO_42_MODE
964#define INTR0x60_MONDO_42_MODE 1
965#else
966#define INTR0x60_MONDO_42_MODE 0
967#endif /* INTR0x60_MONDO_42_MODE */
968
969#if INTR0x60_MONDO_42_V
970#define INTR0x60_MONDO_42_V 1
971#else
972#define INTR0x60_MONDO_42_V 0
973#endif /* INTR0x60_MONDO_42_V */
974
975#ifndef INTR0x60_MONDO_42_THREAD
976#define INTR0x60_MONDO_42_THREAD INTR0x60_MONDO_BAD_THREAD
977#endif /* INTR0x60_MONDO_42_THREAD */
978
979#ifndef INTR0x60_MONDO_42_CNTRL
980#define INTR0x60_MONDO_42_CNTRL 0
981#endif /* INTR0x60_MONDO_42_CNTRL */
982
983#ifndef INTR0x60_MONDO_42_DMAEPT_ENGINE
984#define INTR0x60_MONDO_42_DMAEPT_ENGINE 3
985#endif /* INTR0x60_MONDO_42_DMAEPT_ENGINE */
986
987
988/****************************************/
989#if INTR0x60_MONDO_43_MODE
990#define INTR0x60_MONDO_43_MODE 1
991#else
992#define INTR0x60_MONDO_43_MODE 0
993#endif /* INTR0x60_MONDO_43_MODE */
994
995#if INTR0x60_MONDO_43_V
996#define INTR0x60_MONDO_43_V 1
997#else
998#define INTR0x60_MONDO_43_V 0
999#endif /* INTR0x60_MONDO_43_V */
1000
1001#ifndef INTR0x60_MONDO_43_THREAD
1002#define INTR0x60_MONDO_43_THREAD INTR0x60_MONDO_BAD_THREAD
1003#endif /* INTR0x60_MONDO_43_THREAD */
1004
1005#ifndef INTR0x60_MONDO_43_CNTRL
1006#define INTR0x60_MONDO_43_CNTRL 0
1007#endif /* INTR0x60_MONDO_43_CNTRL */
1008
1009#ifndef INTR0x60_MONDO_43_DMAEPT_ENGINE
1010#define INTR0x60_MONDO_43_DMAEPT_ENGINE 4
1011#endif /* INTR0x60_MONDO_43_DMAEPT_ENGINE */
1012
1013
1014/****************************************/
1015#if INTR0x60_MONDO_44_MODE
1016#define INTR0x60_MONDO_44_MODE 1
1017#else
1018#define INTR0x60_MONDO_44_MODE 0
1019#endif /* INTR0x60_MONDO_44_MODE */
1020
1021#if INTR0x60_MONDO_44_V
1022#define INTR0x60_MONDO_44_V 1
1023#else
1024#define INTR0x60_MONDO_44_V 0
1025#endif /* INTR0x60_MONDO_44_V */
1026
1027#ifndef INTR0x60_MONDO_44_THREAD
1028#define INTR0x60_MONDO_44_THREAD INTR0x60_MONDO_BAD_THREAD
1029#endif /* INTR0x60_MONDO_44_THREAD */
1030
1031#ifndef INTR0x60_MONDO_44_CNTRL
1032#define INTR0x60_MONDO_44_CNTRL 0
1033#endif /* INTR0x60_MONDO_44_CNTRL */
1034
1035#ifndef INTR0x60_MONDO_44_DMAEPT_ENGINE
1036#define INTR0x60_MONDO_44_DMAEPT_ENGINE 1
1037#endif /* INTR0x60_MONDO_44_DMAEPT_ENGINE */
1038
1039
1040/****************************************/
1041#if INTR0x60_MONDO_45_MODE
1042#define INTR0x60_MONDO_45_MODE 1
1043#else
1044#define INTR0x60_MONDO_45_MODE 0
1045#endif /* INTR0x60_MONDO_45_MODE */
1046
1047#if INTR0x60_MONDO_45_V
1048#define INTR0x60_MONDO_45_V 1
1049#else
1050#define INTR0x60_MONDO_45_V 0
1051#endif /* INTR0x60_MONDO_45_V */
1052
1053#ifndef INTR0x60_MONDO_45_THREAD
1054#define INTR0x60_MONDO_45_THREAD INTR0x60_MONDO_BAD_THREAD
1055#endif /* INTR0x60_MONDO_45_THREAD */
1056
1057#ifndef INTR0x60_MONDO_45_CNTRL
1058#define INTR0x60_MONDO_45_CNTRL 0
1059#endif /* INTR0x60_MONDO_45_CNTRL */
1060
1061#ifndef INTR0x60_MONDO_45_DMAEPT_ENGINE
1062#define INTR0x60_MONDO_45_DMAEPT_ENGINE 2
1063#endif /* INTR0x60_MONDO_45_DMAEPT_ENGINE */
1064
1065
1066/****************************************/
1067#if INTR0x60_MONDO_46_MODE
1068#define INTR0x60_MONDO_46_MODE 1
1069#else
1070#define INTR0x60_MONDO_46_MODE 0
1071#endif /* INTR0x60_MONDO_46_MODE */
1072
1073#if INTR0x60_MONDO_46_V
1074#define INTR0x60_MONDO_46_V 1
1075#else
1076#define INTR0x60_MONDO_46_V 0
1077#endif /* INTR0x60_MONDO_46_V */
1078
1079#ifndef INTR0x60_MONDO_46_THREAD
1080#define INTR0x60_MONDO_46_THREAD INTR0x60_MONDO_BAD_THREAD
1081#endif /* INTR0x60_MONDO_46_THREAD */
1082
1083#ifndef INTR0x60_MONDO_46_CNTRL
1084#define INTR0x60_MONDO_46_CNTRL 0
1085#endif /* INTR0x60_MONDO_46_CNTRL */
1086
1087#ifndef INTR0x60_MONDO_46_DMAEPT_ENGINE
1088#define INTR0x60_MONDO_46_DMAEPT_ENGINE 3
1089#endif /* INTR0x60_MONDO_46_DMAEPT_ENGINE */
1090
1091
1092/****************************************/
1093#if INTR0x60_MONDO_47_MODE
1094#define INTR0x60_MONDO_47_MODE 1
1095#else
1096#define INTR0x60_MONDO_47_MODE 0
1097#endif /* INTR0x60_MONDO_47_MODE */
1098
1099#if INTR0x60_MONDO_47_V
1100#define INTR0x60_MONDO_47_V 1
1101#else
1102#define INTR0x60_MONDO_47_V 0
1103#endif /* INTR0x60_MONDO_47_V */
1104
1105#ifndef INTR0x60_MONDO_47_THREAD
1106#define INTR0x60_MONDO_47_THREAD INTR0x60_MONDO_BAD_THREAD
1107#endif /* INTR0x60_MONDO_47_THREAD */
1108
1109#ifndef INTR0x60_MONDO_47_CNTRL
1110#define INTR0x60_MONDO_47_CNTRL 0
1111#endif /* INTR0x60_MONDO_47_CNTRL */
1112
1113#ifndef INTR0x60_MONDO_47_DMAEPT_ENGINE
1114#define INTR0x60_MONDO_47_DMAEPT_ENGINE 4
1115#endif /* INTR0x60_MONDO_47_DMAEPT_ENGINE */
1116
1117
1118/****************************************/
1119#if INTR0x60_MONDO_48_MODE
1120#define INTR0x60_MONDO_48_MODE 1
1121#else
1122#define INTR0x60_MONDO_48_MODE 0
1123#endif /* INTR0x60_MONDO_48_MODE */
1124
1125#if INTR0x60_MONDO_48_V
1126#define INTR0x60_MONDO_48_V 1
1127#else
1128#define INTR0x60_MONDO_48_V 0
1129#endif /* INTR0x60_MONDO_48_V */
1130
1131#ifndef INTR0x60_MONDO_48_THREAD
1132#define INTR0x60_MONDO_48_THREAD INTR0x60_MONDO_BAD_THREAD
1133#endif /* INTR0x60_MONDO_48_THREAD */
1134
1135#ifndef INTR0x60_MONDO_48_CNTRL
1136#define INTR0x60_MONDO_48_CNTRL 0
1137#endif /* INTR0x60_MONDO_48_CNTRL */
1138
1139#ifndef INTR0x60_MONDO_48_DMAEPT_ENGINE
1140#define INTR0x60_MONDO_48_DMAEPT_ENGINE 1
1141#endif /* INTR0x60_MONDO_48_DMAEPT_ENGINE */
1142
1143
1144/****************************************/
1145#if INTR0x60_MONDO_49_MODE
1146#define INTR0x60_MONDO_49_MODE 1
1147#else
1148#define INTR0x60_MONDO_49_MODE 0
1149#endif /* INTR0x60_MONDO_49_MODE */
1150
1151#if INTR0x60_MONDO_49_V
1152#define INTR0x60_MONDO_49_V 1
1153#else
1154#define INTR0x60_MONDO_49_V 0
1155#endif /* INTR0x60_MONDO_49_V */
1156
1157#ifndef INTR0x60_MONDO_49_THREAD
1158#define INTR0x60_MONDO_49_THREAD INTR0x60_MONDO_BAD_THREAD
1159#endif /* INTR0x60_MONDO_49_THREAD */
1160
1161#ifndef INTR0x60_MONDO_49_CNTRL
1162#define INTR0x60_MONDO_49_CNTRL 0
1163#endif /* INTR0x60_MONDO_49_CNTRL */
1164
1165#ifndef INTR0x60_MONDO_49_DMAEPT_ENGINE
1166#define INTR0x60_MONDO_49_DMAEPT_ENGINE 2
1167#endif /* INTR0x60_MONDO_49_DMAEPT_ENGINE */
1168
1169
1170/****************************************/
1171#if INTR0x60_MONDO_50_MODE
1172#define INTR0x60_MONDO_50_MODE 1
1173#else
1174#define INTR0x60_MONDO_50_MODE 0
1175#endif /* INTR0x60_MONDO_50_MODE */
1176
1177#if INTR0x60_MONDO_50_V
1178#define INTR0x60_MONDO_50_V 1
1179#else
1180#define INTR0x60_MONDO_50_V 0
1181#endif /* INTR0x60_MONDO_50_V */
1182
1183#ifndef INTR0x60_MONDO_50_THREAD
1184#define INTR0x60_MONDO_50_THREAD INTR0x60_MONDO_BAD_THREAD
1185#endif /* INTR0x60_MONDO_50_THREAD */
1186
1187#ifndef INTR0x60_MONDO_50_CNTRL
1188#define INTR0x60_MONDO_50_CNTRL 0
1189#endif /* INTR0x60_MONDO_50_CNTRL */
1190
1191#ifndef INTR0x60_MONDO_50_DMAEPT_ENGINE
1192#define INTR0x60_MONDO_50_DMAEPT_ENGINE 3
1193#endif /* INTR0x60_MONDO_50_DMAEPT_ENGINE */
1194
1195
1196/****************************************/
1197#if INTR0x60_MONDO_51_MODE
1198#define INTR0x60_MONDO_51_MODE 1
1199#else
1200#define INTR0x60_MONDO_51_MODE 0
1201#endif /* INTR0x60_MONDO_51_MODE */
1202
1203#if INTR0x60_MONDO_51_V
1204#define INTR0x60_MONDO_51_V 1
1205#else
1206#define INTR0x60_MONDO_51_V 0
1207#endif /* INTR0x60_MONDO_51_V */
1208
1209#ifndef INTR0x60_MONDO_51_THREAD
1210#define INTR0x60_MONDO_51_THREAD INTR0x60_MONDO_BAD_THREAD
1211#endif /* INTR0x60_MONDO_51_THREAD */
1212
1213#ifndef INTR0x60_MONDO_51_CNTRL
1214#define INTR0x60_MONDO_51_CNTRL 0
1215#endif /* INTR0x60_MONDO_51_CNTRL */
1216
1217#ifndef INTR0x60_MONDO_51_DMAEPT_ENGINE
1218#define INTR0x60_MONDO_51_DMAEPT_ENGINE 4
1219#endif /* INTR0x60_MONDO_51_DMAEPT_ENGINE */
1220
1221
1222/****************************************/
1223#if INTR0x60_MONDO_52_MODE
1224#define INTR0x60_MONDO_52_MODE 1
1225#else
1226#define INTR0x60_MONDO_52_MODE 0
1227#endif /* INTR0x60_MONDO_52_MODE */
1228
1229#if INTR0x60_MONDO_52_V
1230#define INTR0x60_MONDO_52_V 1
1231#else
1232#define INTR0x60_MONDO_52_V 0
1233#endif /* INTR0x60_MONDO_52_V */
1234
1235#ifndef INTR0x60_MONDO_52_THREAD
1236#define INTR0x60_MONDO_52_THREAD INTR0x60_MONDO_BAD_THREAD
1237#endif /* INTR0x60_MONDO_52_THREAD */
1238
1239#ifndef INTR0x60_MONDO_52_CNTRL
1240#define INTR0x60_MONDO_52_CNTRL 0
1241#endif /* INTR0x60_MONDO_52_CNTRL */
1242
1243#ifndef INTR0x60_MONDO_52_DMAEPT_ENGINE
1244#define INTR0x60_MONDO_52_DMAEPT_ENGINE 1
1245#endif /* INTR0x60_MONDO_52_DMAEPT_ENGINE */
1246
1247
1248/****************************************/
1249#if INTR0x60_MONDO_53_MODE
1250#define INTR0x60_MONDO_53_MODE 1
1251#else
1252#define INTR0x60_MONDO_53_MODE 0
1253#endif /* INTR0x60_MONDO_53_MODE */
1254
1255#if INTR0x60_MONDO_53_V
1256#define INTR0x60_MONDO_53_V 1
1257#else
1258#define INTR0x60_MONDO_53_V 0
1259#endif /* INTR0x60_MONDO_53_V */
1260
1261#ifndef INTR0x60_MONDO_53_THREAD
1262#define INTR0x60_MONDO_53_THREAD INTR0x60_MONDO_BAD_THREAD
1263#endif /* INTR0x60_MONDO_53_THREAD */
1264
1265#ifndef INTR0x60_MONDO_53_CNTRL
1266#define INTR0x60_MONDO_53_CNTRL 0
1267#endif /* INTR0x60_MONDO_53_CNTRL */
1268
1269#ifndef INTR0x60_MONDO_53_DMAEPT_ENGINE
1270#define INTR0x60_MONDO_53_DMAEPT_ENGINE 2
1271#endif /* INTR0x60_MONDO_53_DMAEPT_ENGINE */
1272
1273
1274/****************************************/
1275#if INTR0x60_MONDO_54_MODE
1276#define INTR0x60_MONDO_54_MODE 1
1277#else
1278#define INTR0x60_MONDO_54_MODE 0
1279#endif /* INTR0x60_MONDO_54_MODE */
1280
1281#if INTR0x60_MONDO_54_V
1282#define INTR0x60_MONDO_54_V 1
1283#else
1284#define INTR0x60_MONDO_54_V 0
1285#endif /* INTR0x60_MONDO_54_V */
1286
1287#ifndef INTR0x60_MONDO_54_THREAD
1288#define INTR0x60_MONDO_54_THREAD INTR0x60_MONDO_BAD_THREAD
1289#endif /* INTR0x60_MONDO_54_THREAD */
1290
1291#ifndef INTR0x60_MONDO_54_CNTRL
1292#define INTR0x60_MONDO_54_CNTRL 0
1293#endif /* INTR0x60_MONDO_54_CNTRL */
1294
1295#ifndef INTR0x60_MONDO_54_DMAEPT_ENGINE
1296#define INTR0x60_MONDO_54_DMAEPT_ENGINE 3
1297#endif /* INTR0x60_MONDO_54_DMAEPT_ENGINE */
1298
1299
1300/****************************************/
1301#if INTR0x60_MONDO_55_MODE
1302#define INTR0x60_MONDO_55_MODE 1
1303#else
1304#define INTR0x60_MONDO_55_MODE 0
1305#endif /* INTR0x60_MONDO_55_MODE */
1306
1307#if INTR0x60_MONDO_55_V
1308#define INTR0x60_MONDO_55_V 1
1309#else
1310#define INTR0x60_MONDO_55_V 0
1311#endif /* INTR0x60_MONDO_55_V */
1312
1313#ifndef INTR0x60_MONDO_55_THREAD
1314#define INTR0x60_MONDO_55_THREAD INTR0x60_MONDO_BAD_THREAD
1315#endif /* INTR0x60_MONDO_55_THREAD */
1316
1317#ifndef INTR0x60_MONDO_55_CNTRL
1318#define INTR0x60_MONDO_55_CNTRL 0
1319#endif /* INTR0x60_MONDO_55_CNTRL */
1320
1321#ifndef INTR0x60_MONDO_55_DMAEPT_ENGINE
1322#define INTR0x60_MONDO_55_DMAEPT_ENGINE 4
1323#endif /* INTR0x60_MONDO_55_DMAEPT_ENGINE */
1324
1325
1326/****************************************/
1327#if INTR0x60_MONDO_56_MODE
1328#define INTR0x60_MONDO_56_MODE 1
1329#else
1330#define INTR0x60_MONDO_56_MODE 0
1331#endif /* INTR0x60_MONDO_56_MODE */
1332
1333#if INTR0x60_MONDO_56_V
1334#define INTR0x60_MONDO_56_V 1
1335#else
1336#define INTR0x60_MONDO_56_V 0
1337#endif /* INTR0x60_MONDO_56_V */
1338
1339#ifndef INTR0x60_MONDO_56_THREAD
1340#define INTR0x60_MONDO_56_THREAD INTR0x60_MONDO_BAD_THREAD
1341#endif /* INTR0x60_MONDO_56_THREAD */
1342
1343#ifndef INTR0x60_MONDO_56_CNTRL
1344#define INTR0x60_MONDO_56_CNTRL 0
1345#endif /* INTR0x60_MONDO_56_CNTRL */
1346
1347#ifndef INTR0x60_MONDO_56_DMAEPT_ENGINE
1348#define INTR0x60_MONDO_56_DMAEPT_ENGINE 1
1349#endif /* INTR0x60_MONDO_56_DMAEPT_ENGINE */
1350
1351
1352/****************************************/
1353#if INTR0x60_MONDO_57_MODE
1354#define INTR0x60_MONDO_57_MODE 1
1355#else
1356#define INTR0x60_MONDO_57_MODE 0
1357#endif /* INTR0x60_MONDO_57_MODE */
1358
1359#if INTR0x60_MONDO_57_V
1360#define INTR0x60_MONDO_57_V 1
1361#else
1362#define INTR0x60_MONDO_57_V 0
1363#endif /* INTR0x60_MONDO_57_V */
1364
1365#ifndef INTR0x60_MONDO_57_THREAD
1366#define INTR0x60_MONDO_57_THREAD INTR0x60_MONDO_BAD_THREAD
1367#endif /* INTR0x60_MONDO_57_THREAD */
1368
1369#ifndef INTR0x60_MONDO_57_CNTRL
1370#define INTR0x60_MONDO_57_CNTRL 0
1371#endif /* INTR0x60_MONDO_57_CNTRL */
1372
1373#ifndef INTR0x60_MONDO_57_DMAEPT_ENGINE
1374#define INTR0x60_MONDO_57_DMAEPT_ENGINE 2
1375#endif /* INTR0x60_MONDO_57_DMAEPT_ENGINE */
1376
1377
1378/****************************************/
1379#if INTR0x60_MONDO_58_MODE
1380#define INTR0x60_MONDO_58_MODE 1
1381#else
1382#define INTR0x60_MONDO_58_MODE 0
1383#endif /* INTR0x60_MONDO_58_MODE */
1384
1385#if INTR0x60_MONDO_58_V
1386#define INTR0x60_MONDO_58_V 1
1387#else
1388#define INTR0x60_MONDO_58_V 0
1389#endif /* INTR0x60_MONDO_58_V */
1390
1391#ifndef INTR0x60_MONDO_58_THREAD
1392#define INTR0x60_MONDO_58_THREAD INTR0x60_MONDO_BAD_THREAD
1393#endif /* INTR0x60_MONDO_58_THREAD */
1394
1395#ifndef INTR0x60_MONDO_58_CNTRL
1396#define INTR0x60_MONDO_58_CNTRL 0
1397#endif /* INTR0x60_MONDO_58_CNTRL */
1398
1399#ifndef INTR0x60_MONDO_58_DMAEPT_ENGINE
1400#define INTR0x60_MONDO_58_DMAEPT_ENGINE 3
1401#endif /* INTR0x60_MONDO_58_DMAEPT_ENGINE */
1402
1403
1404/****************************************/
1405#if INTR0x60_MONDO_59_MODE
1406#define INTR0x60_MONDO_59_MODE 1
1407#else
1408#define INTR0x60_MONDO_59_MODE 0
1409#endif /* INTR0x60_MONDO_59_MODE */
1410
1411#if INTR0x60_MONDO_59_V
1412#define INTR0x60_MONDO_59_V 1
1413#else
1414#define INTR0x60_MONDO_59_V 0
1415#endif /* INTR0x60_MONDO_59_V */
1416
1417#ifndef INTR0x60_MONDO_59_THREAD
1418#define INTR0x60_MONDO_59_THREAD INTR0x60_MONDO_BAD_THREAD
1419#endif /* INTR0x60_MONDO_59_THREAD */
1420
1421#ifndef INTR0x60_MONDO_59_CNTRL
1422#define INTR0x60_MONDO_59_CNTRL 0
1423#endif /* INTR0x60_MONDO_59_CNTRL */
1424
1425#ifndef INTR0x60_MONDO_59_DMAEPT_ENGINE
1426#define INTR0x60_MONDO_59_DMAEPT_ENGINE 4
1427#endif /* INTR0x60_MONDO_59_DMAEPT_ENGINE */
1428
1429
1430/****************************************/
1431#if INTR0x60_MONDO_62_MODE
1432#define INTR0x60_MONDO_62_MODE 1
1433#else
1434#define INTR0x60_MONDO_62_MODE 0
1435#endif /* INTR0x60_MONDO_62_MODE */
1436
1437#if INTR0x60_MONDO_62_V
1438#define INTR0x60_MONDO_62_V 1
1439#else
1440#define INTR0x60_MONDO_62_V 0
1441#endif /* INTR0x60_MONDO_62_V */
1442
1443#ifndef INTR0x60_MONDO_62_THREAD
1444#define INTR0x60_MONDO_62_THREAD INTR0x60_MONDO_BAD_THREAD
1445#endif /* INTR0x60_MONDO_62_THREAD */
1446
1447#ifndef INTR0x60_MONDO_62_CNTRL
1448#define INTR0x60_MONDO_62_CNTRL 0
1449#endif /* INTR0x60_MONDO_62_CNTRL */
1450
1451
1452
1453/****************************************/
1454#if INTR0x60_MONDO_63_MODE
1455#define INTR0x60_MONDO_63_MODE 1
1456#else
1457#define INTR0x60_MONDO_63_MODE 0
1458#endif /* INTR0x60_MONDO_63_MODE */
1459
1460#if INTR0x60_MONDO_63_V
1461#define INTR0x60_MONDO_63_V 1
1462#else
1463#define INTR0x60_MONDO_63_V 0
1464#endif /* INTR0x60_MONDO_63_V */
1465
1466#ifndef INTR0x60_MONDO_63_THREAD
1467#define INTR0x60_MONDO_63_THREAD INTR0x60_MONDO_BAD_THREAD
1468#endif /* INTR0x60_MONDO_63_THREAD */
1469
1470#ifndef INTR0x60_MONDO_63_CNTRL
1471#define INTR0x60_MONDO_63_CNTRL 0
1472#endif /* INTR0x60_MONDO_63_CNTRL */
1473
1474
1475
1476#ifndef INTR0x60_INTX_DEASSERT_TIMEOUT
1477#define INTR0x60_INTX_DEASSERT_TIMEOUT 1000
1478#endif /* INTR0x60_INTX_DEASSERT_TIMEOUT */
1479
1480
1481/****************************************/
1482#define INTR0x60_IG_UNUSED 0
1483#define INTR0x60_IG_CC 1
1484#define INTR0x60_IG_SSI_ERR 2
1485#define INTR0x60_IG_SSI_INT 3
1486#define INTR0x60_IG_NIU_RX 4
1487#define INTR0x60_IG_NIU_TX 5
1488#define INTR0x60_IG_PIU 6
1489
1490#endif /* INTERRUPT0x60_DEFINES_H */
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