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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt0x60_defines.h.pal | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | start_perl | |
39 | # $Id: interrupt0x60_defines.h.pal,v 1.10 2006/07/19 15:33:23 kensan Exp $ | |
40 | print "/* \$Id\$ */\n"; | |
41 | ||
42 | # Hardware constraints: | |
43 | $hw_num_ivs = 64; $hw_max_ivn = $hw_num_ivs - 1; | |
44 | $hw_num_threads = 64; $hw_max_thread_num = $hw_num_threads - 1; | |
45 | ||
46 | # interrupt0x60 constraints: | |
47 | $max_cc_ivns = 48; $max_cc_ivns_m1 = $max_cc_ivns - 1; | |
48 | $max_niu_ivns = 16; $max_niu_ivns_m1 = $max_niu_ivns - 1; | |
49 | $max_msi_idx = 8; $max_msi_idx_m1 = $max_msi_idx - 1; | |
50 | ||
51 | start_text(>) | |
52 | /* Defines for interrupt-related registers (TT=0x60) */ | |
53 | ||
54 | /*>>>>>> ONLY EDIT THE .pal VERSION OF THIS FILE <<<<<<<<*/ | |
55 | ||
56 | #ifndef INTERRUPT0x60_DEFINES_H | |
57 | #define INTERRUPT0x60_DEFINES_H 1 | |
58 | ||
59 | #define H_HT0_Interrupt_0x60 | |
60 | /* Note: Must preserve %o7, so save it temporarily in %g7 */ | |
61 | #define My_HT0_Interrupt_0x60 \ | |
62 | mov %o7, %g7; \ | |
63 | call intr0x60_handler; \ | |
64 | nop | |
65 | ||
66 | ||
67 | /* | |
68 | * This is tightly linked with interrupt0x60_init.s | |
69 | * | |
70 | * Here are the supported CPP macros. In all cases, | |
71 | * <I> stands for an index, allowing multiple uniquely-named macros. | |
72 | * <IVN> stands for an interrupt vector number, 0-${hw_max_ivn}. | |
73 | * <M> stands for PIU mondo number (20-59, 62, 63). | |
74 | * <T> stands for a thread number (0-${hw_max_thread_num}). | |
75 | * | |
76 | * INTR0x60_BAD_IV=<IVN> | |
77 | * If defined, interrupt vector <IVN> is used in INT_MAN | |
78 | * and MONDO_INT_VEC for any interrupts that are not allowed. | |
79 | * If not defined, interrupt vector 9 will be used. | |
80 | * | |
81 | * INTR0x60_BAD_THREAD=<T> | |
82 | * If defined, thread <T> is used in INT_MAN | |
83 | * for any interrupts that are not allowed. | |
84 | * If not defined, thread 0 will be used. | |
85 | * | |
86 | * | |
87 | * | |
88 | * INTR0x60_CC_IV_<I>=<IVN> (<I> = 0-${max_cc_ivns_m1}) | |
89 | * If defined, interrupt vector <IVN> is permitted to be used | |
90 | * for cross-call interrupts. (Max of ${max_cc_ivns} interrupt vectors can | |
91 | * be used for this purpose; could be increased if needed.) | |
92 | * | |
93 | * INTR0x60_CC_DEST_ALL | |
94 | * If defined, allow cross-call interrupts to all threads. | |
95 | * If not defined, check the target thread against | |
96 | * INTR0x60_CC_DEST_<T> | |
97 | * | |
98 | * INTR0x60_CC_DEST_<T> | |
99 | * Ignored if INTR0x60_CC_DEST_ALL is defined. | |
100 | * If defined to a non-zero value, | |
101 | * allow cross-call interrupts to thread <T> | |
102 | * If not defined, or defined as zero, | |
103 | * do not allow cross-call interrupts to thread <T> | |
104 | * | |
105 | * INTR0x60_CC_EXTRA_HANDLER | |
106 | * If defined (as assembler code), the code will be executed | |
107 | * at the end of the trap handler in hyperprivileged mode. | |
108 | * The code can assume %g1 is the current thread, | |
109 | * and %g2 is the received interrupt vector number. | |
110 | * | |
111 | * | |
112 | * | |
113 | * INTR0x60_MONDO_IV=<IVN> | |
114 | * If defined, interrupt vector <IVN> is used for mondo interrupts | |
115 | * (INTx, MSI, PCIe power management). If not defined, mondo | |
116 | * interrupts will be assigned to INTR0x60_BAD_IV. | |
117 | * | |
118 | * INTR0x60_MONDO_<M>_V=1 | |
119 | * If defined to a non-zero value, mondo <M> will be dispatched to | |
120 | * a thread. Otherwise, mondo <M> will not be dispatched. Used to | |
121 | * set up the PIU Interrupt Mapping Registers. | |
122 | * | |
123 | * INTR0x60_MONDO_<M>_MODE=1 | |
124 | * If defined to a non-zero value, mondo <M> will bear data (MDO_MODE). | |
125 | * Otherwise, mondo <M> will not bear data. Used to set up | |
126 | * the PIU Interrupt Mapping Registers. | |
127 | * | |
128 | * INTR0x60_MONDO_BAD_THREAD=<T> | |
129 | * If defined, any unused mondo will be assigned to thread <T>. | |
130 | * Otherwise, any unused mondo will be assigned to INTR0x60_BAD_THREAD. | |
131 | * Used to set up the PIU Interrupt Mapping Registers when | |
132 | * INTR0x60_MONDO_<M>_THREAD is not defined. | |
133 | * | |
134 | * INTR0x60_MONDO_<M>_THREAD=<T> | |
135 | * If defined, mondo <M> will be assigned to thread <T>. | |
136 | * Otherwise, mondo <M> will be assigned to INTR0x60_MONDO_BAD_THREAD. | |
137 | * Used to set up the PIU Interrupt Mapping Registers. | |
138 | * | |
139 | * INTR0x60_MONDO_<M>_CNTRL=<N> (<N> = 0-3) | |
140 | * If defined, mondo <M> will be assigned to interrupt controller <N>. | |
141 | * Otherwise, mondo <M> will be assigned to interrupt controller 0. | |
142 | * Used to set up the PIU Interrupt Mapping Registers. | |
143 | * | |
144 | * INTR0x60_MONDO_<M>_DMAEPT_ENGINE=<N> (<N> = 1-4) | |
145 | * Unused for Denali endpoint; used for DMAEPT/PEP (FC_NO_PEU_VERA). | |
146 | * If defined, mondo <M> will be generated by DMA engine <N>. | |
147 | * Default is 1+modulo(<M>,4). | |
148 | * Used when clearing INTX. | |
149 | * | |
150 | * INTR0x60_MSI_<I>_NUM=<MSI> (<I> = 0-${max_msi_idx_m1}, <MSI> = 0-255) | |
151 | * INTR0x60_MSI_<I>_EQN=<EQN> (<I> = 0-${max_msi_idx_m1}, <EQN> = 0-35) | |
152 | * If defined, MSI <MSI> will be written to event queue <EQN>. | |
153 | * Otherwise, MSI <MSI> will be treated as an error. | |
154 | * Note that INTR0x60_MONDO_<M>_* must be defined, where | |
155 | * <M> is equal to <EQN> plus 24. | |
156 | * Used to set up the PIU MSI Mapping Registers. | |
157 | * | |
158 | * INTR0x60_PM_PME_EQN=<EQN> (<EQN> = 0-35) | |
159 | * If defined, PM_PME messages will be written to event queue <EQN>. | |
160 | * Otherwise, PM_PME messages will be treated as an error. | |
161 | * Note that INTR0x60_MONDO_<M>_* must be defined, where | |
162 | * <M> is equal to <EQN> plus 24. | |
163 | * Used to set up the PIU PM_PME Mapping Registers. | |
164 | * | |
165 | * INTR0x60_PME_TO_ACK_EQN=<EQN> (<EQN> = 0-35) | |
166 | * If defined, PME_TO_ACK messages will be written to event queue <EQN>. | |
167 | * Otherwise, PME_TO_ACK messages will be treated as an error. | |
168 | * Note that INTR0x60_MONDO_<M>_* must be defined, where | |
169 | * <M> is equal to <EQN> plus 24. | |
170 | * Used to set up the PIU PME_TO_ACK Mapping Registers. | |
171 | * | |
172 | * INTR0x60_EVENT_QUEUE_BASE | |
173 | * Label of data area for the event queue. | |
174 | * Must be 512KB aligned (19 lowest bits must be 0). | |
175 | * Must be defined if using MSI, PM_PME or PME_TO_ACK. | |
176 | * | |
177 | * INTR0x60_MSI_START_ADDRESS | |
178 | * Starting PCI-E address for MSI messages. | |
179 | * Must be 64KB aligned (16 lowest bits must be 0). | |
180 | * Must be defined if using MSI. | |
181 | * | |
182 | * INTR0x60_INTX_DEASSERT_TIMEOUT | |
183 | * Maximum number of iterations while waiting for | |
184 | * the interrupt status bit in PCI_E_INTX_STATUS_ADDR | |
185 | * to be cleared after requesting the PCI-E endpoint | |
186 | * to send the deassert message. | |
187 | * | |
188 | * INTR0x60_INT<x>_EXTRA_HANDLER (<x> = A, B, C or D) | |
189 | * If defined (as assembler code), the code will be executed | |
190 | * at the end of the trap handler in hyperprivileged mode. | |
191 | * The code can assume %g1 is the current thread, and | |
192 | * %g2 is the received interrupt vector number. | |
193 | * | |
194 | * INTR0x60_MSI_<I>_EXTRA_HANDLER_WHILE_BUSY | |
195 | * If defined (as assembler code), the code will be executed | |
196 | * in the trap handler in hyperprivileged mode while the | |
197 | * mondo busy flag (MONDO_INT_ABUSY) is still asserted. | |
198 | * The code can assume %g1 is the current thread, | |
199 | * %g2 is the received interrupt vector number, and | |
200 | * %g3 is the mondo number. | |
201 | * | |
202 | * INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED | |
203 | * If defined (as assembler code), the code will be executed | |
204 | * in the trap handler in hyperprivileged mode while the | |
205 | * event queue is disabled. | |
206 | * The code can assume %g1 is the current thread, | |
207 | * %g2 is the received interrupt vector number, and | |
208 | * %g3 is the mondo number. | |
209 | * | |
210 | * INTR0x60_MSI_EXTRA_HANDLER | |
211 | * If defined (as assembler code), the code will be executed | |
212 | * at the end of the trap handler in hyperprivileged mode. | |
213 | * The code can assume %g1 is the current thread, | |
214 | * %g2 is the received interrupt vector number, and | |
215 | * %g3 is the mondo number. | |
216 | * | |
217 | * INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED | |
218 | * If defined (as assembler code), the code will be executed | |
219 | * in the trap handler in hyperprivileged mode while the | |
220 | * event queue is disabled. | |
221 | * The code can assume %g1 is the current thread, | |
222 | * %g2 is the received interrupt vector number, and | |
223 | * %g3 is the mondo number. | |
224 | * | |
225 | * INTR0x60_PM_PME_EXTRA_HANDLER | |
226 | * If defined (as assembler code), the code will be executed | |
227 | * at the end of the trap handler in hyperprivileged mode. | |
228 | * The code can assume %g1 is the current thread, | |
229 | * %g2 is the received interrupt vector number, and | |
230 | * %g3 is the mondo number. | |
231 | * | |
232 | * INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED | |
233 | * If defined (as assembler code), the code will be executed | |
234 | * in the trap handler in hyperprivileged mode while the | |
235 | * event queue is disabled. | |
236 | * The code can assume %g1 is the current thread, | |
237 | * %g2 is the received interrupt vector number, and | |
238 | * %g3 is the mondo number. | |
239 | * | |
240 | * INTR0x60_PME_TO_ACK_EXTRA_HANDLER | |
241 | * If defined (as assembler code), the code will be executed | |
242 | * at the end of the trap handler in hyperprivileged mode. | |
243 | * The code can assume %g1 is the current thread, | |
244 | * %g2 is the received interrupt vector number, and | |
245 | * %g3 is the mondo number. | |
246 | * | |
247 | * | |
248 | * | |
249 | * INTR0x60_NIU_RX_IV_<I>=<IVN> (<I> = 0-${max_niu_ivns_m1}) | |
250 | * If defined, interrupts coming from NIU Logical Device Group <IVN> | |
251 | * are permitted and will be assigned to interrupt vector <IVN>. | |
252 | * The interrupt must be caused by RX DMA. | |
253 | * (Max of ${max_niu_ivns} interrupt vectors can be used for this purpose; | |
254 | * could be increased if needed.) | |
255 | * NOTE: The interrupt vector number is always the same | |
256 | * as the Logical Device Group. The System Interrupt | |
257 | * Data register in the NIU for the LDG will be | |
258 | * initialized to <IVN>+64 | |
259 | * | |
260 | * INTR0x60_NIU_RX_DMA_<I>=<N> (<I> = 0-${max_niu_ivns_m1}; <N> = 0-15) | |
261 | * Must be defined if INTR0x60_NIU_RX_IV_<I> is defined (same <I>). | |
262 | * Interrupts coming from NIU RX DMA Channel <N> | |
263 | * will be assigned to the NIU Logical Device Group specified | |
264 | * by INTR0x60_NIU_RX_IV_<I> (same <I>). | |
265 | * | |
266 | * INTR0x60_NIU_RX_THREAD_<I>=<T> (<I> = 0-${max_niu_ivns_m1}) | |
267 | * If defined, interrupts coming from NIU Logical Device Group | |
268 | * specified by INTR0x60_NIU_RX_IV_<I> (same <I>) will be sent to | |
269 | * thread <T>. If not defined, those interrupts | |
270 | * will be sent to INTR0x60_NIU_BAD_THREAD. | |
271 | * | |
272 | * INTR0x60_NIU_RX_EXTRA_HANDLER | |
273 | * If defined (as assembler code), the code will be executed | |
274 | * at the end of the trap handler in hyperprivileged mode. | |
275 | * The code can assume %g1 is the current thread, | |
276 | * %g2 is the received interrupt vector number, and | |
277 | * %g3 is the RX DMA channel number. | |
278 | * | |
279 | * INTR0x60_NIU_RX_FATAL_HANDLER | |
280 | * If defined (as assembler code), the code will be executed | |
281 | * (in hyperprivileged mode) as soon as the trap handler | |
282 | * determines that the NIU RX interrupt was caused by a | |
283 | * fatal error. The code must finish with a "retry" instruction. | |
284 | * The code can assume %g1 is the current thread, | |
285 | * %g2 is the received interrupt vector number, | |
286 | * %g3 is the RX DMA channel number, | |
287 | * %g4 is the address of the RX_DMA_CTL_STAT register, and | |
288 | * %g5 is the value of the RX_DMA_CTL_STAT register. | |
289 | * | |
290 | * INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL | |
291 | * If defined, and the trap handler determines that the | |
292 | * NIU RX interrupt was caused by a fatal error, the RX DMA | |
293 | * channel will be reset in a way that is compatible with | |
294 | * the tsotool NIU RX interrupt macro. Afterward, the | |
295 | * INTR0x60_NIU_RX_EXTRA_HANDLER code (if any) will be executed. | |
296 | * INTR0x60_NIU_RX_FATAL_HANDLER preempts this macro. | |
297 | * If the trap handler determines that an NIU RX interrupt was | |
298 | * caused by a fatal error and neither INTR0x60_NIU_RX_FATAL_HANDLER | |
299 | * nor INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL are defined, then the | |
300 | * trap handler will execute EXIT_BAD. | |
301 | * | |
302 | * | |
303 | * | |
304 | * INTR0x60_NIU_TX_IV_<I>=<IVN> (<I> = 0-${max_niu_ivns_m1}) | |
305 | * If defined, interrupts coming from NIU Logical Device Group <IVN> | |
306 | * are permitted and will be assigned to interrupt vector <IVN>. | |
307 | * The interrupt must be caused by TX DMA. | |
308 | * (Max of ${max_niu_ivns} interrupt vectors can be used for this purpose; | |
309 | * could be increased if needed.) | |
310 | * NOTE: The interrupt vector number is always the same | |
311 | * as the Logical Device Group. The System Interrupt | |
312 | * Data register in the NIU for the LDG will be | |
313 | * initialized to <IVN>+64 | |
314 | * | |
315 | * INTR0x60_NIU_TX_DMA_<I>=<N> (<I> = 0-${max_niu_ivns_m1}; <N> = 0-15) | |
316 | * Must be defined if INTR0x60_NIU_TX_IV_<I> is defined (same <I>). | |
317 | * Interrupts coming from NIU TX DMA Channel <N> | |
318 | * will be assigned to the NIU Logical Device Group specified | |
319 | * by INTR0x60_NIU_TX_IV_<I> (same <I>). | |
320 | * | |
321 | * INTR0x60_NIU_TX_THREAD_<I>=<T> (<I> = 0-${max_niu_ivns_m1}) | |
322 | * If defined, interrupts coming from NIU Logical Device Group | |
323 | * specified by INTR0x60_NIU_TX_IV_<I> (same <I>) will be sent to | |
324 | * thread <T>. If not defined, those interrupts | |
325 | * will be sent to INTR0x60_NIU_BAD_THREAD. | |
326 | * | |
327 | * INTR0x60_NIU_TX_EXTRA_HANDLER | |
328 | * If defined (as assembler code), the code will be executed | |
329 | * at the end of the trap handler in hyperprivileged mode. | |
330 | * The code can assume %g1 is the current thread, | |
331 | * %g2 is the received interrupt vector number, and | |
332 | * %g3 is the TX DMA channel number. | |
333 | * | |
334 | * | |
335 | * | |
336 | * INTR0x60_SSI_ERR_IV=<IVN> | |
337 | * If defined, interrupt vector <IVN> is used for SSI error | |
338 | * interrupts. If not defined, SSI error interrupts will | |
339 | * be assigned to INTR0x60_BAD_IV. | |
340 | * | |
341 | * INTR0x60_SSI_ERR_THREAD=<T> | |
342 | * If defined, thread <T> is used for SSI error | |
343 | * interrupts. If not defined, SSI error interrupts will | |
344 | * be assigned to INTR0x60_BAD_THREAD. | |
345 | * | |
346 | * INTR0x60_SSI_ERR_EXTRA_HANDLER | |
347 | * If defined (as assembler code), the code will be executed | |
348 | * at the end of the trap handler in hyperprivileged mode. | |
349 | * The code can assume %g1 is the current thread, and | |
350 | * %g2 is the received interrupt vector number | |
351 | * | |
352 | * | |
353 | * | |
354 | * INTR0x60_SSI_INT_IV=<IVN> | |
355 | * If defined, interrupt vector <IVN> is used for SSI_EXT_INT_L | |
356 | * interrupts. If not defined, SSI_EXT_INT_L interrupts will | |
357 | * be assigned to INTR0x60_BAD_IV. | |
358 | * | |
359 | * INTR0x60_SSI_INT_THREAD=<T> | |
360 | * If defined, thread <T> is used for SSI_EXT_INT_L | |
361 | * interrupts. If not defined, SSI_EXT_INT_L interrupts will | |
362 | * be assigned to INTR0x60_BAD_THREAD. | |
363 | * | |
364 | * INTR0x60_SSI_INT_EXTRA_HANDLER | |
365 | * If defined (as assembler code), the code will be executed | |
366 | * at the end of the trap handler in hyperprivileged mode. | |
367 | * The code can assume %g1 is the current thread, and | |
368 | * %g2 is the received interrupt vector number | |
369 | * | |
370 | */ | |
371 | ||
372 | #ifndef INTR0x60_BAD_IV | |
373 | #define INTR0x60_BAD_IV 9 | |
374 | #endif /* INTR0x60_BAD_IV */ | |
375 | ||
376 | #ifndef INTR0x60_BAD_THREAD | |
377 | #define INTR0x60_BAD_THREAD 0 | |
378 | #endif /* INTR0x60_BAD_THREAD */ | |
379 | ||
380 | #ifndef INTR0x60_MONDO_BAD_THREAD | |
381 | #define INTR0x60_MONDO_BAD_THREAD INTR0x60_BAD_THREAD | |
382 | #endif /* INTR0x60_MONDO_BAD_THREAD */ | |
383 | ||
384 | #ifndef INTR0x60_NIU_BAD_THREAD | |
385 | #define INTR0x60_NIU_BAD_THREAD INTR0x60_BAD_THREAD | |
386 | #endif /* INTR0x60_NIU_BAD_THREAD */ | |
387 | ||
388 | ||
389 | /****************************************/ | |
390 | #ifndef INTR0x60_SSI_ERR_IV | |
391 | #define INTR0x60_SSI_ERR_IV INTR0x60_BAD_IV | |
392 | #endif /* INTR0x60_SSI_ERR_IV */ | |
393 | ||
394 | #ifndef INTR0x60_SSI_ERR_THREAD | |
395 | #define INTR0x60_SSI_ERR_THREAD INTR0x60_BAD_THREAD | |
396 | #endif /* INTR0x60_SSI_ERR_THREAD */ | |
397 | ||
398 | #ifndef INTR0x60_SSI_INT_IV | |
399 | #define INTR0x60_SSI_INT_IV INTR0x60_BAD_IV | |
400 | #endif /* INTR0x60_SSI_INT_IV */ | |
401 | ||
402 | #ifndef INTR0x60_SSI_INT_THREAD | |
403 | #define INTR0x60_SSI_INT_THREAD INTR0x60_BAD_THREAD | |
404 | #endif /* INTR0x60_SSI_INT_THREAD */ | |
405 | ||
406 | >for $mondo_num (20 .. 59, 62, 63) { | |
407 | ||
408 | ||
409 | /****************************************/ | |
410 | #if INTR0x60_MONDO_${mondo_num}_MODE | |
411 | #define INTR0x60_MONDO_${mondo_num}_MODE 1 | |
412 | #else | |
413 | #define INTR0x60_MONDO_${mondo_num}_MODE 0 | |
414 | #endif /* INTR0x60_MONDO_${mondo_num}_MODE */ | |
415 | ||
416 | #if INTR0x60_MONDO_${mondo_num}_V | |
417 | #define INTR0x60_MONDO_${mondo_num}_V 1 | |
418 | #else | |
419 | #define INTR0x60_MONDO_${mondo_num}_V 0 | |
420 | #endif /* INTR0x60_MONDO_${mondo_num}_V */ | |
421 | ||
422 | #ifndef INTR0x60_MONDO_${mondo_num}_THREAD | |
423 | #define INTR0x60_MONDO_${mondo_num}_THREAD INTR0x60_MONDO_BAD_THREAD | |
424 | #endif /* INTR0x60_MONDO_${mondo_num}_THREAD */ | |
425 | ||
426 | #ifndef INTR0x60_MONDO_${mondo_num}_CNTRL | |
427 | #define INTR0x60_MONDO_${mondo_num}_CNTRL 0 | |
428 | #endif /* INTR0x60_MONDO_${mondo_num}_CNTRL */ | |
429 | ||
430 | >if ($mondo_num < 60) { | |
431 | >$engine = 1+ $mondo_num % 4; | |
432 | #ifndef INTR0x60_MONDO_${mondo_num}_DMAEPT_ENGINE | |
433 | #define INTR0x60_MONDO_${mondo_num}_DMAEPT_ENGINE ${engine} | |
434 | #endif /* INTR0x60_MONDO_${mondo_num}_DMAEPT_ENGINE */ | |
435 | >} | |
436 | >} | |
437 | ||
438 | ||
439 | #ifndef INTR0x60_INTX_DEASSERT_TIMEOUT | |
440 | #define INTR0x60_INTX_DEASSERT_TIMEOUT 1000 | |
441 | #endif /* INTR0x60_INTX_DEASSERT_TIMEOUT */ | |
442 | ||
443 | ||
444 | /****************************************/ | |
445 | #define INTR0x60_IG_UNUSED 0 | |
446 | #define INTR0x60_IG_CC 1 | |
447 | #define INTR0x60_IG_SSI_ERR 2 | |
448 | #define INTR0x60_IG_SSI_INT 3 | |
449 | #define INTR0x60_IG_NIU_RX 4 | |
450 | #define INTR0x60_IG_NIU_TX 5 | |
451 | #define INTR0x60_IG_PIU 6 | |
452 | ||
453 | #endif /* INTERRUPT0x60_DEFINES_H */ |