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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / interrupt0x60_sys_init.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt0x60_sys_init.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#include "ncu_defines.h"
39
40#if defined(INTR0x60_NIU_RX_IV_0) || defined(INTR0x60_NIU_TX_IV_0)
41#include "niu_defines.h"
42#include "niu_macros.h"
43#endif /*defined(INTR0x60_NIU_RX_IV_0) || defined(INTR0x60_NIU_TX_IV_0)*/
44
45
46intr0x60_sys_init:
47
48#ifdef PORTABLE_CORE
49 ldxa [%g0] ASI_INTR_ID, %l7
50 and %l7, 0x38, %l7 ! %l7 = core ID, not thread ID
51#endif
52
53#if defined(INTR0x60_INITIALIZE_INT_MAN) || (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV) || (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
54 ! Initialize the Interrupt Management Registers
55intr0x60_sys_init_int_man:
56 best_set_reg(INT_MAN, %l1, %l2) ! %l2 = INT_MAN reg. addr.
57
58intr0x60_sys_init_int_man_0:
59 best_set_reg(mpeval((INTR0x60_BAD_THREAD<<8)+INTR0x60_BAD_IV), %l0, %l1)
60#ifdef PORTABLE_CORE
61 setx 0x3800, %l0, %l6
62 andn %l1, %l6, %l1
63 sllx %l7, 8, %l6
64 or %l1, %l6, %l1 ! Use core ID of core running on
65#endif
66 stx %l1, [%l2]
67
68intr0x60_sys_init_int_man_ssi_err:
69 add %l2, INT_MAN_STEP, %l2
70 best_set_reg(mpeval((INTR0x60_SSI_ERR_THREAD<<8)+INTR0x60_SSI_ERR_IV),
71 %l0, %l1)
72#ifdef PORTABLE_CORE
73 setx 0x3800, %l0, %l6
74 andn %l1, %l6, %l1
75 sllx %l7, 8, %l6
76 or %l1, %l6, %l1 ! Use core ID of core running on
77#endif
78 stx %l1, [%l2]
79intr0x60_sys_init_enable_ssi_error_interrupts:
80#include "ssi_defines.h"
81 best_set_reg(SSI_TIMEOUT_ADDR, %l0, %l3)
82 best_set_reg(SSI_TIMEOUT_ERREN_MASK, %l0, %l1)
83 ldx [%l3],%l0
84 or %l0, %l1, %l1
85 stx %l1, [%l3]
86
87intr0x60_sys_init_int_man_ssi_int:
88 add %l2, INT_MAN_STEP, %l2
89 best_set_reg(mpeval((INTR0x60_SSI_INT_THREAD<<8)+INTR0x60_SSI_INT_IV),
90 %l0, %l1)
91#ifdef PORTABLE_CORE
92 setx 0x3800, %l0, %l6
93 andn %l1, %l6, %l1
94 sllx %l7, 8, %l6
95 or %l1, %l6, %l1 ! Use core ID of core running on
96#endif
97 stx %l1, [%l2]
98#endif /* INTR0x60_INITIALIZE_INT_MAN or SSI_ERR or SSI_INT */
99
100
101
102#ifdef INTR0x60_NIU_RX_IV_0
103intr0x60_sys_init_int_man_niu_rx_0:
104 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_0)*INT_MAN_STEP), %l1, %l2)
105 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_0<<8)+INTR0x60_NIU_RX_IV_0),
106 %l0, %l1)
107 stx %l1, [%l2]
108#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
109 ! Initialize the NIU for RX DMA interrupt.
110 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_0,
111 %l1, %l2, %l3, %l4,
112 INTR0x60_NIU_RX_IV_0,
113 eval(64 + INTR0x60_NIU_RX_IV_0), %l5 )
114#endif
115#endif /* INTR0x60_NIU_RX_IV_0 */
116
117#ifdef INTR0x60_NIU_RX_IV_1
118intr0x60_sys_init_int_man_niu_rx_1:
119 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_1)*INT_MAN_STEP), %l1, %l2)
120 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_1<<8)+INTR0x60_NIU_RX_IV_1),
121 %l0, %l1)
122 stx %l1, [%l2]
123#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
124 ! Initialize the NIU for RX DMA interrupt.
125 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_1,
126 %l1, %l2, %l3, %l4,
127 INTR0x60_NIU_RX_IV_1,
128 eval(64 + INTR0x60_NIU_RX_IV_1), %l5 )
129#endif
130#endif /* INTR0x60_NIU_RX_IV_1 */
131
132#ifdef INTR0x60_NIU_RX_IV_2
133intr0x60_sys_init_int_man_niu_rx_2:
134 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_2)*INT_MAN_STEP), %l1, %l2)
135 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_2<<8)+INTR0x60_NIU_RX_IV_2),
136 %l0, %l1)
137 stx %l1, [%l2]
138#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
139 ! Initialize the NIU for RX DMA interrupt.
140 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_2,
141 %l1, %l2, %l3, %l4,
142 INTR0x60_NIU_RX_IV_2,
143 eval(64 + INTR0x60_NIU_RX_IV_2), %l5 )
144#endif
145#endif /* INTR0x60_NIU_RX_IV_2 */
146
147#ifdef INTR0x60_NIU_RX_IV_3
148intr0x60_sys_init_int_man_niu_rx_3:
149 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_3)*INT_MAN_STEP), %l1, %l2)
150 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_3<<8)+INTR0x60_NIU_RX_IV_3),
151 %l0, %l1)
152 stx %l1, [%l2]
153#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
154 ! Initialize the NIU for RX DMA interrupt.
155 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_3,
156 %l1, %l2, %l3, %l4,
157 INTR0x60_NIU_RX_IV_3,
158 eval(64 + INTR0x60_NIU_RX_IV_3), %l5 )
159#endif
160#endif /* INTR0x60_NIU_RX_IV_3 */
161
162#ifdef INTR0x60_NIU_RX_IV_4
163intr0x60_sys_init_int_man_niu_rx_4:
164 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_4)*INT_MAN_STEP), %l1, %l2)
165 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_4<<8)+INTR0x60_NIU_RX_IV_4),
166 %l0, %l1)
167 stx %l1, [%l2]
168#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
169 ! Initialize the NIU for RX DMA interrupt.
170 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_4,
171 %l1, %l2, %l3, %l4,
172 INTR0x60_NIU_RX_IV_4,
173 eval(64 + INTR0x60_NIU_RX_IV_4), %l5 )
174#endif
175#endif /* INTR0x60_NIU_RX_IV_4 */
176
177#ifdef INTR0x60_NIU_RX_IV_5
178intr0x60_sys_init_int_man_niu_rx_5:
179 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_5)*INT_MAN_STEP), %l1, %l2)
180 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_5<<8)+INTR0x60_NIU_RX_IV_5),
181 %l0, %l1)
182 stx %l1, [%l2]
183#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
184 ! Initialize the NIU for RX DMA interrupt.
185 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_5,
186 %l1, %l2, %l3, %l4,
187 INTR0x60_NIU_RX_IV_5,
188 eval(64 + INTR0x60_NIU_RX_IV_5), %l5 )
189#endif
190#endif /* INTR0x60_NIU_RX_IV_5 */
191
192#ifdef INTR0x60_NIU_RX_IV_6
193intr0x60_sys_init_int_man_niu_rx_6:
194 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_6)*INT_MAN_STEP), %l1, %l2)
195 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_6<<8)+INTR0x60_NIU_RX_IV_6),
196 %l0, %l1)
197 stx %l1, [%l2]
198#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
199 ! Initialize the NIU for RX DMA interrupt.
200 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_6,
201 %l1, %l2, %l3, %l4,
202 INTR0x60_NIU_RX_IV_6,
203 eval(64 + INTR0x60_NIU_RX_IV_6), %l5 )
204#endif
205#endif /* INTR0x60_NIU_RX_IV_6 */
206
207#ifdef INTR0x60_NIU_RX_IV_7
208intr0x60_sys_init_int_man_niu_rx_7:
209 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_7)*INT_MAN_STEP), %l1, %l2)
210 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_7<<8)+INTR0x60_NIU_RX_IV_7),
211 %l0, %l1)
212 stx %l1, [%l2]
213#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
214 ! Initialize the NIU for RX DMA interrupt.
215 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_7,
216 %l1, %l2, %l3, %l4,
217 INTR0x60_NIU_RX_IV_7,
218 eval(64 + INTR0x60_NIU_RX_IV_7), %l5 )
219#endif
220#endif /* INTR0x60_NIU_RX_IV_7 */
221
222#ifdef INTR0x60_NIU_RX_IV_8
223intr0x60_sys_init_int_man_niu_rx_8:
224 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_8)*INT_MAN_STEP), %l1, %l2)
225 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_8<<8)+INTR0x60_NIU_RX_IV_8),
226 %l0, %l1)
227 stx %l1, [%l2]
228#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
229 ! Initialize the NIU for RX DMA interrupt.
230 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_8,
231 %l1, %l2, %l3, %l4,
232 INTR0x60_NIU_RX_IV_8,
233 eval(64 + INTR0x60_NIU_RX_IV_8), %l5 )
234#endif
235#endif /* INTR0x60_NIU_RX_IV_8 */
236
237#ifdef INTR0x60_NIU_RX_IV_9
238intr0x60_sys_init_int_man_niu_rx_9:
239 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_9)*INT_MAN_STEP), %l1, %l2)
240 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_9<<8)+INTR0x60_NIU_RX_IV_9),
241 %l0, %l1)
242 stx %l1, [%l2]
243#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
244 ! Initialize the NIU for RX DMA interrupt.
245 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_9,
246 %l1, %l2, %l3, %l4,
247 INTR0x60_NIU_RX_IV_9,
248 eval(64 + INTR0x60_NIU_RX_IV_9), %l5 )
249#endif
250#endif /* INTR0x60_NIU_RX_IV_9 */
251
252#ifdef INTR0x60_NIU_RX_IV_10
253intr0x60_sys_init_int_man_niu_rx_10:
254 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_10)*INT_MAN_STEP), %l1, %l2)
255 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_10<<8)+INTR0x60_NIU_RX_IV_10),
256 %l0, %l1)
257 stx %l1, [%l2]
258#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
259 ! Initialize the NIU for RX DMA interrupt.
260 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_10,
261 %l1, %l2, %l3, %l4,
262 INTR0x60_NIU_RX_IV_10,
263 eval(64 + INTR0x60_NIU_RX_IV_10), %l5 )
264#endif
265#endif /* INTR0x60_NIU_RX_IV_10 */
266
267#ifdef INTR0x60_NIU_RX_IV_11
268intr0x60_sys_init_int_man_niu_rx_11:
269 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_11)*INT_MAN_STEP), %l1, %l2)
270 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_11<<8)+INTR0x60_NIU_RX_IV_11),
271 %l0, %l1)
272 stx %l1, [%l2]
273#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
274 ! Initialize the NIU for RX DMA interrupt.
275 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_11,
276 %l1, %l2, %l3, %l4,
277 INTR0x60_NIU_RX_IV_11,
278 eval(64 + INTR0x60_NIU_RX_IV_11), %l5 )
279#endif
280#endif /* INTR0x60_NIU_RX_IV_11 */
281
282#ifdef INTR0x60_NIU_RX_IV_12
283intr0x60_sys_init_int_man_niu_rx_12:
284 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_12)*INT_MAN_STEP), %l1, %l2)
285 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_12<<8)+INTR0x60_NIU_RX_IV_12),
286 %l0, %l1)
287 stx %l1, [%l2]
288#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
289 ! Initialize the NIU for RX DMA interrupt.
290 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_12,
291 %l1, %l2, %l3, %l4,
292 INTR0x60_NIU_RX_IV_12,
293 eval(64 + INTR0x60_NIU_RX_IV_12), %l5 )
294#endif
295#endif /* INTR0x60_NIU_RX_IV_12 */
296
297#ifdef INTR0x60_NIU_RX_IV_13
298intr0x60_sys_init_int_man_niu_rx_13:
299 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_13)*INT_MAN_STEP), %l1, %l2)
300 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_13<<8)+INTR0x60_NIU_RX_IV_13),
301 %l0, %l1)
302 stx %l1, [%l2]
303#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
304 ! Initialize the NIU for RX DMA interrupt.
305 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_13,
306 %l1, %l2, %l3, %l4,
307 INTR0x60_NIU_RX_IV_13,
308 eval(64 + INTR0x60_NIU_RX_IV_13), %l5 )
309#endif
310#endif /* INTR0x60_NIU_RX_IV_13 */
311
312#ifdef INTR0x60_NIU_RX_IV_14
313intr0x60_sys_init_int_man_niu_rx_14:
314 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_14)*INT_MAN_STEP), %l1, %l2)
315 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_14<<8)+INTR0x60_NIU_RX_IV_14),
316 %l0, %l1)
317 stx %l1, [%l2]
318#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
319 ! Initialize the NIU for RX DMA interrupt.
320 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_14,
321 %l1, %l2, %l3, %l4,
322 INTR0x60_NIU_RX_IV_14,
323 eval(64 + INTR0x60_NIU_RX_IV_14), %l5 )
324#endif
325#endif /* INTR0x60_NIU_RX_IV_14 */
326
327#ifdef INTR0x60_NIU_RX_IV_15
328intr0x60_sys_init_int_man_niu_rx_15:
329 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_15)*INT_MAN_STEP), %l1, %l2)
330 best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_15<<8)+INTR0x60_NIU_RX_IV_15),
331 %l0, %l1)
332 stx %l1, [%l2]
333#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
334 ! Initialize the NIU for RX DMA interrupt.
335 NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_15,
336 %l1, %l2, %l3, %l4,
337 INTR0x60_NIU_RX_IV_15,
338 eval(64 + INTR0x60_NIU_RX_IV_15), %l5 )
339#endif
340#endif /* INTR0x60_NIU_RX_IV_15 */
341
342
343
344#ifdef INTR0x60_NIU_TX_IV_0
345intr0x60_sys_init_int_man_niu_tx_0:
346 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_0)*INT_MAN_STEP), %l1, %l2)
347 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_0<<8)+INTR0x60_NIU_TX_IV_0),
348 %l0, %l1)
349 stx %l1, [%l2]
350#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
351 ! Initialize the NIU for TX DMA interrupt.
352 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_0,
353 %l1, %l2, %l3, %l4,
354 INTR0x60_NIU_TX_IV_0,
355 eval(64 + INTR0x60_NIU_TX_IV_0) )
356#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
357#endif /* INTR0x60_NIU_TX_IV_0 */
358
359#ifdef INTR0x60_NIU_TX_IV_1
360intr0x60_sys_init_int_man_niu_tx_1:
361 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_1)*INT_MAN_STEP), %l1, %l2)
362 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_1<<8)+INTR0x60_NIU_TX_IV_1),
363 %l0, %l1)
364 stx %l1, [%l2]
365#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
366 ! Initialize the NIU for TX DMA interrupt.
367 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_1,
368 %l1, %l2, %l3, %l4,
369 INTR0x60_NIU_TX_IV_1,
370 eval(64 + INTR0x60_NIU_TX_IV_1) )
371#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
372#endif /* INTR0x60_NIU_TX_IV_1 */
373
374#ifdef INTR0x60_NIU_TX_IV_2
375intr0x60_sys_init_int_man_niu_tx_2:
376 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_2)*INT_MAN_STEP), %l1, %l2)
377 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_2<<8)+INTR0x60_NIU_TX_IV_2),
378 %l0, %l1)
379 stx %l1, [%l2]
380#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
381 ! Initialize the NIU for TX DMA interrupt.
382 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_2,
383 %l1, %l2, %l3, %l4,
384 INTR0x60_NIU_TX_IV_2,
385 eval(64 + INTR0x60_NIU_TX_IV_2) )
386#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
387#endif /* INTR0x60_NIU_TX_IV_2 */
388
389#ifdef INTR0x60_NIU_TX_IV_3
390intr0x60_sys_init_int_man_niu_tx_3:
391 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_3)*INT_MAN_STEP), %l1, %l2)
392 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_3<<8)+INTR0x60_NIU_TX_IV_3),
393 %l0, %l1)
394 stx %l1, [%l2]
395#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
396 ! Initialize the NIU for TX DMA interrupt.
397 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_3,
398 %l1, %l2, %l3, %l4,
399 INTR0x60_NIU_TX_IV_3,
400 eval(64 + INTR0x60_NIU_TX_IV_3) )
401#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
402#endif /* INTR0x60_NIU_TX_IV_3 */
403
404#ifdef INTR0x60_NIU_TX_IV_4
405intr0x60_sys_init_int_man_niu_tx_4:
406 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_4)*INT_MAN_STEP), %l1, %l2)
407 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_4<<8)+INTR0x60_NIU_TX_IV_4),
408 %l0, %l1)
409 stx %l1, [%l2]
410#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
411 ! Initialize the NIU for TX DMA interrupt.
412 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_4,
413 %l1, %l2, %l3, %l4,
414 INTR0x60_NIU_TX_IV_4,
415 eval(64 + INTR0x60_NIU_TX_IV_4) )
416#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
417#endif /* INTR0x60_NIU_TX_IV_4 */
418
419#ifdef INTR0x60_NIU_TX_IV_5
420intr0x60_sys_init_int_man_niu_tx_5:
421 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_5)*INT_MAN_STEP), %l1, %l2)
422 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_5<<8)+INTR0x60_NIU_TX_IV_5),
423 %l0, %l1)
424 stx %l1, [%l2]
425#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
426 ! Initialize the NIU for TX DMA interrupt.
427 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_5,
428 %l1, %l2, %l3, %l4,
429 INTR0x60_NIU_TX_IV_5,
430 eval(64 + INTR0x60_NIU_TX_IV_5) )
431#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
432#endif /* INTR0x60_NIU_TX_IV_5 */
433
434#ifdef INTR0x60_NIU_TX_IV_6
435intr0x60_sys_init_int_man_niu_tx_6:
436 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_6)*INT_MAN_STEP), %l1, %l2)
437 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_6<<8)+INTR0x60_NIU_TX_IV_6),
438 %l0, %l1)
439 stx %l1, [%l2]
440#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
441 ! Initialize the NIU for TX DMA interrupt.
442 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_6,
443 %l1, %l2, %l3, %l4,
444 INTR0x60_NIU_TX_IV_6,
445 eval(64 + INTR0x60_NIU_TX_IV_6) )
446#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
447#endif /* INTR0x60_NIU_TX_IV_6 */
448
449#ifdef INTR0x60_NIU_TX_IV_7
450intr0x60_sys_init_int_man_niu_tx_7:
451 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_7)*INT_MAN_STEP), %l1, %l2)
452 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_7<<8)+INTR0x60_NIU_TX_IV_7),
453 %l0, %l1)
454 stx %l1, [%l2]
455#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
456 ! Initialize the NIU for TX DMA interrupt.
457 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_7,
458 %l1, %l2, %l3, %l4,
459 INTR0x60_NIU_TX_IV_7,
460 eval(64 + INTR0x60_NIU_TX_IV_7) )
461#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
462#endif /* INTR0x60_NIU_TX_IV_7 */
463
464#ifdef INTR0x60_NIU_TX_IV_8
465intr0x60_sys_init_int_man_niu_tx_8:
466 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_8)*INT_MAN_STEP), %l1, %l2)
467 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_8<<8)+INTR0x60_NIU_TX_IV_8),
468 %l0, %l1)
469 stx %l1, [%l2]
470#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
471 ! Initialize the NIU for TX DMA interrupt.
472 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_8,
473 %l1, %l2, %l3, %l4,
474 INTR0x60_NIU_TX_IV_8,
475 eval(64 + INTR0x60_NIU_TX_IV_8) )
476#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
477#endif /* INTR0x60_NIU_TX_IV_8 */
478
479#ifdef INTR0x60_NIU_TX_IV_9
480intr0x60_sys_init_int_man_niu_tx_9:
481 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_9)*INT_MAN_STEP), %l1, %l2)
482 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_9<<8)+INTR0x60_NIU_TX_IV_9),
483 %l0, %l1)
484 stx %l1, [%l2]
485#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
486 ! Initialize the NIU for TX DMA interrupt.
487 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_9,
488 %l1, %l2, %l3, %l4,
489 INTR0x60_NIU_TX_IV_9,
490 eval(64 + INTR0x60_NIU_TX_IV_9) )
491#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
492#endif /* INTR0x60_NIU_TX_IV_9 */
493
494#ifdef INTR0x60_NIU_TX_IV_10
495intr0x60_sys_init_int_man_niu_tx_10:
496 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_10)*INT_MAN_STEP), %l1, %l2)
497 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_10<<8)+INTR0x60_NIU_TX_IV_10),
498 %l0, %l1)
499 stx %l1, [%l2]
500#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
501 ! Initialize the NIU for TX DMA interrupt.
502 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_10,
503 %l1, %l2, %l3, %l4,
504 INTR0x60_NIU_TX_IV_10,
505 eval(64 + INTR0x60_NIU_TX_IV_10) )
506#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
507#endif /* INTR0x60_NIU_TX_IV_10 */
508
509#ifdef INTR0x60_NIU_TX_IV_11
510intr0x60_sys_init_int_man_niu_tx_11:
511 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_11)*INT_MAN_STEP), %l1, %l2)
512 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_11<<8)+INTR0x60_NIU_TX_IV_11),
513 %l0, %l1)
514 stx %l1, [%l2]
515#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
516 ! Initialize the NIU for TX DMA interrupt.
517 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_11,
518 %l1, %l2, %l3, %l4,
519 INTR0x60_NIU_TX_IV_11,
520 eval(64 + INTR0x60_NIU_TX_IV_11) )
521#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
522#endif /* INTR0x60_NIU_TX_IV_11 */
523
524#ifdef INTR0x60_NIU_TX_IV_12
525intr0x60_sys_init_int_man_niu_tx_12:
526 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_12)*INT_MAN_STEP), %l1, %l2)
527 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_12<<8)+INTR0x60_NIU_TX_IV_12),
528 %l0, %l1)
529 stx %l1, [%l2]
530#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
531 ! Initialize the NIU for TX DMA interrupt.
532 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_12,
533 %l1, %l2, %l3, %l4,
534 INTR0x60_NIU_TX_IV_12,
535 eval(64 + INTR0x60_NIU_TX_IV_12) )
536#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
537#endif /* INTR0x60_NIU_TX_IV_12 */
538
539#ifdef INTR0x60_NIU_TX_IV_13
540intr0x60_sys_init_int_man_niu_tx_13:
541 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_13)*INT_MAN_STEP), %l1, %l2)
542 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_13<<8)+INTR0x60_NIU_TX_IV_13),
543 %l0, %l1)
544 stx %l1, [%l2]
545#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
546 ! Initialize the NIU for TX DMA interrupt.
547 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_13,
548 %l1, %l2, %l3, %l4,
549 INTR0x60_NIU_TX_IV_13,
550 eval(64 + INTR0x60_NIU_TX_IV_13) )
551#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
552#endif /* INTR0x60_NIU_TX_IV_13 */
553
554#ifdef INTR0x60_NIU_TX_IV_14
555intr0x60_sys_init_int_man_niu_tx_14:
556 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_14)*INT_MAN_STEP), %l1, %l2)
557 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_14<<8)+INTR0x60_NIU_TX_IV_14),
558 %l0, %l1)
559 stx %l1, [%l2]
560#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
561 ! Initialize the NIU for TX DMA interrupt.
562 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_14,
563 %l1, %l2, %l3, %l4,
564 INTR0x60_NIU_TX_IV_14,
565 eval(64 + INTR0x60_NIU_TX_IV_14) )
566#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
567#endif /* INTR0x60_NIU_TX_IV_14 */
568
569#ifdef INTR0x60_NIU_TX_IV_15
570intr0x60_sys_init_int_man_niu_tx_15:
571 best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_15)*INT_MAN_STEP), %l1, %l2)
572 best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_15<<8)+INTR0x60_NIU_TX_IV_15),
573 %l0, %l1)
574 stx %l1, [%l2]
575#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
576 ! Initialize the NIU for TX DMA interrupt.
577 NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_15,
578 %l1, %l2, %l3, %l4,
579 INTR0x60_NIU_TX_IV_15,
580 eval(64 + INTR0x60_NIU_TX_IV_15) )
581#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
582#endif /* INTR0x60_NIU_TX_IV_15 */
583
584
585
586 ! Initialize Mondo Interrupt Vector Register
587intr0x60_sys_init_mondo_int_vec:
588#ifdef INTR0x60_MONDO_IV
589 best_set_reg(INTR0x60_MONDO_IV, %l2, %l1)
590#else
591 best_set_reg(INTR0x60_BAD_IV, %l2, %l1)
592#endif /* INTR0x60_MONDO_IV */
593 best_set_reg(MONDO_INT_VEC, %l2, %l3)
594 stx %l1, [%l3]
595
596#ifdef INTR0x60_MONDO_IV
597/* Mondos come from PIU, so do the appropriate initialization */
598/* Need some cpp macros for PIU registers */
599#include "peu_defines.h"
600
601
602intr0x60_sys_init_clear_intx:
603 set 1, %l3
604 best_set_reg(PCI_E_INT_A_CLEAR_ADDR, %l1, %l2)
605 stx %l3, [%l2]
606 best_set_reg(PCI_E_INT_B_CLEAR_ADDR, %l1, %l2)
607 stx %l3, [%l2]
608 best_set_reg(PCI_E_INT_C_CLEAR_ADDR, %l1, %l2)
609 stx %l3, [%l2]
610 best_set_reg(PCI_E_INT_D_CLEAR_ADDR, %l1, %l2)
611 stx %l3, [%l2]
612
613
614/* Clear the MSI registers, if any MSIs are being used */
615#ifdef INTR0x60_MSI_0_NUM
616intr0x60_sys_init_clear_msi:
617 set 1, %l3
618 sllx %l3, 62, %l3 ! EQWR_N is bit 62
619 best_set_reg(PCI_E_MSI_CLEAR_ADDR, %l1, %l2)
620#ifdef INTR0x60_MSI_0_NUM
621intr0x60_sys_init_clear_msi_0:
622 best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_0_NUM),
623 %l1, %l4)
624 stx %l3, [%l2+%l4]
625#endif /* INTR0x60_MSI_0_NUM */
626#ifdef INTR0x60_MSI_1_NUM
627intr0x60_sys_init_clear_msi_1:
628 best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_1_NUM),
629 %l1, %l4)
630 stx %l3, [%l2+%l4]
631#endif /* INTR0x60_MSI_1_NUM */
632#ifdef INTR0x60_MSI_2_NUM
633intr0x60_sys_init_clear_msi_2:
634 best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_2_NUM),
635 %l1, %l4)
636 stx %l3, [%l2+%l4]
637#endif /* INTR0x60_MSI_2_NUM */
638#ifdef INTR0x60_MSI_3_NUM
639intr0x60_sys_init_clear_msi_3:
640 best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_3_NUM),
641 %l1, %l4)
642 stx %l3, [%l2+%l4]
643#endif /* INTR0x60_MSI_3_NUM */
644#ifdef INTR0x60_MSI_4_NUM
645intr0x60_sys_init_clear_msi_4:
646 best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_4_NUM),
647 %l1, %l4)
648 stx %l3, [%l2+%l4]
649#endif /* INTR0x60_MSI_4_NUM */
650#ifdef INTR0x60_MSI_5_NUM
651intr0x60_sys_init_clear_msi_5:
652 best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_5_NUM),
653 %l1, %l4)
654 stx %l3, [%l2+%l4]
655#endif /* INTR0x60_MSI_5_NUM */
656#ifdef INTR0x60_MSI_6_NUM
657intr0x60_sys_init_clear_msi_6:
658 best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_6_NUM),
659 %l1, %l4)
660 stx %l3, [%l2+%l4]
661#endif /* INTR0x60_MSI_6_NUM */
662#ifdef INTR0x60_MSI_7_NUM
663intr0x60_sys_init_clear_msi_7:
664 best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_7_NUM),
665 %l1, %l4)
666 stx %l3, [%l2+%l4]
667#endif /* INTR0x60_MSI_7_NUM */
668#endif /* INTR0x60_MSI_0_NUM */
669
670
671 ! Also clear in Interrupt Clear reg.
672intr0x60_sys_init_piu_intr_clear:
673 best_set_reg(PCI_E_INT_CLEAR_ADDR, %l1, %l2)
674 mov PCI_E_INT_CLEAR_COUNT, %l3
675intr0x60_sys_init_piu_intr_clear_loop_top:
676 stx %g0, [%l2]
677 dec %l3
678 brnz %l3,intr0x60_sys_init_piu_intr_clear_loop_top
679 add PCI_E_INT_CLEAR_STEP, %l2, %l2
680
681/* WIP: Clear INO 62 and 63 */
682
683
684/* Set up the Event Queues in PIU, if any are being used */
685#ifdef INTR0x60_EVENT_QUEUE_BASE
686intr0x60_sys_init_piu_eq_base_addr:
687 ! First the Event Queue Base Address reg.
688 ! Formatted for a bypass address.
689 best_set_reg(PCI_E_EV_QUE_BASE_ADDRESS_ADDR, %l1, %l2)
690 setx (INTR0x60_EVENT_QUEUE_BASE), %l1, %l3
691 best_set_reg(0xfffc000000000000, %l1, %l6)
692 or %l3, %l6, %l3
693 stx %l3, [%l2]
694
695 ! Event Queue Control Set reg.
696intr0x60_sys_init_piu_eq_ctl_set_en:
697 set 1, %l3
698 sllx %l3, 44, %l3 ! EN is bit 44
699 best_set_reg(PCI_E_EV_QUE_CTL_SET_ADDR, %l1, %l2)
700#ifdef INTR0x60_MSI_0_NUM
701intr0x60_sys_init_piu_eq_ctl_set_en_0:
702 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_0_EQN),
703 %l1, %l4)
704 stx %l3, [%l2+%l4]
705#endif /* INTR0x60_MSI_0_NUM */
706#ifdef INTR0x60_MSI_1_NUM
707intr0x60_sys_init_piu_eq_ctl_set_en_1:
708 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_1_EQN),
709 %l1, %l4)
710 stx %l3, [%l2+%l4]
711#endif /* INTR0x60_MSI_1_NUM */
712#ifdef INTR0x60_MSI_2_NUM
713intr0x60_sys_init_piu_eq_ctl_set_en_2:
714 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_2_EQN),
715 %l1, %l4)
716 stx %l3, [%l2+%l4]
717#endif /* INTR0x60_MSI_2_NUM */
718#ifdef INTR0x60_MSI_3_NUM
719intr0x60_sys_init_piu_eq_ctl_set_en_3:
720 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_3_EQN),
721 %l1, %l4)
722 stx %l3, [%l2+%l4]
723#endif /* INTR0x60_MSI_3_NUM */
724#ifdef INTR0x60_MSI_4_NUM
725intr0x60_sys_init_piu_eq_ctl_set_en_4:
726 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_4_EQN),
727 %l1, %l4)
728 stx %l3, [%l2+%l4]
729#endif /* INTR0x60_MSI_4_NUM */
730#ifdef INTR0x60_MSI_5_NUM
731intr0x60_sys_init_piu_eq_ctl_set_en_5:
732 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_5_EQN),
733 %l1, %l4)
734 stx %l3, [%l2+%l4]
735#endif /* INTR0x60_MSI_5_NUM */
736#ifdef INTR0x60_MSI_6_NUM
737intr0x60_sys_init_piu_eq_ctl_set_en_6:
738 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_6_EQN),
739 %l1, %l4)
740 stx %l3, [%l2+%l4]
741#endif /* INTR0x60_MSI_6_NUM */
742#ifdef INTR0x60_MSI_7_NUM
743intr0x60_sys_init_piu_eq_ctl_set_en_7:
744 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_7_EQN),
745 %l1, %l4)
746 stx %l3, [%l2+%l4]
747#endif /* INTR0x60_MSI_7_NUM */
748#ifdef INTR0x60_PM_PME_EQN
749intr0x60_sys_init_piu_eq_ctl_set_en_pm_pme:
750 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PM_PME_EQN),
751 %l1, %l4)
752 stx %l3, [%l2+%l4]
753#endif /* INTR0x60_PM_PME_EQN */
754#ifdef INTR0x60_PME_TO_ACK_EQN
755intr0x60_sys_init_piu_eq_ctl_set_en_pme_to_ack:
756 best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PME_TO_ACK_EQN),
757 %l1, %l4)
758 stx %l3, [%l2+%l4]
759#endif /* INTR0x60_PME_TO_ACK_EQN */
760
761#endif /* INTR0x60_EVENT_QUEUE_BASE */
762
763
764#ifdef INTR0x60_MSI_START_ADDRESS
765 ! Set up the MSI address
766intr0x60_sys_init_piu_msi_addr:
767 best_set_reg(INTR0x60_MSI_START_ADDRESS, %l1, %l3)
768 best_set_reg(PCI_E_MSI_32_ADDRESS_ADDR, %l1, %l2)
769 stx %l3, [%l2]
770 best_set_reg(PCI_E_MSI_64_ADDRESS_ADDR, %l1, %l2)
771 stx %l3, [%l2]
772
773 ! MSI-to-Event Queue Mapping registers
774intr0x60_sys_init_piu_msi_mapping:
775 set 1, %l3
776 sllx %l3, 63, %l3 ! V is bit 63
777 best_set_reg(PCI_E_MSI_MAP_ADDR, %l1, %l2)
778#ifdef INTR0x60_MSI_0_NUM
779intr0x60_sys_init_piu_msi_mapping_0:
780 best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_0_NUM),
781 %l1, %l4)
782 best_set_reg(INTR0x60_MSI_0_EQN, %l1, %l5)
783 add %l3, %l5, %l5
784 stx %l5, [%l2+%l4]
785#endif /* INTR0x60_MSI_0_NUM */
786#ifdef INTR0x60_MSI_1_NUM
787intr0x60_sys_init_piu_msi_mapping_1:
788 best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_1_NUM),
789 %l1, %l4)
790 best_set_reg(INTR0x60_MSI_1_EQN, %l1, %l5)
791 add %l3, %l5, %l5
792 stx %l5, [%l2+%l4]
793#endif /* INTR0x60_MSI_1_NUM */
794#ifdef INTR0x60_MSI_2_NUM
795intr0x60_sys_init_piu_msi_mapping_2:
796 best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_2_NUM),
797 %l1, %l4)
798 best_set_reg(INTR0x60_MSI_2_EQN, %l1, %l5)
799 add %l3, %l5, %l5
800 stx %l5, [%l2+%l4]
801#endif /* INTR0x60_MSI_2_NUM */
802#ifdef INTR0x60_MSI_3_NUM
803intr0x60_sys_init_piu_msi_mapping_3:
804 best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_3_NUM),
805 %l1, %l4)
806 best_set_reg(INTR0x60_MSI_3_EQN, %l1, %l5)
807 add %l3, %l5, %l5
808 stx %l5, [%l2+%l4]
809#endif /* INTR0x60_MSI_3_NUM */
810#ifdef INTR0x60_MSI_4_NUM
811intr0x60_sys_init_piu_msi_mapping_4:
812 best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_4_NUM),
813 %l1, %l4)
814 best_set_reg(INTR0x60_MSI_4_EQN, %l1, %l5)
815 add %l3, %l5, %l5
816 stx %l5, [%l2+%l4]
817#endif /* INTR0x60_MSI_4_NUM */
818#ifdef INTR0x60_MSI_5_NUM
819intr0x60_sys_init_piu_msi_mapping_5:
820 best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_5_NUM),
821 %l1, %l4)
822 best_set_reg(INTR0x60_MSI_5_EQN, %l1, %l5)
823 add %l3, %l5, %l5
824 stx %l5, [%l2+%l4]
825#endif /* INTR0x60_MSI_5_NUM */
826#ifdef INTR0x60_MSI_6_NUM
827intr0x60_sys_init_piu_msi_mapping_6:
828 best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_6_NUM),
829 %l1, %l4)
830 best_set_reg(INTR0x60_MSI_6_EQN, %l1, %l5)
831 add %l3, %l5, %l5
832 stx %l5, [%l2+%l4]
833#endif /* INTR0x60_MSI_6_NUM */
834#ifdef INTR0x60_MSI_7_NUM
835intr0x60_sys_init_piu_msi_mapping_7:
836 best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_7_NUM),
837 %l1, %l4)
838 best_set_reg(INTR0x60_MSI_7_EQN, %l1, %l5)
839 add %l3, %l5, %l5
840 stx %l5, [%l2+%l4]
841#endif /* INTR0x60_MSI_7_NUM */
842#endif /* INTR0x60_MSI_START_ADDRESS */
843
844#ifdef INTR0x60_PM_PME_EQN
845 ! PM_PME-to-Event Queue Mapping registers
846intr0x60_sys_init_piu_pm_pme_mapping:
847 set 1, %l3
848 sllx %l3, 63, %l3 ! V is bit 63
849 best_set_reg(PCI_E_PM_PME_MAP_ADDR, %l1, %l2)
850 best_set_reg(INTR0x60_PM_PME_EQN, %l1, %l5)
851 add %l3, %l5, %l5
852 stx %l5, [%l2]
853#endif /* INTR0x60_PM_PME_EQN */
854
855#ifdef INTR0x60_PME_TO_ACK_EQN
856 ! PME_TO_ACK-to-Event Queue Mapping registers
857intr0x60_sys_init_piu_pme_to_ack_mapping:
858 set 1, %l3
859 sllx %l3, 63, %l3 ! V is bit 63
860 best_set_reg(PCI_E_PME_ACK_MAP_ADDR, %l1, %l2)
861 best_set_reg(INTR0x60_PME_TO_ACK_EQN, %l1, %l5)
862 add %l3, %l5, %l5
863 stx %l5, [%l2]
864#endif /* INTR0x60_PME_TO_ACK_EQN */
865
866
867
868#if INTR0x60_MONDO_20_V || INTR0x60_INIT_ALL_PIU_INT_MAP
869intr0x60_sys_init_piu_int_map_mondo_20:
870 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(20-20)),
871 %l1, %l3)
872 best_set_reg(mpeval((INTR0x60_MONDO_20_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
873 (INTR0x60_MONDO_20_V << PCI_E_INT_MAP_V_SHIFT)+
874 (INTR0x60_MONDO_20_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
875 (1 << (INTR0x60_MONDO_20_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
876 %l1, %l2)
877#ifdef PORTABLE_CORE
878 set 0x38, %l1
879 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
880 andn %l2, %l1, %l2
881 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
882 or %l1, %l2, %l2 ! Use core ID of core running on
883#endif
884 stx %l2, [%l3]
885#endif /* INTR0x60_MONDO_20_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
886
887#if INTR0x60_MONDO_21_V || INTR0x60_INIT_ALL_PIU_INT_MAP
888intr0x60_sys_init_piu_int_map_mondo_21:
889 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(21-20)),
890 %l1, %l3)
891 best_set_reg(mpeval((INTR0x60_MONDO_21_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
892 (INTR0x60_MONDO_21_V << PCI_E_INT_MAP_V_SHIFT)+
893 (INTR0x60_MONDO_21_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
894 (1 << (INTR0x60_MONDO_21_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
895 %l1, %l2)
896#ifdef PORTABLE_CORE
897 set 0x38, %l1
898 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
899 andn %l2, %l1, %l2
900 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
901 or %l1, %l2, %l2 ! Use core ID of core running on
902#endif
903 stx %l2, [%l3]
904#endif /* INTR0x60_MONDO_21_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
905
906#if INTR0x60_MONDO_22_V || INTR0x60_INIT_ALL_PIU_INT_MAP
907intr0x60_sys_init_piu_int_map_mondo_22:
908 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(22-20)),
909 %l1, %l3)
910 best_set_reg(mpeval((INTR0x60_MONDO_22_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
911 (INTR0x60_MONDO_22_V << PCI_E_INT_MAP_V_SHIFT)+
912 (INTR0x60_MONDO_22_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
913 (1 << (INTR0x60_MONDO_22_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
914 %l1, %l2)
915#ifdef PORTABLE_CORE
916 set 0x38, %l1
917 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
918 andn %l2, %l1, %l2
919 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
920 or %l1, %l2, %l2 ! Use core ID of core running on
921#endif
922 stx %l2, [%l3]
923#endif /* INTR0x60_MONDO_22_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
924
925#if INTR0x60_MONDO_23_V || INTR0x60_INIT_ALL_PIU_INT_MAP
926intr0x60_sys_init_piu_int_map_mondo_23:
927 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(23-20)),
928 %l1, %l3)
929 best_set_reg(mpeval((INTR0x60_MONDO_23_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
930 (INTR0x60_MONDO_23_V << PCI_E_INT_MAP_V_SHIFT)+
931 (INTR0x60_MONDO_23_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
932 (1 << (INTR0x60_MONDO_23_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
933 %l1, %l2)
934#ifdef PORTABLE_CORE
935 set 0x38, %l1
936 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
937 andn %l2, %l1, %l2
938 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
939 or %l1, %l2, %l2 ! Use core ID of core running on
940#endif
941 stx %l2, [%l3]
942#endif /* INTR0x60_MONDO_23_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
943
944#if INTR0x60_MONDO_24_V || INTR0x60_INIT_ALL_PIU_INT_MAP
945intr0x60_sys_init_piu_int_map_mondo_24:
946 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(24-20)),
947 %l1, %l3)
948 best_set_reg(mpeval((INTR0x60_MONDO_24_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
949 (INTR0x60_MONDO_24_V << PCI_E_INT_MAP_V_SHIFT)+
950 (INTR0x60_MONDO_24_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
951 (1 << (INTR0x60_MONDO_24_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
952 %l1, %l2)
953#ifdef PORTABLE_CORE
954 set 0x38, %l1
955 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
956 andn %l2, %l1, %l2
957 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
958 or %l1, %l2, %l2 ! Use core ID of core running on
959#endif
960 stx %l2, [%l3]
961#endif /* INTR0x60_MONDO_24_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
962
963#if INTR0x60_MONDO_25_V || INTR0x60_INIT_ALL_PIU_INT_MAP
964intr0x60_sys_init_piu_int_map_mondo_25:
965 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(25-20)),
966 %l1, %l3)
967 best_set_reg(mpeval((INTR0x60_MONDO_25_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
968 (INTR0x60_MONDO_25_V << PCI_E_INT_MAP_V_SHIFT)+
969 (INTR0x60_MONDO_25_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
970 (1 << (INTR0x60_MONDO_25_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
971 %l1, %l2)
972#ifdef PORTABLE_CORE
973 set 0x38, %l1
974 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
975 andn %l2, %l1, %l2
976 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
977 or %l1, %l2, %l2 ! Use core ID of core running on
978#endif
979 stx %l2, [%l3]
980#endif /* INTR0x60_MONDO_25_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
981
982#if INTR0x60_MONDO_26_V || INTR0x60_INIT_ALL_PIU_INT_MAP
983intr0x60_sys_init_piu_int_map_mondo_26:
984 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(26-20)),
985 %l1, %l3)
986 best_set_reg(mpeval((INTR0x60_MONDO_26_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
987 (INTR0x60_MONDO_26_V << PCI_E_INT_MAP_V_SHIFT)+
988 (INTR0x60_MONDO_26_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
989 (1 << (INTR0x60_MONDO_26_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
990 %l1, %l2)
991#ifdef PORTABLE_CORE
992 set 0x38, %l1
993 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
994 andn %l2, %l1, %l2
995 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
996 or %l1, %l2, %l2 ! Use core ID of core running on
997#endif
998 stx %l2, [%l3]
999#endif /* INTR0x60_MONDO_26_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1000
1001#if INTR0x60_MONDO_27_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1002intr0x60_sys_init_piu_int_map_mondo_27:
1003 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(27-20)),
1004 %l1, %l3)
1005 best_set_reg(mpeval((INTR0x60_MONDO_27_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1006 (INTR0x60_MONDO_27_V << PCI_E_INT_MAP_V_SHIFT)+
1007 (INTR0x60_MONDO_27_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1008 (1 << (INTR0x60_MONDO_27_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1009 %l1, %l2)
1010#ifdef PORTABLE_CORE
1011 set 0x38, %l1
1012 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1013 andn %l2, %l1, %l2
1014 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1015 or %l1, %l2, %l2 ! Use core ID of core running on
1016#endif
1017 stx %l2, [%l3]
1018#endif /* INTR0x60_MONDO_27_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1019
1020#if INTR0x60_MONDO_28_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1021intr0x60_sys_init_piu_int_map_mondo_28:
1022 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(28-20)),
1023 %l1, %l3)
1024 best_set_reg(mpeval((INTR0x60_MONDO_28_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1025 (INTR0x60_MONDO_28_V << PCI_E_INT_MAP_V_SHIFT)+
1026 (INTR0x60_MONDO_28_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1027 (1 << (INTR0x60_MONDO_28_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1028 %l1, %l2)
1029#ifdef PORTABLE_CORE
1030 set 0x38, %l1
1031 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1032 andn %l2, %l1, %l2
1033 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1034 or %l1, %l2, %l2 ! Use core ID of core running on
1035#endif
1036 stx %l2, [%l3]
1037#endif /* INTR0x60_MONDO_28_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1038
1039#if INTR0x60_MONDO_29_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1040intr0x60_sys_init_piu_int_map_mondo_29:
1041 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(29-20)),
1042 %l1, %l3)
1043 best_set_reg(mpeval((INTR0x60_MONDO_29_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1044 (INTR0x60_MONDO_29_V << PCI_E_INT_MAP_V_SHIFT)+
1045 (INTR0x60_MONDO_29_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1046 (1 << (INTR0x60_MONDO_29_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1047 %l1, %l2)
1048#ifdef PORTABLE_CORE
1049 set 0x38, %l1
1050 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1051 andn %l2, %l1, %l2
1052 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1053 or %l1, %l2, %l2 ! Use core ID of core running on
1054#endif
1055 stx %l2, [%l3]
1056#endif /* INTR0x60_MONDO_29_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1057
1058#if INTR0x60_MONDO_30_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1059intr0x60_sys_init_piu_int_map_mondo_30:
1060 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(30-20)),
1061 %l1, %l3)
1062 best_set_reg(mpeval((INTR0x60_MONDO_30_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1063 (INTR0x60_MONDO_30_V << PCI_E_INT_MAP_V_SHIFT)+
1064 (INTR0x60_MONDO_30_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1065 (1 << (INTR0x60_MONDO_30_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1066 %l1, %l2)
1067#ifdef PORTABLE_CORE
1068 set 0x38, %l1
1069 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1070 andn %l2, %l1, %l2
1071 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1072 or %l1, %l2, %l2 ! Use core ID of core running on
1073#endif
1074 stx %l2, [%l3]
1075#endif /* INTR0x60_MONDO_30_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1076
1077#if INTR0x60_MONDO_31_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1078intr0x60_sys_init_piu_int_map_mondo_31:
1079 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(31-20)),
1080 %l1, %l3)
1081 best_set_reg(mpeval((INTR0x60_MONDO_31_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1082 (INTR0x60_MONDO_31_V << PCI_E_INT_MAP_V_SHIFT)+
1083 (INTR0x60_MONDO_31_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1084 (1 << (INTR0x60_MONDO_31_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1085 %l1, %l2)
1086#ifdef PORTABLE_CORE
1087 set 0x38, %l1
1088 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1089 andn %l2, %l1, %l2
1090 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1091 or %l1, %l2, %l2 ! Use core ID of core running on
1092#endif
1093 stx %l2, [%l3]
1094#endif /* INTR0x60_MONDO_31_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1095
1096#if INTR0x60_MONDO_32_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1097intr0x60_sys_init_piu_int_map_mondo_32:
1098 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(32-20)),
1099 %l1, %l3)
1100 best_set_reg(mpeval((INTR0x60_MONDO_32_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1101 (INTR0x60_MONDO_32_V << PCI_E_INT_MAP_V_SHIFT)+
1102 (INTR0x60_MONDO_32_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1103 (1 << (INTR0x60_MONDO_32_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1104 %l1, %l2)
1105#ifdef PORTABLE_CORE
1106 set 0x38, %l1
1107 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1108 andn %l2, %l1, %l2
1109 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1110 or %l1, %l2, %l2 ! Use core ID of core running on
1111#endif
1112 stx %l2, [%l3]
1113#endif /* INTR0x60_MONDO_32_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1114
1115#if INTR0x60_MONDO_33_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1116intr0x60_sys_init_piu_int_map_mondo_33:
1117 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(33-20)),
1118 %l1, %l3)
1119 best_set_reg(mpeval((INTR0x60_MONDO_33_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1120 (INTR0x60_MONDO_33_V << PCI_E_INT_MAP_V_SHIFT)+
1121 (INTR0x60_MONDO_33_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1122 (1 << (INTR0x60_MONDO_33_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1123 %l1, %l2)
1124#ifdef PORTABLE_CORE
1125 set 0x38, %l1
1126 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1127 andn %l2, %l1, %l2
1128 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1129 or %l1, %l2, %l2 ! Use core ID of core running on
1130#endif
1131 stx %l2, [%l3]
1132#endif /* INTR0x60_MONDO_33_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1133
1134#if INTR0x60_MONDO_34_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1135intr0x60_sys_init_piu_int_map_mondo_34:
1136 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(34-20)),
1137 %l1, %l3)
1138 best_set_reg(mpeval((INTR0x60_MONDO_34_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1139 (INTR0x60_MONDO_34_V << PCI_E_INT_MAP_V_SHIFT)+
1140 (INTR0x60_MONDO_34_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1141 (1 << (INTR0x60_MONDO_34_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1142 %l1, %l2)
1143#ifdef PORTABLE_CORE
1144 set 0x38, %l1
1145 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1146 andn %l2, %l1, %l2
1147 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1148 or %l1, %l2, %l2 ! Use core ID of core running on
1149#endif
1150 stx %l2, [%l3]
1151#endif /* INTR0x60_MONDO_34_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1152
1153#if INTR0x60_MONDO_35_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1154intr0x60_sys_init_piu_int_map_mondo_35:
1155 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(35-20)),
1156 %l1, %l3)
1157 best_set_reg(mpeval((INTR0x60_MONDO_35_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1158 (INTR0x60_MONDO_35_V << PCI_E_INT_MAP_V_SHIFT)+
1159 (INTR0x60_MONDO_35_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1160 (1 << (INTR0x60_MONDO_35_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1161 %l1, %l2)
1162#ifdef PORTABLE_CORE
1163 set 0x38, %l1
1164 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1165 andn %l2, %l1, %l2
1166 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1167 or %l1, %l2, %l2 ! Use core ID of core running on
1168#endif
1169 stx %l2, [%l3]
1170#endif /* INTR0x60_MONDO_35_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1171
1172#if INTR0x60_MONDO_36_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1173intr0x60_sys_init_piu_int_map_mondo_36:
1174 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(36-20)),
1175 %l1, %l3)
1176 best_set_reg(mpeval((INTR0x60_MONDO_36_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1177 (INTR0x60_MONDO_36_V << PCI_E_INT_MAP_V_SHIFT)+
1178 (INTR0x60_MONDO_36_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1179 (1 << (INTR0x60_MONDO_36_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1180 %l1, %l2)
1181#ifdef PORTABLE_CORE
1182 set 0x38, %l1
1183 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1184 andn %l2, %l1, %l2
1185 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1186 or %l1, %l2, %l2 ! Use core ID of core running on
1187#endif
1188 stx %l2, [%l3]
1189#endif /* INTR0x60_MONDO_36_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1190
1191#if INTR0x60_MONDO_37_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1192intr0x60_sys_init_piu_int_map_mondo_37:
1193 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(37-20)),
1194 %l1, %l3)
1195 best_set_reg(mpeval((INTR0x60_MONDO_37_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1196 (INTR0x60_MONDO_37_V << PCI_E_INT_MAP_V_SHIFT)+
1197 (INTR0x60_MONDO_37_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1198 (1 << (INTR0x60_MONDO_37_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1199 %l1, %l2)
1200#ifdef PORTABLE_CORE
1201 set 0x38, %l1
1202 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1203 andn %l2, %l1, %l2
1204 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1205 or %l1, %l2, %l2 ! Use core ID of core running on
1206#endif
1207 stx %l2, [%l3]
1208#endif /* INTR0x60_MONDO_37_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1209
1210#if INTR0x60_MONDO_38_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1211intr0x60_sys_init_piu_int_map_mondo_38:
1212 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(38-20)),
1213 %l1, %l3)
1214 best_set_reg(mpeval((INTR0x60_MONDO_38_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1215 (INTR0x60_MONDO_38_V << PCI_E_INT_MAP_V_SHIFT)+
1216 (INTR0x60_MONDO_38_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1217 (1 << (INTR0x60_MONDO_38_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1218 %l1, %l2)
1219#ifdef PORTABLE_CORE
1220 set 0x38, %l1
1221 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1222 andn %l2, %l1, %l2
1223 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1224 or %l1, %l2, %l2 ! Use core ID of core running on
1225#endif
1226 stx %l2, [%l3]
1227#endif /* INTR0x60_MONDO_38_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1228
1229#if INTR0x60_MONDO_39_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1230intr0x60_sys_init_piu_int_map_mondo_39:
1231 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(39-20)),
1232 %l1, %l3)
1233 best_set_reg(mpeval((INTR0x60_MONDO_39_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1234 (INTR0x60_MONDO_39_V << PCI_E_INT_MAP_V_SHIFT)+
1235 (INTR0x60_MONDO_39_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1236 (1 << (INTR0x60_MONDO_39_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1237 %l1, %l2)
1238#ifdef PORTABLE_CORE
1239 set 0x38, %l1
1240 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1241 andn %l2, %l1, %l2
1242 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1243 or %l1, %l2, %l2 ! Use core ID of core running on
1244#endif
1245 stx %l2, [%l3]
1246#endif /* INTR0x60_MONDO_39_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1247
1248#if INTR0x60_MONDO_40_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1249intr0x60_sys_init_piu_int_map_mondo_40:
1250 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(40-20)),
1251 %l1, %l3)
1252 best_set_reg(mpeval((INTR0x60_MONDO_40_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1253 (INTR0x60_MONDO_40_V << PCI_E_INT_MAP_V_SHIFT)+
1254 (INTR0x60_MONDO_40_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1255 (1 << (INTR0x60_MONDO_40_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1256 %l1, %l2)
1257#ifdef PORTABLE_CORE
1258 set 0x38, %l1
1259 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1260 andn %l2, %l1, %l2
1261 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1262 or %l1, %l2, %l2 ! Use core ID of core running on
1263#endif
1264 stx %l2, [%l3]
1265#endif /* INTR0x60_MONDO_40_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1266
1267#if INTR0x60_MONDO_41_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1268intr0x60_sys_init_piu_int_map_mondo_41:
1269 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(41-20)),
1270 %l1, %l3)
1271 best_set_reg(mpeval((INTR0x60_MONDO_41_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1272 (INTR0x60_MONDO_41_V << PCI_E_INT_MAP_V_SHIFT)+
1273 (INTR0x60_MONDO_41_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1274 (1 << (INTR0x60_MONDO_41_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1275 %l1, %l2)
1276#ifdef PORTABLE_CORE
1277 set 0x38, %l1
1278 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1279 andn %l2, %l1, %l2
1280 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1281 or %l1, %l2, %l2 ! Use core ID of core running on
1282#endif
1283 stx %l2, [%l3]
1284#endif /* INTR0x60_MONDO_41_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1285
1286#if INTR0x60_MONDO_42_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1287intr0x60_sys_init_piu_int_map_mondo_42:
1288 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(42-20)),
1289 %l1, %l3)
1290 best_set_reg(mpeval((INTR0x60_MONDO_42_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1291 (INTR0x60_MONDO_42_V << PCI_E_INT_MAP_V_SHIFT)+
1292 (INTR0x60_MONDO_42_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1293 (1 << (INTR0x60_MONDO_42_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1294 %l1, %l2)
1295#ifdef PORTABLE_CORE
1296 set 0x38, %l1
1297 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1298 andn %l2, %l1, %l2
1299 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1300 or %l1, %l2, %l2 ! Use core ID of core running on
1301#endif
1302 stx %l2, [%l3]
1303#endif /* INTR0x60_MONDO_42_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1304
1305#if INTR0x60_MONDO_43_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1306intr0x60_sys_init_piu_int_map_mondo_43:
1307 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(43-20)),
1308 %l1, %l3)
1309 best_set_reg(mpeval((INTR0x60_MONDO_43_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1310 (INTR0x60_MONDO_43_V << PCI_E_INT_MAP_V_SHIFT)+
1311 (INTR0x60_MONDO_43_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1312 (1 << (INTR0x60_MONDO_43_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1313 %l1, %l2)
1314#ifdef PORTABLE_CORE
1315 set 0x38, %l1
1316 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1317 andn %l2, %l1, %l2
1318 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1319 or %l1, %l2, %l2 ! Use core ID of core running on
1320#endif
1321 stx %l2, [%l3]
1322#endif /* INTR0x60_MONDO_43_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1323
1324#if INTR0x60_MONDO_44_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1325intr0x60_sys_init_piu_int_map_mondo_44:
1326 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(44-20)),
1327 %l1, %l3)
1328 best_set_reg(mpeval((INTR0x60_MONDO_44_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1329 (INTR0x60_MONDO_44_V << PCI_E_INT_MAP_V_SHIFT)+
1330 (INTR0x60_MONDO_44_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1331 (1 << (INTR0x60_MONDO_44_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1332 %l1, %l2)
1333#ifdef PORTABLE_CORE
1334 set 0x38, %l1
1335 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1336 andn %l2, %l1, %l2
1337 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1338 or %l1, %l2, %l2 ! Use core ID of core running on
1339#endif
1340 stx %l2, [%l3]
1341#endif /* INTR0x60_MONDO_44_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1342
1343#if INTR0x60_MONDO_45_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1344intr0x60_sys_init_piu_int_map_mondo_45:
1345 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(45-20)),
1346 %l1, %l3)
1347 best_set_reg(mpeval((INTR0x60_MONDO_45_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1348 (INTR0x60_MONDO_45_V << PCI_E_INT_MAP_V_SHIFT)+
1349 (INTR0x60_MONDO_45_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1350 (1 << (INTR0x60_MONDO_45_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1351 %l1, %l2)
1352#ifdef PORTABLE_CORE
1353 set 0x38, %l1
1354 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1355 andn %l2, %l1, %l2
1356 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1357 or %l1, %l2, %l2 ! Use core ID of core running on
1358#endif
1359 stx %l2, [%l3]
1360#endif /* INTR0x60_MONDO_45_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1361
1362#if INTR0x60_MONDO_46_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1363intr0x60_sys_init_piu_int_map_mondo_46:
1364 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(46-20)),
1365 %l1, %l3)
1366 best_set_reg(mpeval((INTR0x60_MONDO_46_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1367 (INTR0x60_MONDO_46_V << PCI_E_INT_MAP_V_SHIFT)+
1368 (INTR0x60_MONDO_46_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1369 (1 << (INTR0x60_MONDO_46_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1370 %l1, %l2)
1371#ifdef PORTABLE_CORE
1372 set 0x38, %l1
1373 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1374 andn %l2, %l1, %l2
1375 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1376 or %l1, %l2, %l2 ! Use core ID of core running on
1377#endif
1378 stx %l2, [%l3]
1379#endif /* INTR0x60_MONDO_46_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1380
1381#if INTR0x60_MONDO_47_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1382intr0x60_sys_init_piu_int_map_mondo_47:
1383 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(47-20)),
1384 %l1, %l3)
1385 best_set_reg(mpeval((INTR0x60_MONDO_47_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1386 (INTR0x60_MONDO_47_V << PCI_E_INT_MAP_V_SHIFT)+
1387 (INTR0x60_MONDO_47_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1388 (1 << (INTR0x60_MONDO_47_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1389 %l1, %l2)
1390#ifdef PORTABLE_CORE
1391 set 0x38, %l1
1392 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1393 andn %l2, %l1, %l2
1394 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1395 or %l1, %l2, %l2 ! Use core ID of core running on
1396#endif
1397 stx %l2, [%l3]
1398#endif /* INTR0x60_MONDO_47_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1399
1400#if INTR0x60_MONDO_48_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1401intr0x60_sys_init_piu_int_map_mondo_48:
1402 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(48-20)),
1403 %l1, %l3)
1404 best_set_reg(mpeval((INTR0x60_MONDO_48_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1405 (INTR0x60_MONDO_48_V << PCI_E_INT_MAP_V_SHIFT)+
1406 (INTR0x60_MONDO_48_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1407 (1 << (INTR0x60_MONDO_48_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1408 %l1, %l2)
1409#ifdef PORTABLE_CORE
1410 set 0x38, %l1
1411 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1412 andn %l2, %l1, %l2
1413 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1414 or %l1, %l2, %l2 ! Use core ID of core running on
1415#endif
1416 stx %l2, [%l3]
1417#endif /* INTR0x60_MONDO_48_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1418
1419#if INTR0x60_MONDO_49_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1420intr0x60_sys_init_piu_int_map_mondo_49:
1421 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(49-20)),
1422 %l1, %l3)
1423 best_set_reg(mpeval((INTR0x60_MONDO_49_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1424 (INTR0x60_MONDO_49_V << PCI_E_INT_MAP_V_SHIFT)+
1425 (INTR0x60_MONDO_49_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1426 (1 << (INTR0x60_MONDO_49_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1427 %l1, %l2)
1428#ifdef PORTABLE_CORE
1429 set 0x38, %l1
1430 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1431 andn %l2, %l1, %l2
1432 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1433 or %l1, %l2, %l2 ! Use core ID of core running on
1434#endif
1435 stx %l2, [%l3]
1436#endif /* INTR0x60_MONDO_49_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1437
1438#if INTR0x60_MONDO_50_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1439intr0x60_sys_init_piu_int_map_mondo_50:
1440 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(50-20)),
1441 %l1, %l3)
1442 best_set_reg(mpeval((INTR0x60_MONDO_50_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1443 (INTR0x60_MONDO_50_V << PCI_E_INT_MAP_V_SHIFT)+
1444 (INTR0x60_MONDO_50_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1445 (1 << (INTR0x60_MONDO_50_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1446 %l1, %l2)
1447#ifdef PORTABLE_CORE
1448 set 0x38, %l1
1449 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1450 andn %l2, %l1, %l2
1451 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1452 or %l1, %l2, %l2 ! Use core ID of core running on
1453#endif
1454 stx %l2, [%l3]
1455#endif /* INTR0x60_MONDO_50_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1456
1457#if INTR0x60_MONDO_51_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1458intr0x60_sys_init_piu_int_map_mondo_51:
1459 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(51-20)),
1460 %l1, %l3)
1461 best_set_reg(mpeval((INTR0x60_MONDO_51_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1462 (INTR0x60_MONDO_51_V << PCI_E_INT_MAP_V_SHIFT)+
1463 (INTR0x60_MONDO_51_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1464 (1 << (INTR0x60_MONDO_51_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1465 %l1, %l2)
1466#ifdef PORTABLE_CORE
1467 set 0x38, %l1
1468 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1469 andn %l2, %l1, %l2
1470 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1471 or %l1, %l2, %l2 ! Use core ID of core running on
1472#endif
1473 stx %l2, [%l3]
1474#endif /* INTR0x60_MONDO_51_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1475
1476#if INTR0x60_MONDO_52_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1477intr0x60_sys_init_piu_int_map_mondo_52:
1478 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(52-20)),
1479 %l1, %l3)
1480 best_set_reg(mpeval((INTR0x60_MONDO_52_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1481 (INTR0x60_MONDO_52_V << PCI_E_INT_MAP_V_SHIFT)+
1482 (INTR0x60_MONDO_52_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1483 (1 << (INTR0x60_MONDO_52_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1484 %l1, %l2)
1485#ifdef PORTABLE_CORE
1486 set 0x38, %l1
1487 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1488 andn %l2, %l1, %l2
1489 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1490 or %l1, %l2, %l2 ! Use core ID of core running on
1491#endif
1492 stx %l2, [%l3]
1493#endif /* INTR0x60_MONDO_52_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1494
1495#if INTR0x60_MONDO_53_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1496intr0x60_sys_init_piu_int_map_mondo_53:
1497 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(53-20)),
1498 %l1, %l3)
1499 best_set_reg(mpeval((INTR0x60_MONDO_53_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1500 (INTR0x60_MONDO_53_V << PCI_E_INT_MAP_V_SHIFT)+
1501 (INTR0x60_MONDO_53_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1502 (1 << (INTR0x60_MONDO_53_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1503 %l1, %l2)
1504#ifdef PORTABLE_CORE
1505 set 0x38, %l1
1506 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1507 andn %l2, %l1, %l2
1508 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1509 or %l1, %l2, %l2 ! Use core ID of core running on
1510#endif
1511 stx %l2, [%l3]
1512#endif /* INTR0x60_MONDO_53_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1513
1514#if INTR0x60_MONDO_54_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1515intr0x60_sys_init_piu_int_map_mondo_54:
1516 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(54-20)),
1517 %l1, %l3)
1518 best_set_reg(mpeval((INTR0x60_MONDO_54_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1519 (INTR0x60_MONDO_54_V << PCI_E_INT_MAP_V_SHIFT)+
1520 (INTR0x60_MONDO_54_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1521 (1 << (INTR0x60_MONDO_54_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1522 %l1, %l2)
1523#ifdef PORTABLE_CORE
1524 set 0x38, %l1
1525 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1526 andn %l2, %l1, %l2
1527 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1528 or %l1, %l2, %l2 ! Use core ID of core running on
1529#endif
1530 stx %l2, [%l3]
1531#endif /* INTR0x60_MONDO_54_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1532
1533#if INTR0x60_MONDO_55_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1534intr0x60_sys_init_piu_int_map_mondo_55:
1535 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(55-20)),
1536 %l1, %l3)
1537 best_set_reg(mpeval((INTR0x60_MONDO_55_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1538 (INTR0x60_MONDO_55_V << PCI_E_INT_MAP_V_SHIFT)+
1539 (INTR0x60_MONDO_55_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1540 (1 << (INTR0x60_MONDO_55_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1541 %l1, %l2)
1542#ifdef PORTABLE_CORE
1543 set 0x38, %l1
1544 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1545 andn %l2, %l1, %l2
1546 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1547 or %l1, %l2, %l2 ! Use core ID of core running on
1548#endif
1549 stx %l2, [%l3]
1550#endif /* INTR0x60_MONDO_55_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1551
1552#if INTR0x60_MONDO_56_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1553intr0x60_sys_init_piu_int_map_mondo_56:
1554 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(56-20)),
1555 %l1, %l3)
1556 best_set_reg(mpeval((INTR0x60_MONDO_56_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1557 (INTR0x60_MONDO_56_V << PCI_E_INT_MAP_V_SHIFT)+
1558 (INTR0x60_MONDO_56_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1559 (1 << (INTR0x60_MONDO_56_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1560 %l1, %l2)
1561#ifdef PORTABLE_CORE
1562 set 0x38, %l1
1563 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1564 andn %l2, %l1, %l2
1565 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1566 or %l1, %l2, %l2 ! Use core ID of core running on
1567#endif
1568 stx %l2, [%l3]
1569#endif /* INTR0x60_MONDO_56_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1570
1571#if INTR0x60_MONDO_57_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1572intr0x60_sys_init_piu_int_map_mondo_57:
1573 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(57-20)),
1574 %l1, %l3)
1575 best_set_reg(mpeval((INTR0x60_MONDO_57_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1576 (INTR0x60_MONDO_57_V << PCI_E_INT_MAP_V_SHIFT)+
1577 (INTR0x60_MONDO_57_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1578 (1 << (INTR0x60_MONDO_57_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1579 %l1, %l2)
1580#ifdef PORTABLE_CORE
1581 set 0x38, %l1
1582 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1583 andn %l2, %l1, %l2
1584 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1585 or %l1, %l2, %l2 ! Use core ID of core running on
1586#endif
1587 stx %l2, [%l3]
1588#endif /* INTR0x60_MONDO_57_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1589
1590#if INTR0x60_MONDO_58_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1591intr0x60_sys_init_piu_int_map_mondo_58:
1592 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(58-20)),
1593 %l1, %l3)
1594 best_set_reg(mpeval((INTR0x60_MONDO_58_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1595 (INTR0x60_MONDO_58_V << PCI_E_INT_MAP_V_SHIFT)+
1596 (INTR0x60_MONDO_58_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1597 (1 << (INTR0x60_MONDO_58_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1598 %l1, %l2)
1599#ifdef PORTABLE_CORE
1600 set 0x38, %l1
1601 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1602 andn %l2, %l1, %l2
1603 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1604 or %l1, %l2, %l2 ! Use core ID of core running on
1605#endif
1606 stx %l2, [%l3]
1607#endif /* INTR0x60_MONDO_58_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1608
1609#if INTR0x60_MONDO_59_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1610intr0x60_sys_init_piu_int_map_mondo_59:
1611 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(59-20)),
1612 %l1, %l3)
1613 best_set_reg(mpeval((INTR0x60_MONDO_59_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1614 (INTR0x60_MONDO_59_V << PCI_E_INT_MAP_V_SHIFT)+
1615 (INTR0x60_MONDO_59_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1616 (1 << (INTR0x60_MONDO_59_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1617 %l1, %l2)
1618#ifdef PORTABLE_CORE
1619 set 0x38, %l1
1620 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1621 andn %l2, %l1, %l2
1622 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1623 or %l1, %l2, %l2 ! Use core ID of core running on
1624#endif
1625 stx %l2, [%l3]
1626#endif /* INTR0x60_MONDO_59_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1627
1628#if INTR0x60_MONDO_62_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1629intr0x60_sys_init_piu_int_map_mondo_62:
1630 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(62-20)),
1631 %l1, %l3)
1632 best_set_reg(mpeval((INTR0x60_MONDO_62_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1633 (INTR0x60_MONDO_62_V << PCI_E_INT_MAP_V_SHIFT)+
1634 (INTR0x60_MONDO_62_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1635 (1 << (INTR0x60_MONDO_62_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1636 %l1, %l2)
1637#ifdef PORTABLE_CORE
1638 set 0x38, %l1
1639 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1640 andn %l2, %l1, %l2
1641 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1642 or %l1, %l2, %l2 ! Use core ID of core running on
1643#endif
1644 stx %l2, [%l3]
1645#endif /* INTR0x60_MONDO_62_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1646
1647#if INTR0x60_MONDO_63_V || INTR0x60_INIT_ALL_PIU_INT_MAP
1648intr0x60_sys_init_piu_int_map_mondo_63:
1649 best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(63-20)),
1650 %l1, %l3)
1651 best_set_reg(mpeval((INTR0x60_MONDO_63_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
1652 (INTR0x60_MONDO_63_V << PCI_E_INT_MAP_V_SHIFT)+
1653 (INTR0x60_MONDO_63_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
1654 (1 << (INTR0x60_MONDO_63_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
1655 %l1, %l2)
1656#ifdef PORTABLE_CORE
1657 set 0x38, %l1
1658 sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1659 andn %l2, %l1, %l2
1660 sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
1661 or %l1, %l2, %l2 ! Use core ID of core running on
1662#endif
1663 stx %l2, [%l3]
1664#endif /* INTR0x60_MONDO_63_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
1665
1666#endif /* INTR0x60_MONDO_IV */
Full OpenSPARC design & verification tarball including full HDL.