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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / macros.h
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: macros.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#ifndef ALREADY_INCLUDED_MACROS_DOT_H
39#define ALREADY_INCLUDED_MACROS_DOT_H
40
41#define SAVE_WINDOW(BASE) \
42 stx %l0, [BASE + (0*4)]; \
43 stx %l1, [BASE + (2*4)]; \
44 stx %l2, [BASE + (4*4)]; \
45 stx %l3, [BASE + (6*4)]; \
46 stx %l4, [BASE + (8*4)]; \
47 stx %l5, [BASE + (10*4)]; \
48 stx %l6, [BASE + (12*4)]; \
49 stx %l7, [BASE + (14*4)]; \
50 stx %i0, [BASE + (16*4)]; \
51 stx %i1, [BASE + (18*4)]; \
52 stx %i2, [BASE + (20*4)]; \
53 stx %i3, [BASE + (22*4)]; \
54 stx %i4, [BASE + (24*4)]; \
55 stx %i5, [BASE + (26*4)]; \
56 stx %i6, [BASE + (28*4)]; \
57 stx %i7, [BASE + (30*4)];
58
59#define RESTORE_WINDOW(BASE) \
60 ldx [BASE + (0*4)], %l0; \
61 ldx [BASE + (2*4)], %l1; \
62 ldx [BASE + (4*4)], %l2; \
63 ldx [BASE + (6*4)], %l3; \
64 ldx [BASE + (8*4)], %l4; \
65 ldx [BASE + (10*4)], %l5; \
66 ldx [BASE + (12*4)], %l6; \
67 ldx [BASE + (14*4)], %l7; \
68 ldx [BASE + (16*4)], %i0; \
69 ldx [BASE + (18*4)], %i1; \
70 ldx [BASE + (20*4)], %i2; \
71 ldx [BASE + (22*4)], %i3; \
72 ldx [BASE + (24*4)], %i4; \
73 ldx [BASE + (26*4)], %i5; \
74 ldx [BASE + (28*4)], %i6; \
75 ldx [BASE + (30*4)], %i7;
76
77
78/*
79Store out FP registers to the BBC ram to expose the data
80to the pins for tester verification. This macro can be
81planted throughout any diag to store the FP data at will.
82Activitating the FPREG_STORES macro also causes all the FP
83registers to be initialized.
84*/
85#define FPREG_STORES(ADR_REG, ADR_REG_TMP) \
86 setx 0x7ffffffff00, ADR_REG_TMP, ADR_REG; \
87 mov 0x15, %asi; \
88 stda %f0, [ADR_REG] %asi; \
89 stda %f2, [ADR_REG] %asi; \
90 stda %f4, [ADR_REG] %asi; \
91 stda %f6, [ADR_REG] %asi; \
92 stda %f8, [ADR_REG] %asi; \
93 stda %f10, [ADR_REG] %asi; \
94 stda %f12, [ADR_REG] %asi; \
95 stda %f14, [ADR_REG] %asi; \
96 stda %f16, [ADR_REG] %asi; \
97 stda %f18, [ADR_REG] %asi; \
98 stda %f20, [ADR_REG] %asi; \
99 stda %f22, [ADR_REG] %asi; \
100 stda %f24, [ADR_REG] %asi; \
101 stda %f26, [ADR_REG] %asi; \
102 stda %f28, [ADR_REG] %asi; \
103 stda %f30, [ADR_REG] %asi; \
104 stda %f32, [ADR_REG] %asi; \
105 stda %f34, [ADR_REG] %asi; \
106 stda %f36, [ADR_REG] %asi; \
107 stda %f38, [ADR_REG] %asi; \
108 stda %f40, [ADR_REG] %asi; \
109 stda %f42, [ADR_REG] %asi; \
110 stda %f44, [ADR_REG] %asi; \
111 stda %f46, [ADR_REG] %asi; \
112 stda %f48, [ADR_REG] %asi; \
113 stda %f50, [ADR_REG] %asi; \
114 stda %f52, [ADR_REG] %asi; \
115 stda %f54, [ADR_REG] %asi; \
116 stda %f56, [ADR_REG] %asi; \
117 stda %f58, [ADR_REG] %asi; \
118 stda %f60, [ADR_REG] %asi; \
119 stda %f62, [ADR_REG] %asi; \
120 ldxa [ADR_REG] %asi, %g0; \
121
122#define DUMP_LOCALS(ADR_REG, ADR_REG_TMP) \
123 setx 0x7ffffffff00, ADR_REG_TMP, ADR_REG; \
124 mov 0x15, %asi; \
125 stxa %l0, [ADR_REG] %asi; \
126 stxa %l1, [ADR_REG] %asi; \
127 stxa %l2, [ADR_REG] %asi; \
128 stxa %l3, [ADR_REG] %asi; \
129 stxa %l4, [ADR_REG] %asi; \
130 stxa %l5, [ADR_REG] %asi; \
131 stxa %l6, [ADR_REG] %asi; \
132 stxa %l7, [ADR_REG] %asi; \
133
134#define DUMP_OUTS(ADR_REG, ADR_REG_TMP) \
135 setx 0x7ffffffff00, ADR_REG_TMP, ADR_REG; \
136 mov 0x15, %asi; \
137 stxa %o0, [ADR_REG] %asi; \
138 stxa %o1, [ADR_REG] %asi; \
139 stxa %o2, [ADR_REG] %asi; \
140 stxa %o3, [ADR_REG] %asi; \
141 stxa %o4, [ADR_REG] %asi; \
142 stxa %o5, [ADR_REG] %asi; \
143 stxa %o6, [ADR_REG] %asi; \
144 stxa %o7, [ADR_REG] %asi; \
145
146#define DUMP_GLOBALS(ADR_REG, ADR_REG_TMP) \
147 setx 0x7ffffffff00, ADR_REG_TMP, ADR_REG; \
148 mov 0x15, %asi; \
149 stxa %g1, [ADR_REG] %asi; \
150 stxa %g2, [ADR_REG] %asi; \
151 stxa %g3, [ADR_REG] %asi; \
152 stxa %g4, [ADR_REG] %asi; \
153 stxa %g5, [ADR_REG] %asi; \
154 stxa %g6, [ADR_REG] %asi; \
155 stxa %g7, [ADR_REG] %asi; \
156
157define(INIT_MEM,
158 `define( `INIT_VAL', $1)
159 define( `DATA_SIZE', eval($3))
160 define( `BLK_LEN', eval($2))
161 define( `IT_COUNT', 1)
162 define( `MOD_VAL', $5)
163 define( `OPR1', $4)
164 define( `OPR2', $6)
165 define( `OPND3', $7)
166 ifelse(DATA_SIZE,4,`GEN_VALUE',
167 DATA_SIZE,2,`GEN_VALUE',
168 DATA_SIZE,1,`GEN_VALUE',
169 `errprint(ERROR: "INIT_MEM" data_size=DATA_SIZE is illegal)')')
170
171define(GEN_VALUE,
172 `ifelse(DATA_SIZE,4,.word eval(INIT_VAL OPR1 MOD_VAL),
173 DATA_SIZE,2,.half eval(INIT_VAL OPR1 MOD_VAL),
174 DATA_SIZE,1,.byte eval(INIT_VAL OPR1 MOD_VAL)) dnl
175 ifelse(eval(len(OPR1)>0),1,`define(`MOD_VAL',eval(MOD_VAL OPR2 OPND3))') dnl
176 define(`IT_COUNT', incr(IT_COUNT))
177 ifelse(eval(IT_COUNT>BLK_LEN),1,,`GEN_VALUE')')
178
179/* usage: SET_64(value_hi, value_lo, tmp_reg, dest_reg)
180 value_hi : Hi word of the desired extended word -- dword[63:32]
181 value_lo : Lo word of the desired extended word -- dword[31:0]
182 tmp_reg : temporary register
183 dest_reg : destination register
184*/
185define(SET_64, `sethi %hi($1), $3
186 or $3, %lo($1), $3
187 sllx $3, 32, $3
188 sethi %hi($2), $4
189 or $4, $3, $4
190 or $4, %lo($2), $4')
191
192/* CHECK_SRESULT(reg,imm,tmp_reg1)
193 reg: a reg contain value want to compare
194 imm: an immediate value 13 bits want to compare
195 tmp_reg1: a temparory reg
196*/
197define(CHECK_SRESULT, `set $2, $3
198 sub $1,$3,$3
199 sra $3,0,$3
200 brz,pt $3,1f
201 nop
202 ta 0x1 /* ta T_BAD_TRAP */
203 1:')
204
205
206/* usage: CHECK_FSRESULT(fp register, value, tmp_reg1, tmp_reg2, MEM_DUMP_POINTER)
207 fp register : single precision floating point register whose contents need comparison
208 value : The expected value
209 tmp_reg1 : a temporary reg buffer, integer register
210 tmp_reg2 : a temporary reg buffer, integer register
211 MEM_DUMP_POINTER : pointer to the memory dump area where the
212 machine state will be dumped if a miscompare occurs.
213*/
214
215define(CHECK_FSRESULT, `st $1, [$5]
216 lduw [$5], $3
217 set $2, $4
218 sub $3, $4, $3
219 srl $3, 0, $3 !clear upper 32-bit, set might sign extend upper 32-bits.
220 brz,pt $3, 1f
221 nop
222 ta T_BAD_TRAP
223 1:')
224
225/* usage: CHECK_FDRESULT(fp register, value_hi, value_lo,tmp_reg1, tmp_reg2, MEM_DUMP_POINTER)
226 fp register : single precision floating point register whose contents need comparison
227 value_hi, value_lo : The expected value
228 tmp_reg1 : a temporary reg buffer, integer register
229 tmp_reg2 : a temporary reg buffer, integer register
230 MEM_DUMP_POINTER : pointer to the memory dump area where the
231 machine state will be dumped if a miscompare occurs.
232*/
233
234define(CHECK_FDRESULT, `set $2, $4
235 sllx $4, 32, $4 !move left 32-bits. upper-32bit of 64-bit value.
236 set $3, $5
237 srl $5,0, $5 !clear upper-32 bits
238 or $4, $5, $5
239 std $1, [$6]
240 ldx [$6], $4
241 sub $4, $5, $4
242 brz,pt $4, 1f
243 nop
244 ta T_BAD_TRAP
245 1:')
246
247/* usuage: CHECK_XRESULT(%?,reg:value_high,reg:value_low,tmp_reg1)
248 %? 64 bit reg which has the value need to check
249 value_high the high 32 bits of the answer in reg
250 value_low the low 32 bits of the answer in reg
251 tmp_reg1 a temparory reg buffer
252*/
253define(CHECK_XRESULT,`mov $2,$4
254 sllx $4,32,$4
255 add $4,$3,$4
256 sub $1,$4,$4
257 brz,pt $4,1f
258 nop
259 ta T_BAD_TRAP
260 1:')
261
262/*usuage: CHECK_XREGS(reg1,reg2,tmp_reg1,tmp_reg2,label)
263 reg1 and reg2 : are 64 bits regs want to compare
264 tmp_reg1 & tmp_reg2: are buffer regs
265 label:place to go when not matched . e.g error_detected or label in prog
266*/
267define(CHECK_XREGS,`mov $1,$3
268 sub $2,$3,$3
269 brz,pt $3,1f
270 nop
271 ta T_BAD_TRAP
272 1:')
273
274/*usuage: REGS_COMPARE(reg1,reg2,tmp_reg1,tmp_reg2,label)
275 reg1 and reg2 : are 64 bits regs want to compare
276 tmp_reg1 & tmp_reg2: are buffer regs
277 label:place to go when not matched . e.g error_detected or label in prog
278*/
279define(REGS_COMPARE,`mov $1,$3
280 mov $2,$4
281 sub $3,$4,$3
282 brnz,pn $3,$5
283 nop')
284
285
286/* usage: CHECK_FSREGS(reg1,reg2,tmp_reg1,tmp_reg2, MEM_DUMP_POINTER)
287 reg1 and reg2 : are single-precision floating point regs that are to be compared
288 tmp_reg1 & tmp_reg2: are 64-bit integer regs used as buffer regs
289 MEM_DUMP_POINTER : pointer to the memory dump area where the
290 machine state will be dumped if a miscompare occurs.
291 error_found: place to go when failed.
292*/
293
294define(CHECK_FSREGS, `st $1, [$5]
295 st $2, [$5+4]
296 lduw [$5], $3
297 lduw [$5+4], $4
298 sub $3, $4, $3 !since single precision registers, so, there is no need to
299 !clear upper 32-bits
300 brz,pt $3, 1f
301 nop
302 ta T_BAD_TRAP
303 1:')
304
305/* usage: CHECK_FDREGS(reg1,reg2,tmp_reg1,tmp_reg2,MEM_DUMP_POINTER)
306 reg1 and reg2 : are double-precision floating point regs that are to be compared
307 tmp_reg1 & tmp_reg2 : are 64-bit integer regs used as buffer regs
308 MEM_DUMP_POINTER : pointer to the memory dump area where the
309 machine state will be dumped if a miscompare occurs.
310 error_found: place to go when failed.
311*/
312
313define(CHECK_FDREGS, `std $1, [$5]
314 std $2, [$5+8]
315 ldx [$5], $3
316 ldx [$5+8], $4
317 sub $3, $4, $3
318 brz,pt $3, 1f
319 nop
320 ta T_BAD_TRAP
321 1:')
322
323/*usuage: CHECK_XREGS_EQUAL(reg1,reg2,tmp_reg1,tmp_reg2,no_error_found)
324 reg1 and reg2 : are 64 bits regs want to compare
325 tmp_reg1 & tmp_reg2: are buffer regs
326 no_error_found:place to go when passed.
327*/
328define(CHECK_XREGS_EQUAL,`mov $1,$3
329 mov $2,$4
330 sub $3,$4,$3
331 brnz $3,$5
332 nop
333 mov $1,$3
334 srlx $3,32,$3
335 srlx $4,32,$4
336 sub $3,$4,$3
337 brz $3,$5
338 nop')
339
340/* check 64 bit register.(compare 64 bit register with constants)
341 * usage:
342 *
343 * CHECK_64REG(reg, hi_value, low_value, tmp_reg1, tmp_reg2)
344 *
345 * reg - 64 bits reg want to compare
346 * hi_value, low_value - 2 32 bit constants
347 * tmp_reg1, tmp_reg2 - temp. registers
348 * ex: CHECK_64REG(%l0, 0x12345678, 0xfedcba98, %o1, %o2)
349 */
350define(CHECK_64REG, `set $2, $4 !hi_value in tmp_reg1
351 sllx $4, 32, $4 !move left 32-bits
352 set $3, $5 !low_value in tmp_reg2
353 srl $5, 0, $5 !clear upper-32 bits
354 or $4, $5, $4 !64_bit in tmp_reg1
355 sub $1, $4, $4
356 brz,pt $4, 1f
357 nop
358 ta T_BAD_TRAP
359 1:')
360
361
362/* RD/WR_CNTL_REG_FIELD macros 10/5/93 lyoungs
363 -These two macros work work for any register defined
364 in constants.h with *_RD(REG),*_WR(REG),*_MASK, and *_SHIFT.
365 -See /diag/src/sit/examples/exampleCntrlRegRdWr.s for how to use
366 these macros.
367 -Currently can't specify a VA for a read/wr to ASI that uses VA. */
368
369#define ECHO(A) A
370
371#define RD_CNTL_REG_FIELD(DATA_REG,REGNAME,FIELD_NAME,TMP_REG1,TMP_REG2) \
372 ECHO(REGNAME)_RD(DATA_REG); \
373 setx ECHO(FIELD_NAME)_MASK,TMP_REG2,TMP_REG1; \
374 and DATA_REG,TMP_REG1,TMP_REG1; \
375 srlx TMP_REG1,ECHO(FIELD_NAME)_SHIFT,DATA_REG
376
377#define WR_CNTL_REG_FIELD(DATA_REG,REGNAME,FIELD_NAME,TMP_REG1,TMP_REG2) \
378 setx ECHO(FIELD_NAME)_MASK,TMP_REG2,TMP_REG1; \
379 ECHO(REGNAME)_RD(TMP_REG2); \
380 andn TMP_REG2,TMP_REG1,TMP_REG2; \
381 sllx DATA_REG,ECHO(FIELD_NAME)_SHIFT,DATA_REG; \
382 and DATA_REG,TMP_REG1,TMP_REG1; \
383 or TMP_REG1,TMP_REG2,TMP_REG1; \
384 ECHO(REGNAME)_WR(TMP_REG1);\
385 srlx DATA_REG,ECHO(FIELD_NAME)_SHIFT,DATA_REG;
386
387/* Following macro is to align code on I$line boundary. 12/6/93 lyoungs */
388
389#define ALIGN_BRANCH_ICACHE_LINE \
390 ba 1f; \
391 nop; \
392 .align ICACHE_LINE_SIZE_IN_BYTES; \
393 1:
394
395
396/*purpose: do asi read/write
397 usuage: case1 take 2 parameters if the va[63:0] of the reg is fixed
398 1st parameter = reg put the rd/wr value
399 2nd = a temp buffer
400 e.g read tsb reg
401 rdtsb(%l0,tmp_reg1) ;%l0 will hold the rd value of tsb
402 ;tmp_reg1 is defined at the program
403 as #define tmp_reg1 %g5 by portability
404 guideline.
405
406 case2 take 3 parameters if the va[63:0] of the reg is various
407 1st =va that are interested could be in reg or imm_const 13
408 2nd =reg put the rd/wr value
409 3rd = a temp buffer
410 e.g read data_access reg
411 rdDdata_acc(0x48,%l3,tmp_reg1) ;0x48 is the va of data_acc reg
412 ;%l3 will hold the read value
413 rdDtsb(returnvalue,tmp_reg1)
414 wrDtsb(writevalue,tmp_reg1)
415 rdItsb(returnvalue,tmp_reg1)
416 wrItsb(writevalue,tmp_reg1)
417 rdlsu_control_reg(returnvalue,tmp_reg1)
418 wrlsu_control_reg(writevalue,tmp_reg1)
419 rdDtag_acc(returnvalue,tmp_reg1)
420 wrDtag_acc(writevalue,tmp_reg1)
421 rdItag_acc(returnvalue,tmp_reg1)
422 wrItag_acc(returnvalue,tmp_reg1)
423 wrpcontext(writevalue,tmp_reg1)
424 rdpcontext(returnvalue,tmp_reg1)
425 wrscontext(writevalue,tmp_reg1)
426 rdscontext(returnvalue,tmp_reg1)
427 rdDtsb_8k(returnvalue,tmp_reg1)
428 rdItsb_8k(returnvalue,tmp_reg1)
429 rdDtsb_64k(returnvalue,tmp_reg1)
430 rdItsb_64k(returnvalue,tmp_reg1)
431 wrDdata_acc(va,writevalue,tmp_reg1)
432 wrIdata_acc(va,writevalue,tmp_reg1)
433 rdDdata_acc(va,returnvalue,tmp_reg1)
434 rdIdata_acc(va,returnvalue,tmp_reg1)
435 rdDtag_read(va,returnvalue,tmp_reg1)
436 rdItag_read(va,returnvalue,tmp_reg1)
437 wrDdemap(demap_data,reg:demap_va,tmp_reg1,tmp_reg2)
438 wrIdemap(demap_data,reg:demap_va,tmp_reg1,tmp_reg2)
439*/
440
441/*2*/
442define(rdDtsb,`mov ASI_DMMU_TSB_BASE_VAL,$2
443 ldxa [$2]ASI_DMMU_TSB_BASE,$1')
444
445define(wrDtsb,`mov ASI_DMMU_TSB_BASE_VAL,$2
446 stxa $1,[$2]ASI_DMMU_TSB_BASE
447 membar 0x40')
448
449define(rdItsb,`mov ASI_IMMU_TSB_BASE_VAL,$2
450 ldxa [$2]ASI_IMMU_TSB_BASE,$1')
451
452define(wrItsb,`mov ASI_IMMU_TSB_BASE_VAL,$2
453 stxa $1,[$2]ASI_IMMU_TSB_BASE
454 membar 0x40')
455
456define(rdlsu_control_reg,`ldxa [%g0]ASI_DCU_CONTROL_REG,$1')
457
458define(wrlsu_control_reg,`stxa $1,[%g0]ASI_DCU_CONTROL_REG
459 membar 0x40')
460
461define(rdDtag_acc,`mov ASI_DMMU_TAG_ACCESS_VAL,$2
462 ldxa [$2]ASI_DMMU_TAG_ACCESS,$1')
463
464define(wrDtag_acc,`mov ASI_DMMU_TAG_ACCESS_VAL,$2
465 stxa $1,[$2]ASI_DMMU_TAG_ACCESS
466 membar 0x40')
467
468define(rdItag_acc,`mov ASI_IMMU_TAG_ACCESS_VAL,$2
469 ldxa [$2]ASI_IMMU_TAG_ACCESS,$1')
470
471define(wrItag_acc,`mov ASI_IMMU_TAG_ACCESS_VAL,$2
472 stxa $1,[$2]ASI_IMMU_TAG_ACCESS
473 membar 0x40')
474
475
476define(wrpcontext,`mov ASI_PRIMARY_CONTEXT_REG_VAL,$2
477 stxa $1,[$2]ASI_PRIMARY_CONTEXT_REG
478 membar 0x40')
479
480define(rdpcontext,`mov ASI_PRIMARY_CONTEXT_REG_VAL,$2
481 ldxa [$2]ASI_PRIMARY_CONTEXT_REG,$1')
482
483define(wrscontext,`mov ASI_SECONDARY_CONTEXT_REG_VAL,$2
484 stxa $1,[$2]ASI_SECONDARY_CONTEXT_REG
485 membar 0x40')
486
487
488define(rdscontext,`mov ASI_SECONDARY_CONTEXT_REG_VAL,$2
489 ldxa [$2]ASI_SECONDARY_CONTEXT_REG,$1')
490
491
492define(rdDtsb_8k,`ldxa [%g0]ASI_DMMU_TSB_8KB_PTR_REG,$1')
493
494define(rdDtsb_64k,`ldxa [%g0]ASI_DMMU_TSB_64KB_PTR_REG,$1')
495
496define(rdItsb_8k,`ldxa [%g0]ASI_IMMU_TSB_8KB_PTR_REG,$1')
497
498define(rdItsb_64k,`ldxa [%g0]ASI_IMMU_TSB_64KB_PTR_REG,$1')
499
500/*3*/
501
502define(wrDdata_acc,`mov $1,$3
503 stxa $2,[$3]ASI_DTLB_DATA_ACCESS_REG
504 membar 0x40')
505
506define(rdDdata_acc,`mov $1,$3
507 ldxa [$3]ASI_DTLB_DATA_ACCESS_REG,$2')
508
509define(wrIdata_acc,`mov $1,$3
510 stxa $2,[$3]ASI_ITLB_DATA_ACCESS_REG
511 membar 0x40')
512
513define(rdIdata_acc,`mov $1,$3
514 ldxa [$3]ASI_ITLB_DATA_ACCESS_REG,$2')
515
516define(rdDtag_read,`mov $1,$3
517 ldxa [$3]ASI_DTLB_TAG_READ_REG,$2 ')
518
519define(rdItag_read,`mov $1,$3
520 ldxa [$3]ASI_ITLB_TAG_READ_REG,$2 ')
521
522define(wrDdemap,`stxa %g0,[$1]ASI_DMMU_DEMAP
523 membar 0x40')
524
525define(wrIdemap,`stxa %g0,[$1]ASI_IMMU_DEMAP
526 flush %g0')
527
528#ifndef USER_TEXT_START
529#define USER_TEXT_START user_text_start
530#endif
531
532#ifndef ENTRY_POINT
533#define ENTRY_POINT USER_TEXT_START
534#endif
535
536define(SYNC, `.word 0x81b01000')
537define(sync, `.word 0x81b01000')
538
539/*
540 - clear asynchronous fault status register
541 - clr_asy_flt_stat_reg(temp_reg1, temp_reg2, temp_reg3)
542*/
543
544define(CLR_ASY_FLT_STAT_REG,`setx 0x0, $1, $2
545 setx 0x1ffffffff, $1, $3
546 stxa $3,[$2]ASI_ASYNC_FAULT_STATUS
547 membar MBAR_SYNC')
548
549/*
550 - enable d_cache and e_cache by setting ic and dc bits
551 - set_lsu_cntl_reg_csh_en(ic_dc_bits, reg_rd, temp1_reg, temp2_reg)
552*/
553
554define(SET_LSU_CNTL_REG_CSH_EN,`setx 0x0, $3, $4
555 ldxa [$4]ASI_DCU_CONTROL_REG, $2
556 or $2, $1, $2
557 stxa $2, [$4]ASI_DCU_CONTROL_REG
558 membar MBAR_SYNC')
559
560/* following endif needs to be at very bottom -- 6/2/93 lyoungs */
561#endif
Full OpenSPARC design & verification tarball including full HDL.