Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / mbist_defines.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: mbist_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
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31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
39! MBIST_REG 0x8500000000
40!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
41
42#ifndef MBIST_MODE
43#define MBIST_MODE 0x8500000000
44#endif
45
46#ifndef RESET_GEN
47#define RESET_GEN 0x8900000808
48#endif
49
50#ifndef RESET_STAT
51#define RESET_STAT 0x8900000810
52#endif
53
54#ifndef MBIST_BYPASS
55#define MBIST_BYPASS 0x8500000008
56#endif
57
58#ifndef MBIST_START_WMR
59#define MBIST_START_WMR 0x8500000038
60#endif
61
62#ifdef BIST_PAR
63#define MBIST_MODE_REG 0x1
64#endif
65
66#ifdef BIST_SER
67#define MBIST_MODE_REG 0x0
68#endif
69
70#ifndef MBIST_MODE_REG
71#define MBIST_MODE_REG 0x1
72#endif
73
74#ifndef MBIST_BYPASS_REG
75#define MBIST_BYPASS_REG 0xFFFFFFFFFEFF
76#endif
77
78#ifdef CHANGE
79#define WARM_RESET_INIT 1
80#define CCU_REG_PROG 1
81#endif
82
83!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
84! MBIST_MODE 0x8500000000
85! RSVD0 63:4
86! LOOP_MODE 3
87! DIAGNOSTIC 2
88! BISI 1
89! PARALLEL 0
90!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
91
92!#ifndef CREGS_MBIST_MODE_REG_R64
93!#define CREGS_MBIST_MODE_REG_R64 (MBIST_MODE_REG)
94!#endif
95
96!define(cregs_mbist_mode_reg_r64, `0x'dnl
97!mpeval(CREGS_MBIST_MODE_REG_R64, 16, 8))