projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: mcu_fbdimm_training.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | mcu_fbdimm_training: | |
| 39 | mcuctl_init: | |
| 40 | ||
| 41 | setx 0x8400000000, %l7, %l6 | |
| 42 | sethi %hi(0x00001000), %g1 | |
| 43 | sethi %hi(0x00002000), %g2 | |
| 44 | sethi %hi(0x00003000), %g3 | |
| 45 | ||
| 46 | /*** | |
| 47 | !DRAM_DIMM_INIT_REG | |
| 48 | add %l6, 0x1a0, %l0 | |
| 49 | mov 0x0, %l3 | |
| 50 | stx %l3, [%l0+%g0] | |
| 51 | stx %l3, [%l0+%g1] | |
| 52 | stx %l3, [%l0+%g2] | |
| 53 | stx %l3, [%l0+%g3] | |
| 54 | ||
| 55 | /***added from SAT (NEW) ***/ | |
| 56 | add %l6, 0x800, %l5 | |
| 57 | stx %g0, [%l5+%g0] | |
| 58 | stx %g0, [%l5+%g1] | |
| 59 | stx %g0, [%l5+%g2] | |
| 60 | stx %g0, [%l5+%g3] | |
| 61 | ||
| 62 | add %l6, 0x808, %l5 | |
| 63 | mov 0x9, %l3 | |
| 64 | stx %l3, [%l5+%g0] | |
| 65 | stx %l3, [%l5+%g1] | |
| 66 | stx %l3, [%l5+%g2] | |
| 67 | stx %l3, [%l5+%g3] | |
| 68 | ||
| 69 | /***End from SAT (NEW) ***/ | |
| 70 | ||
| 71 | ! CHANNEL_RESET_REG | |
| 72 | add %l6, 0x810, %l5 | |
| 73 | mov 0x1, %l3 | |
| 74 | stx %l3, [%l5+%g0] | |
| 75 | stx %l3, [%l5+%g1] | |
| 76 | stx %l3, [%l5+%g2] | |
| 77 | stx %l3, [%l5+%g3] | |
| 78 | ***/ | |
| 79 | ||
| 80 | load_fbd_chnl_state_reg: | |
| 81 | add %l6, 0x800, %l4 | |
| 82 | mov 0x6,%l1 | |
| 83 | ||
| 84 | Poll_for1st_link_training: | |
| 85 | mcu0: | |
| 86 | ldx [%l4+%g0], %g4 | |
| 87 | andcc %g4,0xf,%l3 | |
| 88 | cmp %l1,%l3 | |
| 89 | bne mcu0 | |
| 90 | mcu1: | |
| 91 | ldx [%l4+%g1], %g4 | |
| 92 | andcc %g4,0xf,%l3 | |
| 93 | cmp %l1,%l3 | |
| 94 | bne mcu1 | |
| 95 | mcu2: | |
| 96 | ldx [%l4+%g2], %g4 | |
| 97 | andcc %g4,0xf,%l3 | |
| 98 | cmp %l1,%l3 | |
| 99 | bne mcu2 | |
| 100 | mcu3: | |
| 101 | ldx [%l4+%g3], %g4 | |
| 102 | andcc %g4,0xf,%l3 | |
| 103 | cmp %l1,%l3 | |
| 104 | bne mcu3 | |
| 105 | ||
| 106 | /***!#ifdef FBDIMMS_1***/ | |
| 107 | one_fbdimm: | |
| 108 | mov 0x1,%g4 | |
| 109 | /***!#endif ***/ | |
| 110 | #ifdef FBDIMMS_2 | |
| 111 | mov 0x2,%g4 | |
| 112 | mov 0x2,%i5 | |
| 113 | #endif | |
| 114 | #ifdef FBDIMMS_4 | |
| 115 | mov 0x4,%g4 | |
| 116 | mov 0x4,%i5 | |
| 117 | #endif | |
| 118 | #ifdef FBDIMMS_6 | |
| 119 | mov 0x6,%g4 | |
| 120 | mov 0x6,%i5 | |
| 121 | #endif | |
| 122 | #ifdef FBDIMMS_8 | |
| 123 | mov 0x8,%g4 | |
| 124 | mov 0x8,%i5 | |
| 125 | #endif | |
| 126 | ||
| 127 | set 0x8000,%i5 | |
| 128 | amb_drc_reg_init: | |
| 129 | step_1st: | |
| 130 | set 0x900,%g4 | |
| 131 | add %l6, %g4, %l0 | |
| 132 | set 0x37c, %l3 | |
| 133 | or %l3, %g4, %l3 | |
| 134 | stx %l3, [%l0+%g0] | |
| 135 | stx %l3, [%l0+%g1] | |
| 136 | stx %l3, [%l0+%g2] | |
| 137 | stx %l3, [%l0+%g3] | |
| 138 | ||
| 139 | amb_drc_2nd_step: | |
| 140 | add %l6, 0x908, %l1 | |
| 141 | set 0x633, %l4 | |
| 142 | stx %l4, [%l1+%g0] | |
| 143 | stx %l4, [%l1+%g1] | |
| 144 | stx %l4, [%l1+%g2] | |
| 145 | stx %l4, [%l1+%g3] | |
| 146 | ||
| 147 | amb_drc_3rd_step: | |
| 148 | or %l3, %i5, %l3 | |
| 149 | stx %l3, [%l0+%g0] | |
| 150 | stx %l3, [%l0+%g1] | |
| 151 | stx %l3, [%l0+%g2] | |
| 152 | stx %l3, [%l0+%g3] | |
| 153 | ||
| 154 | amb_drc_4th_step: | |
| 155 | !set 0x733, %l3 | |
| 156 | stx %l4, [%l1+%g0] | |
| 157 | stx %l4, [%l1+%g1] | |
| 158 | stx %l4, [%l1+%g2] | |
| 159 | stx %l4, [%l1+%g3] | |
| 160 | ||
| 161 | ||
| 162 | amb_cmd2data_reg_init: | |
| 163 | step_5th: | |
| 164 | set 0x1e8, %l3 | |
| 165 | or %l3, %g4, %l3 | |
| 166 | stx %l3, [%l0+%g0] | |
| 167 | stx %l3, [%l0+%g1] | |
| 168 | stx %l3, [%l0+%g2] | |
| 169 | stx %l3, [%l0+%g3] | |
| 170 | ||
| 171 | amb_cmd2data_6th_step: | |
| 172 | set 0x20, %l4 | |
| 173 | stx %l4, [%l1+%g0] | |
| 174 | stx %l4, [%l1+%g1] | |
| 175 | stx %l4, [%l1+%g2] | |
| 176 | stx %l4, [%l1+%g3] | |
| 177 | ||
| 178 | ||
| 179 | amb_cmd2data_7th_step: | |
| 180 | or %l3, %i5, %l3 | |
| 181 | stx %l3, [%l0+%g0] | |
| 182 | stx %l3, [%l0+%g1] | |
| 183 | stx %l3, [%l0+%g2] | |
| 184 | stx %l3, [%l0+%g3] | |
| 185 | ||
| 186 | amb_cmd2data_8th_step: | |
| 187 | ! set 0x20, %l4 | |
| 188 | stx %l4, [%l1+%g0] | |
| 189 | stx %l4, [%l1+%g1] | |
| 190 | stx %l4, [%l1+%g2] | |
| 191 | stx %l4, [%l1+%g3] | |
| 192 | ||
| 193 | ||
| 194 | amb_dsreftc_reg_init: | |
| 195 | step_9th: | |
| 196 | set 0x374, %l3 | |
| 197 | or %l3, %g4, %l3 | |
| 198 | stx %l3, [%l0+%g0] | |
| 199 | stx %l3, [%l0+%g1] | |
| 200 | stx %l3, [%l0+%g2] | |
| 201 | stx %l3, [%l0+%g3] | |
| 202 | amb_dsreftc_10th_step: | |
| 203 | set 0x56f7,%l4 | |
| 204 | #ifdef STACK_DIMM | |
| 205 | set 0x20000000,%g4 | |
| 206 | or %l4, %g4, %l4 | |
| 207 | #endif | |
| 208 | stx %l4, [%l1+%g0] | |
| 209 | stx %l4, [%l1+%g1] | |
| 210 | stx %l4, [%l1+%g2] | |
| 211 | stx %l4, [%l1+%g3] | |
| 212 | ||
| 213 | amb_dsreftc_11th_step: | |
| 214 | or %l3, %i5, %l3 | |
| 215 | stx %l3, [%l0+%g0] | |
| 216 | stx %l3, [%l0+%g1] | |
| 217 | stx %l3, [%l0+%g2] | |
| 218 | stx %l3, [%l0+%g3] | |
| 219 | amb_dsreftc_12th_step: | |
| 220 | stx %l4, [%l1+%g0] | |
| 221 | stx %l4, [%l1+%g1] | |
| 222 | stx %l4, [%l1+%g2] | |
| 223 | stx %l4, [%l1+%g3] | |
| 224 | ||
| 225 | set_chnl_reg_2nd_link_train: | |
| 226 | ! CHANNEL_RESET_REG | |
| 227 | !add %l6, 0x810, %l5 | |
| 228 | mov 0x1, %l3 | |
| 229 | stx %l3, [%l5+%g0] | |
| 230 | stx %l3, [%l5+%g1] | |
| 231 | stx %l3, [%l5+%g2] | |
| 232 | stx %l3, [%l5+%g3] | |
| 233 | ||
| 234 | set_808: | |
| 235 | add %l6, 0x808, %l4 | |
| 236 | !mov 0x1, %l3 | |
| 237 | stx %l3, [%l4+%g0] | |
| 238 | stx %l3, [%l4+%g1] | |
| 239 | stx %l3, [%l4+%g2] | |
| 240 | stx %l3, [%l4+%g3] | |
| 241 | ||
| 242 | mov 0x6,%l2 | |
| 243 | load_fbd_chnl_state_reg_2nd_link_train: | |
| 244 | add %l6, 0x800, %l4 | |
| 245 | ||
| 246 | ||
| 247 | ||
| 248 | Poll_for2nd_link_training_complete: | |
| 249 | mcu0_2: | |
| 250 | ldx [%l4+%g0], %g4 | |
| 251 | andcc %g4,0xf,%i5 | |
| 252 | cmp %l2,%i5 | |
| 253 | bne mcu0_2 | |
| 254 | nop | |
| 255 | mcu1_2: | |
| 256 | ldx [%l4+%g1], %g4 | |
| 257 | andcc %g4,0xf,%i5 | |
| 258 | cmp %l2,%i5 | |
| 259 | bne mcu1_2 | |
| 260 | nop | |
| 261 | mcu2_2: | |
| 262 | ldx [%l4+%g2], %g4 | |
| 263 | andcc %g4,0xf,%i5 | |
| 264 | cmp %l2,%i5 | |
| 265 | bne mcu2_2 | |
| 266 | nop | |
| 267 | mcu3_2: | |
| 268 | ldx [%l4+%g3], %g5 | |
| 269 | andcc %g5,0xf,%i5 | |
| 270 | cmp %l2,%i5 | |
| 271 | bne mcu3_2 | |
| 272 | nop | |
| 273 | Polling_complete: | |
| 274 | nop | |
| 275 | ||
| 276 | init_1a0_done_0: | |
| 277 | !DRAM_DIMM_INIT_REG | |
| 278 | add %l6, 0x1a0, %l2 | |
| 279 | !mov 0x1, %l3 | |
| 280 | stx %l3, [%l2+%g0] | |
| 281 | stx %l3, [%l2+%g1] | |
| 282 | stx %l3, [%l2+%g2] | |
| 283 | stx %l3, [%l0+%g3] | |
| 284 | ||
| 285 | /***!#ifdef FBDIMMS_1***/ | |
| 286 | one_fbdimm_1: | |
| 287 | mov 0x1,%g4 | |
| 288 | mov 0x1,%i5 | |
| 289 | /***!#endif ***/ | |
| 290 | #ifdef FBDIMMS_2 | |
| 291 | mov 0x2,%g4 | |
| 292 | mov 0x2,%i5 | |
| 293 | #endif | |
| 294 | #ifdef FBDIMMS_4 | |
| 295 | mov 0x4,%g4 | |
| 296 | mov 0x4,%i5 | |
| 297 | #endif | |
| 298 | #ifdef FBDIMMS_6 | |
| 299 | mov 0x6,%g4 | |
| 300 | mov 0x6,%i5 | |
| 301 | #endif | |
| 302 | #ifdef FBDIMMS_8 | |
| 303 | mov 0x8,%g4 | |
| 304 | mov 0x8,%i5 | |
| 305 | #endif | |
| 306 | ||
| 307 | ||
| 308 | ||
| 309 | done_mcu_fbdimm_2nd_link_training: | |
| 310 | sllx %g4,11,%l2 | |
| 311 | set 0x440,%g5 | |
| 312 | or %g5,%l2,%l3 ! l3 has DCALCSR_REG_ADDR_data 64'h440 | |
| 313 | set 0x444,%g6 | |
| 314 | or %g6,%l2,%l6 ! l6 has DCALADDR_REG_ADDR_data 64'h444 | |
| 315 | set 0x8000,%l2 ! l1 has channel b | |
| 316 | or %l2,%l3,%g4 ! g4 has DCALCSR_REG_ADDR_data channel b 64'h8440 | |
| 317 | or %l2,%l6,%g5 ! g5 has DCALADDR_REG_ADDR_data channel b 64'8h444 | |
| 318 | ||
| 319 | ||
| 320 | send_nop_fromMCU: | |
| 321 | ! add %l6, 0x900, %l0 | |
| 322 | stx %l3, [%l0+%g0] | |
| 323 | stx %l3, [%l0+%g1] | |
| 324 | stx %l3, [%l0+%g2] | |
| 325 | stx %l3, [%l0+%g3] | |
| 326 | send_nop_2nd_step: | |
| 327 | ! add %l6, 0x908, %l1 | |
| 328 | set 0x80600000,%g6 | |
| 329 | stx %g6, [%l1+%g0] | |
| 330 | stx %g6, [%l1+%g1] | |
| 331 | stx %g6, [%l1+%g2] | |
| 332 | stx %g6, [%l1+%g3] | |
| 333 | send_nop_3rd_step: | |
| 334 | ! add %l6, 0x900, %l0 | |
| 335 | stx %g4, [%l0+%g0] | |
| 336 | stx %g4, [%l0+%g1] | |
| 337 | stx %g4, [%l0+%g2] | |
| 338 | stx %g4, [%l0+%g3] | |
| 339 | send_nop_4th_step: | |
| 340 | ! add %l6, 0x908, %l1 | |
| 341 | ! setx 0x80600000,%i2,%g6 | |
| 342 | stx %g6, [%l1+%g0] | |
| 343 | stx %g6, [%l1+%g1] | |
| 344 | stx %g6, [%l1+%g2] | |
| 345 | stx %g6, [%l1+%g3] | |
| 346 | send_nop_5th_step: | |
| 347 | ! add %l6, 0x900, %l0 | |
| 348 | sllx %i5,11,%g7 | |
| 349 | set 0x37c, %i4 | |
| 350 | or %i4,%g7,%g6 ! l3 has DCALCSR_REG_ADDR_data 64'h440 | |
| 351 | stx %g6, [%l0+%g0] | |
| 352 | stx %g6, [%l0+%g1] | |
| 353 | stx %g6, [%l0+%g2] | |
| 354 | stx %g6, [%l0+%g3] | |
| 355 | send_nop_6th_step: | |
| 356 | ! add %l6, 0x908, %l1 | |
| 357 | set 0x633,%g7 | |
| 358 | stx %g7, [%l1+%g0] | |
| 359 | stx %g7, [%l1+%g1] | |
| 360 | stx %g7, [%l1+%g2] | |
| 361 | stx %g7, [%l1+%g3] | |
| 362 | send_nop_7th_step: | |
| 363 | set 0x8000, %i4 | |
| 364 | or %i4,%g6,%g6 ! l3 has DCALCSR_REG_ADDR_data 64'h440 | |
| 365 | stx %g6, [%l0+%g0] | |
| 366 | stx %g6, [%l0+%g1] | |
| 367 | stx %g6, [%l0+%g2] | |
| 368 | stx %g6, [%l0+%g3] | |
| 369 | send_nop_8th_step: | |
| 370 | ! add %l6, 0x908, %l1 | |
| 371 | stx %g7, [%l1+%g0] | |
| 372 | stx %g7, [%l1+%g1] | |
| 373 | stx %g7, [%l1+%g2] | |
| 374 | stx %g7, [%l1+%g3] | |
| 375 | ||
| 376 | ||
| 377 | ||
| 378 | send_precharge: | |
| 379 | ! add %l6, 0x900, %l0 | |
| 380 | stx %l6, [%l0+%g0] | |
| 381 | stx %l6, [%l0+%g1] | |
| 382 | stx %l6, [%l0+%g2] | |
| 383 | stx %l6, [%l0+%g3] | |
| 384 | send_precharge_2nd_step: | |
| 385 | ! add %l6, 0x908, %l1 | |
| 386 | set 0x1c000000,%g6 | |
| 387 | stx %g6, [%l1+%g0] | |
| 388 | stx %g6, [%l1+%g1] | |
| 389 | stx %g6, [%l1+%g2] | |
| 390 | stx %g6, [%l1+%g3] | |
| 391 | send_precharge_3rd_step: | |
| 392 | ! add %l6, 0x900, %l0 | |
| 393 | stx %l3, [%l0+%g0] | |
| 394 | stx %l3, [%l0+%g1] | |
| 395 | stx %l3, [%l0+%g2] | |
| 396 | stx %l3, [%l0+%g3] | |
| 397 | send_precharge_4th_step: | |
| 398 | ! add %l6, 0x908, %l1 | |
| 399 | set 0x80600002,%g6 | |
| 400 | stx %g6, [%l1+%g0] | |
| 401 | stx %g6, [%l1+%g1] | |
| 402 | stx %g6, [%l1+%g2] | |
| 403 | stx %g6, [%l1+%g3] | |
| 404 | ||
| 405 | send_precharge_5th_step: | |
| 406 | ! add %l6, 0x900, %l0 | |
| 407 | stx %g5, [%l0+%g0] | |
| 408 | stx %g5, [%l0+%g1] | |
| 409 | stx %g5, [%l0+%g2] | |
| 410 | stx %g5, [%l0+%g3] | |
| 411 | send_precharge_6th_step: | |
| 412 | ! add %l6, 0x908, %l1 | |
| 413 | set 0x1c000000, %g6 | |
| 414 | stx %g6, [%l1+%g0] | |
| 415 | stx %g6, [%l1+%g1] | |
| 416 | stx %g6, [%l1+%g2] | |
| 417 | stx %g6, [%l1+%g3] | |
| 418 | send_precharge_7th_step: | |
| 419 | ! add %l6, 0x900, %l0 | |
| 420 | stx %g4, [%l0+%g0] | |
| 421 | stx %g4, [%l0+%g1] | |
| 422 | stx %g4, [%l0+%g2] | |
| 423 | stx %g4, [%l0+%g3] | |
| 424 | send_precharge_8th_step: | |
| 425 | ! add %l6, 0x908, %l1 | |
| 426 | set 0x80600002, %g6 | |
| 427 | stx %g6, [%l1+%g0] | |
| 428 | stx %g6, [%l1+%g1] | |
| 429 | stx %g6, [%l1+%g2] | |
| 430 | stx %g6, [%l1+%g3] | |
| 431 | ||
| 432 | send_emrs: | |
| 433 | ! add %l6, 0x900, %l0 | |
| 434 | stx %l6, [%l0+%g0] | |
| 435 | stx %l6, [%l0+%g1] | |
| 436 | stx %l6, [%l0+%g2] | |
| 437 | stx %l6, [%l0+%g3] | |
| 438 | send_emrs_2nd_step: | |
| 439 | ! add %l6, 0x908, %l1 | |
| 440 | mov 0x2, %g7 | |
| 441 | stx %g7, [%l1+%g0] | |
| 442 | stx %g7, [%l1+%g1] | |
| 443 | stx %g7, [%l1+%g2] | |
| 444 | stx %g7, [%l1+%g3] | |
| 445 | send_emrs_3rd_step: | |
| 446 | ! add %l6, 0x900, %l0 | |
| 447 | stx %l3, [%l0+%g0] | |
| 448 | stx %l3, [%l0+%g1] | |
| 449 | stx %l3, [%l0+%g2] | |
| 450 | stx %l3, [%l0+%g3] | |
| 451 | send_emrs_4th_step: | |
| 452 | ! add %l6, 0x908, %l1 | |
| 453 | set 0x80600003,%g6 | |
| 454 | stx %g6, [%l1+%g0] | |
| 455 | stx %g6, [%l1+%g1] | |
| 456 | stx %g6, [%l1+%g2] | |
| 457 | stx %g6, [%l1+%g3] | |
| 458 | ||
| 459 | send_emrs_5th_step: | |
| 460 | ! add %l6, 0x900, %l0 | |
| 461 | stx %g5, [%l0+%g0] | |
| 462 | stx %g5, [%l0+%g1] | |
| 463 | stx %g5, [%l0+%g2] | |
| 464 | stx %g5, [%l0+%g3] | |
| 465 | send_emrs_6th_step: | |
| 466 | ! add %l6, 0x908, %l1 | |
| 467 | stx %g7, [%l1+%g0] | |
| 468 | stx %g7, [%l1+%g1] | |
| 469 | stx %g7, [%l1+%g2] | |
| 470 | stx %g7, [%l1+%g3] | |
| 471 | ||
| 472 | send_emrs_7th_step: | |
| 473 | ! add %l6, 0x900, %l0 | |
| 474 | stx %g4, [%l0+%g0] | |
| 475 | stx %g4, [%l0+%g1] | |
| 476 | stx %g4, [%l0+%g2] | |
| 477 | stx %g4, [%l0+%g3] | |
| 478 | send_emrs_8th_step: | |
| 479 | ! add %l6, 0x908, %l1 | |
| 480 | stx %g6, [%l1+%g0] | |
| 481 | stx %g6, [%l1+%g1] | |
| 482 | stx %g6, [%l1+%g2] | |
| 483 | stx %g6, [%l1+%g3] | |
| 484 | ||
| 485 | send_emrs_3: | |
| 486 | ! add %l6, 0x900, %l0 | |
| 487 | stx %l6, [%l0+%g0] | |
| 488 | stx %l6, [%l0+%g1] | |
| 489 | stx %l6, [%l0+%g2] | |
| 490 | stx %l6, [%l0+%g3] | |
| 491 | send_emrs_3_2nd_step: | |
| 492 | ! add %l6, 0x908, %l1 | |
| 493 | mov 0x3, %g7 | |
| 494 | stx %g7, [%l1+%g0] | |
| 495 | stx %g7, [%l1+%g1] | |
| 496 | stx %g7, [%l1+%g2] | |
| 497 | stx %g7, [%l1+%g3] | |
| 498 | send_emrs_3_3rd_step: | |
| 499 | ! add %l6, 0x900, %l0 | |
| 500 | stx %l3, [%l0+%g0] | |
| 501 | stx %l3, [%l0+%g1] | |
| 502 | stx %l3, [%l0+%g2] | |
| 503 | stx %l3, [%l0+%g3] | |
| 504 | send_emrs_3_4th_step: | |
| 505 | ! add %l6, 0x908, %l1 | |
| 506 | ! set 0x80600003,%g6 | |
| 507 | stx %g6, [%l1+%g0] | |
| 508 | stx %g6, [%l1+%g1] | |
| 509 | stx %g6, [%l1+%g2] | |
| 510 | stx %g6, [%l1+%g3] | |
| 511 | ||
| 512 | send_emrs_3_5th_step: | |
| 513 | ! add %l6, 0x900, %l0 | |
| 514 | stx %g5, [%l0+%g0] | |
| 515 | stx %g5, [%l0+%g1] | |
| 516 | stx %g5, [%l0+%g2] | |
| 517 | stx %g5, [%l0+%g3] | |
| 518 | send_emrs_3_6th_step: | |
| 519 | ! add %l6, 0x908, %l1 | |
| 520 | stx %g7, [%l1+%g0] | |
| 521 | stx %g7, [%l1+%g1] | |
| 522 | stx %g7, [%l1+%g2] | |
| 523 | stx %g7, [%l1+%g3] | |
| 524 | ||
| 525 | send_emrs_3_7th_step: | |
| 526 | ! add %l6, 0x900, %l0 | |
| 527 | stx %g4, [%l0+%g0] | |
| 528 | stx %g4, [%l0+%g1] | |
| 529 | stx %g4, [%l0+%g2] | |
| 530 | stx %g4, [%l0+%g3] | |
| 531 | send_emrs_3_8th_step: | |
| 532 | ! add %l6, 0x908, %l1 | |
| 533 | stx %g6, [%l1+%g0] | |
| 534 | stx %g6, [%l1+%g1] | |
| 535 | stx %g6, [%l1+%g2] | |
| 536 | stx %g6, [%l1+%g3] | |
| 537 | ||
| 538 | send_emrs_1: | |
| 539 | ! add %l6, 0x900, %l0 | |
| 540 | stx %l6, [%l0+%g0] | |
| 541 | stx %l6, [%l0+%g1] | |
| 542 | stx %l6, [%l0+%g2] | |
| 543 | stx %l6, [%l0+%g3] | |
| 544 | send_emrs_1_2nd_step: | |
| 545 | ! add %l6, 0x908, %l1 | |
| 546 | set 0x000001, %g7 | |
| 547 | stx %g7, [%l1+%g0] | |
| 548 | stx %g7, [%l1+%g1] | |
| 549 | stx %g7, [%l1+%g2] | |
| 550 | stx %g7, [%l1+%g3] | |
| 551 | send_emrs_1_3rd_step: | |
| 552 | ! add %l6, 0x900, %l0 | |
| 553 | stx %l3, [%l0+%g0] | |
| 554 | stx %l3, [%l0+%g1] | |
| 555 | stx %l3, [%l0+%g2] | |
| 556 | stx %l3, [%l0+%g3] | |
| 557 | send_emrs_1_4th_step: | |
| 558 | ! add %l6, 0x908, %l1 | |
| 559 | ! set 0x80600003,%g6 | |
| 560 | stx %g6, [%l1+%g0] | |
| 561 | stx %g6, [%l1+%g1] | |
| 562 | stx %g6, [%l1+%g2] | |
| 563 | stx %g6, [%l1+%g3] | |
| 564 | ||
| 565 | send_emrs_1_5th_step: | |
| 566 | ! add %l6, 0x900, %l0 | |
| 567 | stx %g5, [%l0+%g0] | |
| 568 | stx %g5, [%l0+%g1] | |
| 569 | stx %g5, [%l0+%g2] | |
| 570 | stx %g5, [%l0+%g3] | |
| 571 | send_emrs_1_6th_step: | |
| 572 | ! add %l6, 0x908, %l1 | |
| 573 | stx %g7, [%l1+%g0] | |
| 574 | stx %g7, [%l1+%g1] | |
| 575 | stx %g7, [%l1+%g2] | |
| 576 | stx %g7, [%l1+%g3] | |
| 577 | ||
| 578 | send_emrs_1_7th_step: | |
| 579 | ! add %l6, 0x900, %l0 | |
| 580 | stx %g4, [%l0+%g0] | |
| 581 | stx %g4, [%l0+%g1] | |
| 582 | stx %g4, [%l0+%g2] | |
| 583 | stx %g4, [%l0+%g3] | |
| 584 | send_emrs_1_8th_step: | |
| 585 | ! add %l6, 0x908, %l1 | |
| 586 | stx %g6, [%l1+%g0] | |
| 587 | stx %g6, [%l1+%g1] | |
| 588 | stx %g6, [%l1+%g2] | |
| 589 | stx %g6, [%l1+%g3] | |
| 590 | ||
| 591 | ||
| 592 | #ifdef SNG_CHANNEL | |
| 593 | set 0x30000,%g6 | |
| 594 | #endif | |
| 595 | /***#ifdef DUAL_CHANNEL ***/ | |
| 596 | dual_channel_1: | |
| 597 | set 0x20000,%g6 | |
| 598 | /***#endif ***/ | |
| 599 | ||
| 600 | ||
| 601 | send_mrs: | |
| 602 | ! add %l6, 0x900, %l0 | |
| 603 | stx %l6, [%l0+%g0] | |
| 604 | stx %l6, [%l0+%g1] | |
| 605 | stx %l6, [%l0+%g2] | |
| 606 | stx %l6, [%l0+%g3] | |
| 607 | send_mrs_2nd_step: | |
| 608 | ! add %l6, 0x908, %l1 | |
| 609 | set 0x5300000, %g7 | |
| 610 | or %g7, %g6, %g7 | |
| 611 | stx %g7, [%l1+%g0] | |
| 612 | stx %g7, [%l1+%g1] | |
| 613 | stx %g7, [%l1+%g2] | |
| 614 | stx %g7, [%l1+%g3] | |
| 615 | send_mrs_3rd_step: | |
| 616 | ! add %l6, 0x900, %l0 | |
| 617 | stx %l3, [%l0+%g0] | |
| 618 | stx %l3, [%l0+%g1] | |
| 619 | stx %l3, [%l0+%g2] | |
| 620 | stx %l3, [%l0+%g3] | |
| 621 | send_mrs_4th_step: | |
| 622 | ! add %l6, 0x908, %l1 | |
| 623 | set 0x80600003,%g6 | |
| 624 | stx %g6, [%l1+%g0] | |
| 625 | stx %g6, [%l1+%g1] | |
| 626 | stx %g6, [%l1+%g2] | |
| 627 | stx %g6, [%l1+%g3] | |
| 628 | ||
| 629 | send_mrs_5th_step: | |
| 630 | ! add %l6, 0x900, %l0 | |
| 631 | stx %g5, [%l0+%g0] | |
| 632 | stx %g5, [%l0+%g1] | |
| 633 | stx %g5, [%l0+%g2] | |
| 634 | stx %g5, [%l0+%g3] | |
| 635 | send_mrs_6th_step: | |
| 636 | ! add %l6, 0x908, %l1 | |
| 637 | stx %g7, [%l1+%g0] | |
| 638 | stx %g7, [%l1+%g1] | |
| 639 | stx %g7, [%l1+%g2] | |
| 640 | stx %g7, [%l1+%g3] | |
| 641 | ||
| 642 | send_mrs_7th_step: | |
| 643 | ! add %l6, 0x900, %l0 | |
| 644 | stx %g4, [%l0+%g0] | |
| 645 | stx %g4, [%l0+%g1] | |
| 646 | stx %g4, [%l0+%g2] | |
| 647 | stx %g4, [%l0+%g3] | |
| 648 | send_mrs_8th_step: | |
| 649 | ! add %l6, 0x908, %l1 | |
| 650 | stx %g6, [%l1+%g0] | |
| 651 | stx %g6, [%l1+%g1] | |
| 652 | stx %g6, [%l1+%g2] | |
| 653 | stx %g6, [%l1+%g3] | |
| 654 | ||
| 655 | ||
| 656 | send_all_precharge: | |
| 657 | ! add %l6, 0x900, %l0 | |
| 658 | stx %l6, [%l0+%g0] | |
| 659 | stx %l6, [%l0+%g1] | |
| 660 | stx %l6, [%l0+%g2] | |
| 661 | stx %l6, [%l0+%g3] | |
| 662 | send_all_precharge_2nd_step: | |
| 663 | ! add %l6, 0x908, %l1 | |
| 664 | set 0x1c000000,%g7 | |
| 665 | stx %g7, [%l1+%g0] | |
| 666 | stx %g7, [%l1+%g1] | |
| 667 | stx %g7, [%l1+%g2] | |
| 668 | stx %g7, [%l1+%g3] | |
| 669 | send_all_precharge_3rd_step: | |
| 670 | ! add %l6, 0x900, %l0 | |
| 671 | stx %l3, [%l0+%g0] | |
| 672 | stx %l3, [%l0+%g1] | |
| 673 | stx %l3, [%l0+%g2] | |
| 674 | stx %l3, [%l0+%g3] | |
| 675 | send_all_precharge_4th_step: | |
| 676 | ! add %l6, 0x908, %l1 | |
| 677 | set 0x80600002,%g6 | |
| 678 | stx %g6, [%l1+%g0] | |
| 679 | stx %g6, [%l1+%g1] | |
| 680 | stx %g6, [%l1+%g2] | |
| 681 | stx %g6, [%l1+%g3] | |
| 682 | ||
| 683 | send_all_precharge_5th_step: | |
| 684 | ! add %l6, 0x900, %l0 | |
| 685 | stx %g5, [%l0+%g0] | |
| 686 | stx %g5, [%l0+%g1] | |
| 687 | stx %g5, [%l0+%g2] | |
| 688 | stx %g5, [%l0+%g3] | |
| 689 | send_all_precharge_6th_step: | |
| 690 | ! add %l6, 0x908, %l1 | |
| 691 | ! set 0x1c000000, %g7 | |
| 692 | stx %g7, [%l1+%g0] | |
| 693 | stx %g7, [%l1+%g1] | |
| 694 | stx %g7, [%l1+%g2] | |
| 695 | stx %g7, [%l1+%g3] | |
| 696 | send_all_precharge_7th_step: | |
| 697 | ! add %l6, 0x900, %l0 | |
| 698 | stx %g4, [%l0+%g0] | |
| 699 | stx %g4, [%l0+%g1] | |
| 700 | stx %g4, [%l0+%g2] | |
| 701 | stx %g4, [%l0+%g3] | |
| 702 | send_all_precharge_8th_step: | |
| 703 | ! add %l6, 0x908, %l1 | |
| 704 | ! set 0x80600002, %g6 | |
| 705 | stx %g6, [%l1+%g0] | |
| 706 | stx %g6, [%l1+%g1] | |
| 707 | stx %g6, [%l1+%g2] | |
| 708 | stx %g6, [%l1+%g3] | |
| 709 | ||
| 710 | ||
| 711 | send_auto_refresh1st_step: | |
| 712 | ! add %l6, 0x900, %l0 | |
| 713 | stx %l3, [%l0+%g0] | |
| 714 | stx %l3, [%l0+%g1] | |
| 715 | stx %l3, [%l0+%g2] | |
| 716 | stx %l3, [%l0+%g3] | |
| 717 | send_auto_refresh2nd_step: | |
| 718 | ! add %l6, 0x908, %l1 | |
| 719 | set 0x80600001,%g6 | |
| 720 | stx %g6, [%l1+%g0] | |
| 721 | stx %g6, [%l1+%g1] | |
| 722 | stx %g6, [%l1+%g2] | |
| 723 | stx %g6, [%l1+%g3] | |
| 724 | send_auto_refresh3rd_step: | |
| 725 | ! add %l6, 0x900, %l0 | |
| 726 | stx %g4, [%l0+%g0] | |
| 727 | stx %g4, [%l0+%g1] | |
| 728 | stx %g4, [%l0+%g2] | |
| 729 | stx %g4, [%l0+%g3] | |
| 730 | send_auto_refresh4th_step: | |
| 731 | ! add %l6, 0x908, %l1 | |
| 732 | ! set 0x80600001, %g6 | |
| 733 | stx %g6, [%l1+%g0] | |
| 734 | stx %g6, [%l1+%g1] | |
| 735 | stx %g6, [%l1+%g2] | |
| 736 | stx %g6, [%l1+%g3] | |
| 737 | ||
| 738 | ||
| 739 | Wait_state: | |
| 740 | nop; | |
| 741 | nop; | |
| 742 | nop; | |
| 743 | nop; | |
| 744 | nop; | |
| 745 | nop; | |
| 746 | nop; | |
| 747 | nop; | |
| 748 | nop; | |
| 749 | nop; | |
| 750 | nop; | |
| 751 | nop; | |
| 752 | nop; | |
| 753 | nop; | |
| 754 | nop; | |
| 755 | nop; | |
| 756 | nop; | |
| 757 | nop; | |
| 758 | nop; | |
| 759 | nop; | |
| 760 | nop; | |
| 761 | send_auto_refresh_again_1st_step: | |
| 762 | ! add %l6, 0x900, %l0 | |
| 763 | stx %l3, [%l0+%g0] | |
| 764 | stx %l3, [%l0+%g1] | |
| 765 | stx %l3, [%l0+%g2] | |
| 766 | stx %l3, [%l0+%g3] | |
| 767 | send_auto_refresh_again_2nd_step: | |
| 768 | ! add %l6, 0x908, %l1 | |
| 769 | ! set 0x80600001,%g6 | |
| 770 | stx %g6, [%l1+%g0] | |
| 771 | stx %g6, [%l1+%g1] | |
| 772 | stx %g6, [%l1+%g2] | |
| 773 | stx %g6, [%l1+%g3] | |
| 774 | send_auto_refresh_again_3rd_step: | |
| 775 | ! add %l6, 0x900, %l0 | |
| 776 | stx %g4, [%l0+%g0] | |
| 777 | stx %g4, [%l0+%g1] | |
| 778 | stx %g4, [%l0+%g2] | |
| 779 | stx %g4, [%l0+%g3] | |
| 780 | send_auto_refresh_again_4th_step: | |
| 781 | ! add %l6, 0x908, %l1 | |
| 782 | ! set 0x80600001, %g6 | |
| 783 | stx %g6, [%l1+%g0] | |
| 784 | stx %g6, [%l1+%g1] | |
| 785 | stx %g6, [%l1+%g2] | |
| 786 | stx %g6, [%l1+%g3] | |
| 787 | ||
| 788 | ||
| 789 | #ifdef SNG_CHANNEL | |
| 790 | set 0x30000,%g6 | |
| 791 | #endif | |
| 792 | /***#ifdef DUAL_CHANNEL***/ | |
| 793 | dual_channel_0: | |
| 794 | set 0x20000,%g6 | |
| 795 | /**#endif***/ | |
| 796 | ||
| 797 | ||
| 798 | issue_mrs: | |
| 799 | ! add %l6, 0x900, %l0 | |
| 800 | stx %l6, [%l0+%g0] | |
| 801 | stx %l6, [%l0+%g1] | |
| 802 | stx %l6, [%l0+%g2] | |
| 803 | stx %l6, [%l0+%g3] | |
| 804 | issue_mrs_2nd_step: | |
| 805 | ! add %l6, 0x908, %l1 | |
| 806 | set 0x4300000, %g7 | |
| 807 | or %g7, %g6, %g7 | |
| 808 | stx %g7, [%l1+%g0] | |
| 809 | stx %g7, [%l1+%g1] | |
| 810 | stx %g7, [%l1+%g2] | |
| 811 | stx %g7, [%l1+%g3] | |
| 812 | issue_mrs_3rd_step: | |
| 813 | ! add %l6, 0x900, %l0 | |
| 814 | stx %l3, [%l0+%g0] | |
| 815 | stx %l3, [%l0+%g1] | |
| 816 | stx %l3, [%l0+%g2] | |
| 817 | stx %l3, [%l0+%g3] | |
| 818 | issue_mrs_4th_step: | |
| 819 | ! add %l6, 0x908, %l1 | |
| 820 | set 0x80600003,%g6 | |
| 821 | stx %g6, [%l1+%g0] | |
| 822 | stx %g6, [%l1+%g1] | |
| 823 | stx %g6, [%l1+%g2] | |
| 824 | stx %g6, [%l1+%g3] | |
| 825 | ||
| 826 | issue_mrs_5th_step: | |
| 827 | ! add %l6, 0x900, %l0 | |
| 828 | stx %g5, [%l0+%g0] | |
| 829 | stx %g5, [%l0+%g1] | |
| 830 | stx %g5, [%l0+%g2] | |
| 831 | stx %g5, [%l0+%g3] | |
| 832 | issue_mrs_6th_step: | |
| 833 | ! add %l6, 0x908, %l1 | |
| 834 | stx %g7, [%l1+%g0] | |
| 835 | stx %g7, [%l1+%g1] | |
| 836 | stx %g7, [%l1+%g2] | |
| 837 | stx %g7, [%l1+%g3] | |
| 838 | ||
| 839 | issue_mrs_7th_step: | |
| 840 | ! add %l6, 0x900, %l0 | |
| 841 | stx %g4, [%l0+%g0] | |
| 842 | stx %g4, [%l0+%g1] | |
| 843 | stx %g4, [%l0+%g2] | |
| 844 | stx %g4, [%l0+%g3] | |
| 845 | issue_mrs_8th_step: | |
| 846 | ! add %l6, 0x908, %l1 | |
| 847 | stx %g6, [%l1+%g0] | |
| 848 | stx %g6, [%l1+%g1] | |
| 849 | stx %g6, [%l1+%g2] | |
| 850 | stx %g6, [%l1+%g3] | |
| 851 | ||
| 852 | ||
| 853 | issue_emrs_1: | |
| 854 | ! add %l6, 0x900, %l0 | |
| 855 | stx %l6, [%l0+%g0] | |
| 856 | stx %l6, [%l0+%g1] | |
| 857 | stx %l6, [%l0+%g2] | |
| 858 | stx %l6, [%l0+%g3] | |
| 859 | issue_emrs_1_2nd_step: | |
| 860 | ! add %l6, 0x908, %l1 | |
| 861 | set 0x3800001, %g7 | |
| 862 | stx %g7, [%l1+%g0] | |
| 863 | stx %g7, [%l1+%g1] | |
| 864 | stx %g7, [%l1+%g2] | |
| 865 | stx %g7, [%l1+%g3] | |
| 866 | issue_emrs_1_3rd_step: | |
| 867 | ! add %l6, 0x900, %l0 | |
| 868 | stx %l3, [%l0+%g0] | |
| 869 | stx %l3, [%l0+%g1] | |
| 870 | stx %l3, [%l0+%g2] | |
| 871 | stx %l3, [%l0+%g3] | |
| 872 | issue_emrs_1_4th_step: | |
| 873 | ! add %l6, 0x908, %l1 | |
| 874 | ! set 0x80600003,%g6 | |
| 875 | stx %g6, [%l1+%g0] | |
| 876 | stx %g6, [%l1+%g1] | |
| 877 | stx %g6, [%l1+%g2] | |
| 878 | stx %g6, [%l1+%g3] | |
| 879 | ||
| 880 | issue_emrs_1_5th_step: | |
| 881 | ! add %l6, 0x900, %l0 | |
| 882 | stx %g5, [%l0+%g0] | |
| 883 | stx %g5, [%l0+%g1] | |
| 884 | stx %g5, [%l0+%g2] | |
| 885 | stx %g5, [%l0+%g3] | |
| 886 | issue_emrs_1_6th_step: | |
| 887 | ! add %l6, 0x908, %l1 | |
| 888 | stx %g7, [%l1+%g0] | |
| 889 | stx %g7, [%l1+%g1] | |
| 890 | stx %g7, [%l1+%g2] | |
| 891 | stx %g7, [%l1+%g3] | |
| 892 | ||
| 893 | issue_emrs_1_7th_step: | |
| 894 | ! add %l6, 0x900, %l0 | |
| 895 | stx %g4, [%l0+%g0] | |
| 896 | stx %g4, [%l0+%g1] | |
| 897 | stx %g4, [%l0+%g2] | |
| 898 | stx %g4, [%l0+%g3] | |
| 899 | issue_emrs_1_8th_step: | |
| 900 | ! add %l6, 0x908, %l1 | |
| 901 | stx %g6, [%l1+%g0] | |
| 902 | stx %g6, [%l1+%g1] | |
| 903 | stx %g6, [%l1+%g2] | |
| 904 | stx %g6, [%l1+%g3] | |
| 905 | ||
| 906 | issue_emrs_2: | |
| 907 | ! add %l6, 0x900, %l0 | |
| 908 | stx %l6, [%l0+%g0] | |
| 909 | stx %l6, [%l0+%g1] | |
| 910 | stx %l6, [%l0+%g2] | |
| 911 | stx %l6, [%l0+%g3] | |
| 912 | issue_emrs_2_2nd_step: | |
| 913 | ! add %l6, 0x908, %l1 | |
| 914 | set 0x1800001, %g7 | |
| 915 | stx %g7, [%l1+%g0] | |
| 916 | stx %g7, [%l1+%g1] | |
| 917 | stx %g7, [%l1+%g2] | |
| 918 | stx %g7, [%l1+%g3] | |
| 919 | issue_emrs_2_3rd_step: | |
| 920 | ! add %l6, 0x900, %l0 | |
| 921 | stx %l3, [%l0+%g0] | |
| 922 | stx %l3, [%l0+%g1] | |
| 923 | stx %l3, [%l0+%g2] | |
| 924 | stx %l3, [%l0+%g3] | |
| 925 | issue_emrs_2_4th_step: | |
| 926 | ! add %l6, 0x908, %l1 | |
| 927 | ! set 0x80600003,%g6 | |
| 928 | stx %g6, [%l1+%g0] | |
| 929 | stx %g6, [%l1+%g1] | |
| 930 | stx %g6, [%l1+%g2] | |
| 931 | stx %g6, [%l1+%g3] | |
| 932 | ||
| 933 | issue_emrs_2_5th_step: | |
| 934 | ! add %l6, 0x900, %l0 | |
| 935 | stx %g5, [%l0+%g0] | |
| 936 | stx %g5, [%l0+%g1] | |
| 937 | stx %g5, [%l0+%g2] | |
| 938 | stx %g5, [%l0+%g3] | |
| 939 | issue_emrs_2_6th_step: | |
| 940 | ! add %l6, 0x908, %l1 | |
| 941 | stx %g7, [%l1+%g0] | |
| 942 | stx %g7, [%l1+%g1] | |
| 943 | stx %g7, [%l1+%g2] | |
| 944 | stx %g7, [%l1+%g3] | |
| 945 | ||
| 946 | issue_emrs_2_7th_step: | |
| 947 | ! add %l6, 0x900, %l0 | |
| 948 | stx %g4, [%l0+%g0] | |
| 949 | stx %g4, [%l0+%g1] | |
| 950 | stx %g4, [%l0+%g2] | |
| 951 | stx %g4, [%l0+%g3] | |
| 952 | issue_emrs_2_8th_step: | |
| 953 | ! add %l6, 0x908, %l1 | |
| 954 | stx %g6, [%l1+%g0] | |
| 955 | stx %g6, [%l1+%g1] | |
| 956 | stx %g6, [%l1+%g2] | |
| 957 | stx %g6, [%l1+%g3] | |
| 958 | ||
| 959 | dram_init_done: | |
| 960 | clr %g4 | |
| 961 | clr %g5 | |
| 962 | clr %g6 | |
| 963 | clr %l0 | |
| 964 | clr %l1 | |
| 965 | clr %l2 | |
| 966 | clr %l3 | |
| 967 | clr %l3 | |
| 968 | clr %l4 | |
| 969 | clr %l5 | |
| 970 | clr %i5 | |
| 971 | clr %g1 | |
| 972 | clr %g2 | |
| 973 | clr %g3 |