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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / n0_c6_test4_noSpu.s
CommitLineData
86530b38
AT		 1/************************************************************************
2 Test case code start
3 ************************************************************************/
4
5.text
6.global main_th_48
7.global main_th_49
8.global main_th_50
9.global main_th_51
10.global main_th_52
11.global main_th_53
12.global main_th_54
13.global main_th_55
14
15!
16! Thread 0 Start
17!
18main_th_48:
19 TEST
20 setx t48_data_area, %g1, %l7
21 setx t48_blk_area,%g1,%g5;
22 setx 0x5555555555555555, %g3, %g4
23
24 !# Enable PMU to count instructions...
25 setx t48_t54_perf,%g3,%g6;
26 ldx [%g6],%g6;
27 wr %g0, %g0, %pic
28 wr %g6, %g0, %pcr
29
30 !# Make sure FP trap enables are off...
31
32 stx %g0, [%l7]
33 ldx [%l7], %fsr
34
35 stx %g4, [%l7]
36 ldd [%l7], %f6
37 fxtod %f6, %f0
38 fxtod %f6, %f2
39
40
41 !# Execute Main Diag ..
42 setx loop_cnt_4, %g2,%g1 !msa
43 set 0x0, %g2
44 addcc %g0, 0x0, %g3
45 setx 0xffffffffffffffff, %g2, %l2
46t48_start:
47 xor %l1, %l2, %l1
48 !#add %l0, 0x1efe, %l0
49 add %l0, -0xefe, %l0
50 fmuld %f0, %f2, %f4
51 ldd [%l7], %f6
52
53 !stb %g0,[%g5]
54
55 xor %l1, %l2, %l1
56 add %l0, -0xefe, %l0
57 fmuld %f0, %f2, %f4
58 ldd [%l7], %f6
59
60 bpos %xcc,t48_start
61 subcc %g1,1,%g1
62
63 setx t48_perf_cnt,%g1,%g2
64 rd %pic,%g1;
65 stx %g1,[%g2];
66 EXIT_GOOD
67
68!
69! Thread 1 Start
70!
71main_th_49:
72 TEST
73 setx t49_data_area, %g1, %l7
74 setx t49_blk_area,%g1,%g5;
75
76 !# Initialize registers ..
77 !# Enable PMU to count instructions...
78 setx t48_t54_perf,%g3,%g6;
79 ldx [%g6],%g6;
80 !#setx 0x17f85fe7, %g3, %g6
81 wr %g0, %g0, %pic
82 wr %g6, %g0, %pcr
83
84 !# Make sure FP trap enables are off...
85 stx %g0, [%l7]
86 ldx [%l7], %fsr
87
88 setx 0xf0f0f0abcdef9fff, %g3, %g4
89 stx %g4, [%l7]
90 ldd [%l7], %f6
91 fxtod %f6, %f0
92 fxtod %f6, %f2
93
94 !# Execute Main Diag ..
95 setx loop_cnt_3, %g2, %g1
96 set 0x0, %g2
97 addcc %g0, 0x0, %g3
98 setx 0xffffffffffffffff, %g2, %l2
99 ba,a t49_start
100.align 32
101t49_start:
102
103 !addcc %g1,-0xfff,%g1
104
105 ldd [%l7], %f6
106 fmuld %f0, %f2, %f4
107 add %l0, -0xefe, %l0
108 xor %l1, %l2, %l1
109
110 !stxa %l2,[%g5] 0xe2
111 stb %l2,[%g5]
112
113 ldd [%l7], %f6
114 fmuld %f0, %f2, %f4
115 add %l0, -0xefe, %l0
116 xor %l1, %l2, %l1
117
118 bpos %xcc,t49_start
119 !addcc %g1,-0xfff,%g1
120 subcc %g1,1,%g1
121
122 setx t49_perf_cnt,%g1,%g2
123 rd %pic,%g1;
124 stx %g1,[%g2];
125 EXIT_GOOD
126
127!
128! Thread 2 T2_Start
129!
130main_th_50:
131 TEST
132 setx t50_data_area, %g1, %l7
133 setx t50_blk_area,%g1,%g5;
134
135 !# Initialize registers ..
136 !# Enable PMU to count instructions...
137 setx t48_t54_perf,%g3,%g6;
138 ldx [%g6],%g6;
139 !#setx 0x17f85fe7, %g3, %g6
140 wr %g0, %g0, %pic
141 wr %g6, %g0, %pcr
142
143 !# Make sure FP trap enables are off...
144 stx %g0, [%l7]
145 ldx [%l7], %fsr
146
147 setx 0xefefefdcdcababab, %g3, %g4
148 stx %g4, [%l7]
149 ldd [%l7], %f6
150 fxtod %f6, %f0
151 fxtod %f6, %f2
152
153
154 !# Execute Main Diag ..
155 setx loop_cnt_3, %g2, %g1
156 set 0x0, %g2
157 addcc %g0, 0x0, %g3
158 ba,a t50_start
159.align 32
160t50_start:
161 ldx [%l7], %l5
162 fmuld %f0, %f2, %f4
163 fmuld %f0, %f2, %f4
164 fmuld %f0, %f2, %f4
165 add %l0, -0xefe, %l0
166 xor %l1, %l2, %l1
167 stb %g0,[%g5]
168
169 ldd [%l7], %f6
170 fmuld %f0, %f2, %f4
171 add %l0, -0xefe, %l0
172 xor %l1, %l2, %l1
173
174 bpos %xcc, t50_start
175 !addcc %g1,-0xfff,%g1
176 subcc %g1,1,%g1
177 setx t50_perf_cnt,%g1,%g2
178 rd %pic,%g1;
179 stx %g1,[%g2];
180 EXIT_GOOD
181
182!
183! Thread 3 T2_Start
184!
185main_th_51:
186 TEST
187 setx t51_data_area, %g1, %l7
188 setx t51_blk_area,%g1,%g5;
189
190 !# Initialize registers ..
191 !# Enable PMU to count instructions...
192 setx t48_t54_perf,%g3,%g6;
193 ldx [%g6],%g6;
194 !#setx 0x17f85fe7, %g3, %g6
195 wr %g0, %g0, %pic
196 wr %g6, %g0, %pcr
197
198 !# Make sure FP trap enables are off...
199 stx %g0, [%l7]
200 ldx [%l7], %fsr
201
202 setx 0xf9f8f7f6f5f4f3f2, %g3, %g4
203 stx %g4, [%l7]
204 ldd [%l7], %f6
205 fxtod %f6, %f0
206 fxtod %f6, %f2
207
208
209 !# Execute Main Diag ..
210 setx loop_cnt_2, %g2, %g1
211 set 0x0, %g2
212 addcc %g0, 0x0, %g3
213 ba,a t51_start
214.align 32
215t51_start:
216 xor %l1, %l2, %l1
217 add %l0, -0xefe, %l0
218 ldx [%l7], %l5
219!# fmuld %f0, %f2, %f4
220
221 !stb %g0,[%g5]
222 xor %l1, %l2, %l1
223 add %l0, -0xefe, %l0
224 ldd [%l7], %f6
225!# fmuld %f0, %f2, %f4
226
227 bpos %xcc,t51_start
228 !addcc %g1,-0xfff,%g1
229 subcc %g1,1,%g1
230 setx t51_perf_cnt,%g1,%g2
231 rd %pic,%g1;
232 stx %g1,[%g2];
233 EXIT_GOOD
234
235!
236! Thread 4 T3_Start
237!
238main_th_52:
239 TEST
240 setx t52_data_area, %g1, %l7
241 setx t52_blk_area,%g1,%g5;
242
243 !# Initialize registers ..
244 !# Enable PMU to count instructions...
245 setx t48_t54_perf,%g3,%g6;
246 ldx [%g6],%g6;
247 !#setx 0x17f85fe7, %g3, %g6
248 wr %g0, %g0, %pic
249 wr %g6, %g0, %pcr
250
251
252 !# Make sure trap enables are off...
253 !# Global registers
254 setx 0xaaaaaaaaaaaaaaaa, %g3, %g4
255 stx %g0, [%l7]
256 ldx [%l7], %fsr
257
258 stx %g4, [%l7]
259 ldd [%l7], %f6
260 fxtod %f6, %f0
261 fxtod %f6, %f2
262
263
264 !# Execute Main Diag ..
265 setx loop_cnt, %g2, %g1
266 set 0x0, %g2
267 addcc %g0, 0x0, %g3
268t52_start:
269 ldx [%l7], %l5
270 fmuld %f0, %f2, %f4
271!# add %l0, -0xemv, %l0
272 xor %l1, %l2, %l1
273
274 !stb %g4,[%g5]
275 ldd [%l7], %f6
276 fmuld %f0, %f2, %f4
277 add %l0, -0xefe, %l0
278 xor %l1, %l2, %l1
279 ldx [%l7], %l5
280
281 bpos %xcc,t52_start
282 !addcc %g1,-0xfff,%g1
283 subcc %g1,1,%g1
284
285 setx t52_perf_cnt,%g1,%g2
286 rd %pic,%g1;
287 stx %g1,[%g2];
288 EXIT_GOOD
289
290!
291! Thread 5 Start
292!
293main_th_53:
294 TEST
295 setx t53_data_area, %g1, %l7
296 setx t53_blk_area,%g1,%g5;
297
298 !# Initialize registers ..
299 !# Enable PMU to count instructions...
300 setx t48_t54_perf,%g3,%g6;
301 ldx [%g6],%g6;
302 !#setx 0x17f85fe7, %g3, %g6
303 wr %g0, %g0, %pic
304 wr %g6, %g0, %pcr
305
306
307 !# Make sure trap enables are off...
308 !# Global registers
309 setx 0xaaaaaaaaaaaaaaaa, %g3, %g4
310 stx %g0, [%l7]
311 ldx [%l7], %fsr
312
313 stx %g4, [%l7]
314 ldd [%l7], %f6
315 fxtod %f6, %f0
316 fxtod %f6, %f2
317
318
319 !# Execute Main Diag ..
320 setx loop_cnt, %g2, %g1
321 set 0x0, %g2
322 addcc %g0, 0x0, %g3
323 ba,a t53_start
324.align 32
325t53_start:
326 ldx [%l7], %l5
327 ldx [%l7], %l5
328 ldx [%l7], %l5
329 ldx [%l7], %l5
330 fmuld %f0, %f2, %f4
331 add %l0, -0xefe, %l0
332 xor %l1, %l2, %l1
333
334 !stb %g4,[%g5]
335 ldd [%l7], %f6
336 fmuld %f0, %f2, %f4
337 add %l0, -0xefe, %l0
338 xor %l1, %l2, %l1
339
340 bpos %xcc,t53_start
341 !addcc %g1,-0xfff,%g1
342 subcc %g1,1,%g1
343 setx t53_perf_cnt,%g1,%g2
344 rd %pic,%g1;
345 stx %g1,[%g2];
346 EXIT_GOOD
347
348!
349! Thread 6 Start
350!
351main_th_54:
352 TEST
353 setx t54_data_area, %g1, %l7
354 setx t54_blk_area,%g1,%g5;
355
356 !# Initialize registers ..
357 !# Enable PMU to count instructions...
358 setx t48_t54_perf,%g3,%g6;
359 ldx [%g6],%g6;
360 !#setx 0x17f85fe7, %g3, %g6
361 wr %g0, %g0, %pic
362 wr %g6, %g0, %pcr
363
364 !# Make sure trap enables are off...
365 !# Global registers
366 setx 0xfedcba9876543210, %g3, %g4
367 stx %g0, [%l7]
368 ldx [%l7], %fsr
369
370 stx %g4, [%l7]
371 ldd [%l7], %f6
372 fxtod %f6, %f0
373 fxtod %f6, %f2
374
375
376 !# Execute Main Diag ..
377 setx loop_cnt_2, %g2, %g1
378 set 0x0, %g2
379 addcc %g0, 0x0, %g3
380 ba,a t54_start
381.align 32
382t54_start:
383 ldx [%l7], %l5
384 ldx [%l7], %l5
385!# fmuld %f0, %f2, %f4
386!# add %l0, 0x1efe, %l0
387!# xor %l1, %l2, %l1
388
389 !stb %g4,[%g5]
390 ldd [%l7], %f6
391 fmuld %f0, %f2, %f4
392 ldx [%l7], %l5
393!# add %l0, 0x1efe, %l0
394!# xor %l1, %l2, %l1
395
396 bpos %xcc,t54_start
397 !addcc %g1,-0xfff,%g1
398 subcc %g1,1,%g1
399 setx t54_perf_cnt,%g1,%g2
400 rd %pic,%g1;
401 stx %g1,[%g2];
402 EXIT_GOOD
403
404!
405! Thread 7 Start
406!
407!
408main_th_55:
409 TEST
410
411 setx 0x612345000, %g7, %l0 ! bits [16:8] selects index in 4 bank mode
412 setx 0x623456040, %g7, %l1
413 setx 0x634567080, %g7, %l2
414 setx 0x6456780c0, %g7, %l3
415 setx 0x656789100, %g7, %l4
416 setx 0x66789a140, %g7, %l5
417 setx 0x6789ab180, %g7, %l6
418 setx 0x689abc1c0, %g7, %l7
419
420 setx NUM_LOOP_TH7, %i0, %o1
421loop_th55:
422 !Bank0
423 ld [%l0], %i1 !ld miss
424 ld [%l0+0x8], %i2 !ld hit
425 st %g0, [%l0+0x200] !st miss
426 st %g0, [%l0+0x208] !st hit
427
428 !Bank1
429 ld [%l1], %i1 !ld miss
430 ld [%l1+0x8], %i2 !ld hit
431 st %g0, [%l1+0x200] !st miss
432 st %g0, [%l1+0x208] !st hit
433
434 !Bank2
435 ld [%l2], %i1 !ld miss
436 ld [%l2+0x8], %i2 !ld hit
437 st %g0, [%l2+0x200] !st miss
438 st %g0, [%l2+0x208] !st hit
439
440 !Bank3
441 ld [%l3], %i1 !ld miss
442 ld [%l3+0x8], %i2 !ld hit
443 st %g0, [%l3+0x200] !st miss
444 st %g0, [%l3+0x208] !st hit
445
446 !Bank4
447 ld [%l4], %i1 !ld miss
448 ld [%l4+0x8], %i2 !ld hit
449 st %g0, [%l4+0x200] !st miss
450 st %g0, [%l4+0x208] !st hit
451
452 !Bank5
453 ld [%l5], %i1 !ld miss
454 ld [%l5+0x8], %i2 !ld hit
455 st %g0, [%l5+0x200] !st miss
456 st %g0, [%l5+0x208] !st hit
457
458 !Bank6
459 ld [%l6], %i1 !ld miss
460 ld [%l6+0x8], %i2 !ld hit
461 st %g0, [%l6+0x200] !st miss
462 st %g0, [%l6+0x208] !st hit
463
464 !Bank7
465 ld [%l7], %i1 !ld miss
466 ld [%l7+0x8], %i2 !ld hit
467 st %g0, [%l7+0x200] !st miss
468 st %g0, [%l7+0x208] !st hit
469
470 add %l0, 0x400, %l0
471 add %l1, 0x400, %l1
472 add %l2, 0x400, %l2
473 add %l3, 0x400, %l3
474 add %l4, 0x400, %l4
475 add %l5, 0x400, %l5
476 add %l6, 0x400, %l6
477 add %l7, 0x400, %l7
478
479 dec %o1
480 cmp %o1, 0
481 bne %xcc, loop_th55
482 nop
483
484 EXIT_GOOD
485!=================================================================================================
486fail_t55_1:
487 set 0x1,%g2;
488 ba fail_t55;
489 nop;
490fail_t55_2:
491 set 0x2,%g2;
492 ba fail_t55;
493 nop;
494fail_t55_3:
495 set 0x3,%g2;
496 ba fail_t55;
497 nop;
498fail_t55_4:
499 set 0x4,%g2;
500 ba fail_t55;
501 nop;
502fail_t55_5:
503 set 0x5,%g2;
504 ba fail_t55;
505 nop;
506fail_t55_6:
507 set 0x6,%g2;
508 ba fail_t55;
509 nop;
510fail_t55_7:
511 set 0x7,%g2;
512 ba fail_t55;
513 nop;
514fail_t55_8:
515 set 0x8,%g2;
516 ba fail_t55;
517 nop;
518fail_t55_9:
519 set 0x9,%g2;
520 ba fail_t55;
521 nop;
522fail_t55_10:
523 set 0xa,%g2;
524 ba fail_t55;
525 nop;
526fail_t55_11:
527 set 0xb,%g2;
528 ba fail_t55;
529 nop;
530fail_t55_12:
531 set 0xc,%g2;
532 ba fail_t55;
533 nop;
534fail_t55_13:
535 set 0xd,%g2;
536 ba fail_t55;
537 nop;
538fail_t55_14:
539 set 0xe,%g2;
540 ba fail_t55;
541 nop;
542fail_t55_15:
543 set 0xf,%g2;
544 ba fail_t55;
545 nop;
546fail_t55_16:
547 set 0x10,%g2;
548 ba fail_t55;
549 nop;
550fail_t55:
551 setx t55_fail,%g3,%g1
552 stx %g2,[%g1]
553 EXIT_BAD
554
555/************************************************************************
556 Test case data start
557 ************************************************************************/
558.data
559
560t48_data_area:
561.skip 16384
562
563t49_data_area:
564.skip 16384
565.skip 16
566
567t50_data_area:
568.skip 16384
569.skip 16
570
571t51_data_area:
572.skip 16384
573.skip 16
574
575t52_data_area:
576.skip 16384
577.skip 16
578
579t53_data_area:
580.skip 16384
581.skip 16
582
583t54_data_area:
584.skip 16384
585.skip 16
586
587t55_data_area:
588.align 16
589!# A operand, 32 doublewords
590!# %l7 points to here:
591.xword 0xb61e0f74d889169f !# a[0] for 3
592.xword 0xeb7dad6d2db34663 !# a[1] for 3
593.xword 0x000000069fad6615 !# a[2] for 3
594.xword 0x0 !# a[3] for 3
595.xword 0x0 !# a[4] for 3
596.xword 0x0 !# a[5] for 3
597.xword 0x0 !# a[6] for 3
598.xword 0x0 !# a[7] for 3
599
600.xword 0x85587F96342B939A
601.xword 0x00DD7AAD15E30EB1
602.xword 0xFFFFEEEE00006000
603.xword 0xFFFFEEEE00007000
604.xword 0x222D15F21092A854
605.xword 0xFFFFEEEE00009000
606.xword 0xFD2CB924281A7FB1
607.xword 0xFFFFEEEE0000B000
608
609.xword 0x12D7C16982229DCF
610.xword 0xA75C18D599E04451
611.xword 0xA3BE82C81B280E9D
612.xword 0x8964B57FD2745FFB
613.xword 0x4103465563EB1347
614.xword 0xB4181F76C7A2CE01
615.xword 0xFFFFFFFF10005000
616.xword 0x4AC14D5A55D9D2BD
617
618!#.xword 0x9711E4D4E862AFA7
619.xword 0x2313258847A86E70
620.xword 0x47A084C3801DE4F9
621.xword 0x6B655B6A27D64052
622.xword 0x48CBC2665D6D8BB8
623.xword 0xD60A8BF421AA5DC8
624.xword 0xF4529D511F583B2D
625.xword 0xFFFFFFFF1000D000
626.xword 0x27A0C706E2B783D4
627
628!# m[0] starts here
629.xword 0x00004FFF0000FFFF !#
630.xword 0x0FFF8000FFFF0001 !#
631.xword 0xF000FFFF0000FF00 !#
632.xword 0x0000FFFF0000FF00 !#
633.xword 0x1A890F27A74D6D4F !#
634.xword 0xB34C93D130DF03BC !#
635.xword 0xFD33BC46D2B25B52 !#
636.xword 0x0FFFFFFF00006000 !#
637
638.xword 0x9000111122223333
639.xword 0x4444555566667777
640.xword 0xFFFFEEEE00006000
641.xword 0xFFFFEEEE00007000
642.xword 0x222D15F21092A854
643.xword 0xFFFFEEEE00009000
644.xword 0xFD2CB924281A7FB1
645.xword 0xFFFFEEEE0000B000
646
647.xword 0x0000111122223333
648.xword 0x0000111122223333
649.xword 0x0000111122223333
650.xword 0x0000111122223333
651.xword 0x0000111122223333
652.xword 0x0000111122223333
653.xword 0x0000111122223333
654.xword 0x0000111122223333
655
656.xword 0x0000111122223333
657.xword 0x0000111122223333
658.xword 0xA000111122223333
659.xword 0x0000111122223333
660.xword 0x0000111122223333
661.xword 0x0000111122223333
662.xword 0x0000111122223333
663.xword 0xFFFFFFFF22223333
664
665!# N operand, 32 doublewords
666.xword 0x00000000000000c9 !# 3. n[0]
667.xword 0x0000000000000000 !# 3. n[1]
668.xword 0x0000000800000000 !# 3. n[2]
669.xword 0x0 !# 3. n[3]
670.xword 0x0 !# 3. n[4]
671.xword 0x0 !# 3. n[5]
672.xword 0x0 !# 3. n[6]
673.xword 0x0 !# 3. n[7]
674
675.xword 0xFFFFFFFF00007000
676.xword 0xFFFFFFFF00008000
677.xword 0xFFFFFFFF00009000
678.xword 0xFFFFFFFF0000A000
679.xword 0xFFFFFFFF0000B000
680.xword 0xFFFFFFFF0000C000
681.xword 0xFAEDBEEF0000D000
682.xword 0xFFFFFFFF0000E000
683
684.xword 0xFFFFFFFF0000F000
685.xword 0xFFFFFFFF10000000
686.xword 0xFFFFFFFF10001000
687.xword 0xFFFFFFFF10002000
688.xword 0xFFFFFFFF10003000
689.xword 0xFFFFFFFF10004000
690.xword 0xFFFFFFFF10005000
691.xword 0xFFFFFFFF10006000
692
693.xword 0xFFFFFFFF10007000
694.xword 0xFFFFFFFF10008000
695.xword 0xFFFFFFFF10009000
696.xword 0xFFFFFFFF1000A000
697.xword 0xFFFFFFFF1000B000
698.xword 0xEFFFFFFF1000C000
699.xword 0xFFFFFFFF1000D000
700.xword 0xFFFFFFFF1000E000
701
702!# E starts here
703.xword 0xAAAAAAAAAAAAAAAA !# 3. e[0]
704.xword 0xAAAAAAAAAAAAAAAA !# 3. e[1]
705.xword 0x0000000AAAAAAAAA !# 3. e[2]
706.xword 0x0 !# 3. e[3]
707.xword 0x0 !# 3. e[4]
708.xword 0x0 !# 3. e[5]
709.xword 0x0 !# 3. e[6]
710.xword 0x0 !# 3. e[7]
711
712.xword 0x0000111122223333
713.xword 0x0000111122223333
714.xword 0x0000111122223333
715.xword 0x0000111122223333
716.xword 0x0000111122223333
717.xword 0x0000111122223333
718.xword 0x0000111122223333
719.xword 0x0000111122223333
720
721.xword 0x0000111122223333
722.xword 0x0000111122223333
723.xword 0x0000111122223333
724.xword 0x0000111122223333
725.xword 0x0000111122223333
726.xword 0x0000111122223333
727.xword 0x0000111122223333
728.xword 0x0000111122223333
729
730.xword 0x0000111122223333
731.xword 0x0000111122223333
732.xword 0x0000111122223333
733.xword 0x0000111122223333
734.xword 0x0000111122223333
735.xword 0x0000111122223333
736.xword 0x0000111122223333
737.xword 0x0000111122223333
738
739!# Initial X value
740.xword 0xb61e0f74d889169f !# a[0] for 3
741.xword 0xeb7dad6d2db34663 !# a[1] for 3
742.xword 0x000000069fad6615 !# a[2] for 3
743!#.xword 0x0000001920000000 !# x[0] for 3
744!#.xword 0x0000000000000000 !# x[1] for 3
745!#.xword 0x0000000000000000 !# x[2] for 3
746.xword 0x0 !# x[3] for 3
747.xword 0x0 !# x[4] for 3
748.xword 0x0 !# x[5] for 3
749.xword 0x0 !# x[6] for 3
750.xword 0x0 !# x[7] for 3
751
752t55_expected_x:
753!# Expected X result starts here
754.xword 0x9890891c6f7c2d0b !# 3. X[0]
755.xword 0x8d0356cf2e263a36 !# 3. X[1]
756.xword 0x000000074dc55ef7 !# 3. X[2]
757
758t55_div_area:
759.xword 0x0011223344556677 !# junk area for divide wait loop operand storage
760.skip 16
761
762!================================================================================================
763!=================================================================================================
764.align 65536
765!# Subtest 1 start
766!# input data
767cleartext_t55:
768.xword 0x0011223344556677
769.xword 0x8899aabbccddeeff
770.skip 16384
771
772!# AES initial state (also where final state will be written)
773.align 16
774aes_state_t55:
775.xword 0x0001020304050607
776.xword 0x08090a0b0c0d0e0f
777.xword 0x1011121314151617
778.xword 0x18191a1b1c1d1e1f
779
780!# expected ciphertext
781ciphertext_t55:
782.xword 0x8ea2b7ca516745bf
783.xword 0xeafc49904b496089
784.skip 16384
785
786!# temporary area for storing expected result
787result_t55:
788.xword 0xDEADBEEFDEADBEEF
789.xword 0xDEADBEEFDEADBEEF
790.skip 16384
791
792!################################################
793!# CWQ data area, set aside 512 CW's worth
794!# 512*8*8 = 32KB
795.align 32*1024
796CWQ_BASE_t55:
797.xword 0xAAAAAAAAAAAAAAA
798.xword 0xAAAAAAAAAAAAAAA
799.xword 0xAAAAAAAAAAAAAAA
800.xword 0xAAAAAAAAAAAAAAA
801.xword 0xAAAAAAAAAAAAAAA
802.xword 0xAAAAAAAAAAAAAAA
803.xword 0xAAAAAAAAAAAAAAA
804.xword 0xAAAAAAAAAAAAAAA
805.align 32*1024
806CWQ_LAST_t55:
807.skip 16
808
809!=================================================================================================1
810.global t55_fail
811t55_fail:
812.xword 0x0000000000000000
813!==================================================================================================
814.global t48_t54_perf
815.global t55_perf
816.global t48_perf_cnt
817.global t49_perf_cnt
818.global t50_perf_cnt
819.global t51_perf_cnt
820.global t52_perf_cnt
821.global t53_perf_cnt
822.global t54_perf_cnt
823.global t55_perf_cnt
824t48_t54_perf:
825.xword 0x0000000017f85fe7
826t55_perf:
827.xword 0x0000000057f99fe7
828t48_perf_cnt:
829.xword 0x0000000000000000
830t49_perf_cnt:
831.xword 0x0000000000000000
832t50_perf_cnt:
833.xword 0x0000000000000000
834t51_perf_cnt:
835.xword 0x0000000000000000
836t52_perf_cnt:
837.xword 0x0000000000000000
838t53_perf_cnt:
839.xword 0x0000000000000000
840t54_perf_cnt:
841.xword 0x0000000000000000
842t55_perf_cnt:
843.xword 0x0000000000000000
844.skip 16
845!==================================================================================================
846.align 256 * 1024
847t48_blk_area:
848.xword 0x00ffffffffffffff
849.xword 0xffffffffffffffff
850.xword 0xffffffffffffffff
851.xword 0xffffffffffffffff
852.xword 0xffffffffffffffff
853.xword 0xffffffffffffffff
854.xword 0xffffffffffffffff
855.xword 0xffffffffffffffff
856.xword 0xffffffffffffffff
857.xword 0xffffffffffffffff
858.xword 0xffffffffffffffff
859.xword 0xffffffffffffffff
860.xword 0xffffffffffffffff
861.xword 0xffffffffffffffff
862.xword 0xffffffffffffffff
863.xword 0xffffffffffffffff
864.skip 64
865.align 256 * 1024
866t49_blk_area:
867.xword 0x0100000000000000
868.xword 0x0000000000000000
869.xword 0x0000000000000000
870.xword 0x0000000000000000
871.xword 0x0000000000000000
872.xword 0x0000000000000000
873.xword 0x0000000000000000
874.xword 0x0000000000000000
875.xword 0x0000000000000000
876.xword 0x0000000000000000
877.xword 0x0000000000000000
878.xword 0x0000000000000000
879.xword 0x0000000000000000
880.xword 0x0000000000000000
881.xword 0x0000000000000000
882.xword 0x0000000000000000
883.skip 64
884.align 256 * 1024
885t50_blk_area:
886.xword 0x02ffffffffffffff
887.xword 0xffffffffffffffff
888.xword 0xffffffffffffffff
889.xword 0xffffffffffffffff
890.xword 0xffffffffffffffff
891.xword 0xffffffffffffffff
892.xword 0xffffffffffffffff
893.xword 0xffffffffffffffff
894.xword 0xffffffffffffffff
895.xword 0xffffffffffffffff
896.xword 0xffffffffffffffff
897.xword 0xffffffffffffffff
898.xword 0xffffffffffffffff
899.xword 0xffffffffffffffff
900.xword 0xffffffffffffffff
901.xword 0xffffffffffffffff
902.skip 64
903.align 256 * 1024
904t51_blk_area:
905.xword 0x0300000000000000
906.xword 0x0000000000000000
907.xword 0x0000000000000000
908.xword 0x0000000000000000
909.xword 0x0000000000000000
910.xword 0x0000000000000000
911.xword 0x0000000000000000
912.xword 0x0000000000000000
913.xword 0x0000000000000000
914.xword 0x0000000000000000
915.xword 0x0000000000000000
916.xword 0x0000000000000000
917.xword 0x0000000000000000
918.xword 0x0000000000000000
919.xword 0x0000000000000000
920.xword 0x0000000000000000
921.skip 64
922.align 256 * 1024
923t52_blk_area:
924.xword 0x04ffffffffffffff
925.xword 0xffffffffffffffff
926.xword 0xffffffffffffffff
927.xword 0xffffffffffffffff
928.xword 0xffffffffffffffff
929.xword 0xffffffffffffffff
930.xword 0xffffffffffffffff
931.xword 0xffffffffffffffff
932.xword 0xffffffffffffffff
933.xword 0xffffffffffffffff
934.xword 0xffffffffffffffff
935.xword 0xffffffffffffffff
936.xword 0xffffffffffffffff
937.xword 0xffffffffffffffff
938.xword 0xffffffffffffffff
939.xword 0xffffffffffffffff
940.skip 64
941.align 256 * 1024
942t53_blk_area:
943.xword 0x0500000000000000
944.xword 0x0000000000000000
945.xword 0x0000000000000000
946.xword 0x0000000000000000
947.xword 0x0000000000000000
948.xword 0x0000000000000000
949.xword 0x0000000000000000
950.xword 0x0000000000000000
951.xword 0x0000000000000000
952.xword 0x0000000000000000
953.xword 0x0000000000000000
954.xword 0x0000000000000000
955.xword 0x0000000000000000
956.xword 0x0000000000000000
957.xword 0x0000000000000000
958.xword 0x0000000000000000
959.skip 64
960.align 256 * 1024
961t54_blk_area:
962.xword 0x06ffffffffffffff
963.xword 0xffffffffffffffff
964.xword 0xffffffffffffffff
965.xword 0xffffffffffffffff
966.xword 0xffffffffffffffff
967.xword 0xffffffffffffffff
968.xword 0xffffffffffffffff
969.xword 0xffffffffffffffff
970.xword 0xffffffffffffffff
971.xword 0xffffffffffffffff
972.xword 0xffffffffffffffff
973.xword 0xffffffffffffffff
974.xword 0xffffffffffffffff
975.xword 0xffffffffffffffff
976.xword 0xffffffffffffffff
977.xword 0xffffffffffffffff
978.skip 64
979.align 256 * 1024
980t55_blk_area:
981.xword 0x0700000000000000
982.xword 0x0000000000000000
983.xword 0x0000000000000000
984.xword 0x0000000000000000
985.xword 0x0000000000000000
986.xword 0x0000000000000000
987.xword 0x0000000000000000
988.xword 0x0000000000000000
989.xword 0x0000000000000000
990.xword 0x0000000000000000
991.xword 0x0000000000000000
992.xword 0x0000000000000000
993.xword 0x0000000000000000
994.xword 0x0000000000000000
995.xword 0x0000000000000000
996.xword 0x0000000000000000
997.skip 64
Full OpenSPARC design & verification tarball including full HDL.