projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: niu_defines.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define XPCS_CONTROL1 mpeval( 0x000 <<1) | |
| 39 | #define XPCS_STATUS1 mpeval( 0x004 <<1) | |
| 40 | #define XPCS_DEVICE_ID mpeval( 0x008 <<1) | |
| 41 | #define XPCS_SPEED_ABILITY mpeval( 0x00C <<1) | |
| 42 | #define XPCS_DEVICE_IN_PKG mpeval( 0x010 <<1) | |
| 43 | #define XPCS_CONTROL2 mpeval( 0x014 <<1) | |
| 44 | #define XPCS_STATUS2 mpeval( 0x018 <<1) | |
| 45 | #define XPCS_PKG_ID mpeval( 0x01C <<1) | |
| 46 | #define XPCS_STATUS mpeval( 0x020 <<1) | |
| 47 | #define XPCS_TEST_CONTROL mpeval( 0x024 <<1) | |
| 48 | #define XPCS_CONFIG_VENDOR1 mpeval( 0x028 <<1) | |
| 49 | #define XPCS_DIAG_VENDOR2 mpeval( 0x02C <<1) | |
| 50 | #define XPCS_MASK1 mpeval( 0x030 <<1) | |
| 51 | #define XPCS_PACKET_COUNTER mpeval( 0x034 <<1) | |
| 52 | #define XPCS_TX_STATEMACHINE mpeval( 0x038 <<1) | |
| 53 | #define XPCS_TX_DESKWERR_COUNTER mpeval( 0x03C <<1) | |
| 54 | ||
| 55 | #define NIU_BASE_ADDRESS 0x8100000000 | |
| 56 | #define FZC_MAC_BASE_ADDRESS 0x180000 | |
| 57 | #define TXC_BASE_ADDRESS 0x700000 | |
| 58 | #define FZC_TXC_BASE_ADDRESS 0x780000 | |
| 59 | #define TXC_DMA_MAXBURST 0x000 | |
| 60 | #define TXC_DMA_MAXBURST_MASK 0x00000000000fffff | |
| 61 | #define TXC_PORT_CONTROL_MASK 0x00000000ffffffff | |
| 62 | #define TXC_PORT0_CONTROL 0x020 /* 081505 MAQ #define TXC_PORT0_CONTROL 0x010 */ | |
| 63 | #define TXC_PORT1_CONTROL 0x120 /* 081505 MAQ #define TXC_PORT1_CONTROL 0x018 */ | |
| 64 | #define TXC_CONTROL 0x000 | |
| 65 | #define TXC_CONTROL_MASK 0x000000000000001f | |
| 66 | #define XPCS_0_RANGE mpeval(0x00001000 << 1) | |
| 67 | #define XPCS_1_RANGE mpeval(0x00004000 << 1) | |
| 68 | ||
| 69 | #define NEPTUNE_BASE_ADDRESS NIU_BASE_ADDRESS | |
| 70 | #define MAC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_MAC_BASE_ADDRESS) | |
| 71 | #define XPCS0_BASE mpeval(MAC_ADDRESS_RANGE + XPCS_0_RANGE) | |
| 72 | #define XPCS1_BASE mpeval(MAC_ADDRESS_RANGE + XPCS_1_RANGE) | |
| 73 | #define TXC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + TXC_BASE_ADDRESS) | |
| 74 | #define FZC_TXC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_TXC_BASE_ADDRESS) | |
| 75 | ||
| 76 | #define TXC_FZC_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x20 << 12)) | |
| 77 | #define TXC_PIO_BASE mpeval(TXC_ADDRESS_RANGE + (0x20 << 12)) | |
| 78 | ||
| 79 | #define xpcs_reg0_addr mpeval(XPCS0_BASE + XPCS_CONTROL1) | |
| 80 | #define xpcs_reg1_addr mpeval(XPCS0_BASE + XPCS_TEST_CONTROL) | |
| 81 | #define xpcs_reg2_addr mpeval(XPCS0_BASE + XPCS_CONFIG_VENDOR1) | |
| 82 | #define xpcs_reg3_addr mpeval(XPCS0_BASE + XPCS_DIAG_VENDOR2) | |
| 83 | #define xpcs_reg4_addr mpeval(XPCS0_BASE + XPCS_MASK1) | |
| 84 | #define xpcs_reg5_addr mpeval(XPCS0_BASE + XPCS_PACKET_COUNTER) | |
| 85 | #define xpcs_reg6_addr mpeval(XPCS0_BASE + XPCS_TX_DESKWERR_COUNTER) | |
| 86 | #define xpcs_reg7_addr mpeval(XPCS0_BASE + XPCS_STATUS1) | |
| 87 | #define xpcs_reg8_addr mpeval(XPCS0_BASE + XPCS_DEVICE_ID) | |
| 88 | #define xpcs_reg9_addr mpeval(XPCS0_BASE + XPCS_SPEED_ABILITY) | |
| 89 | #define xpcs_reg10_addr mpeval(XPCS0_BASE + XPCS_DEVICE_IN_PKG) | |
| 90 | #define xpcs_reg11_addr mpeval(XPCS0_BASE + XPCS_CONTROL2) | |
| 91 | #define xpcs_reg12_addr mpeval(XPCS0_BASE + XPCS_STATUS2) | |
| 92 | #define xpcs_reg13_addr mpeval(XPCS0_BASE + XPCS_PKG_ID) | |
| 93 | #define xpcs_reg14_addr mpeval(XPCS0_BASE + XPCS_STATUS) | |
| 94 | #define xpcs_reg15_addr mpeval(XPCS0_BASE + XPCS_TX_STATEMACHINE) | |
| 95 | ||
| 96 | #define xpcs_reg0_data 0x00002040 | |
| 97 | #define xpcs_reg1_data 0x00000000 | |
| 98 | #define xpcs_reg2_data 0x00000003 | |
| 99 | #define xpcs_reg3_data 0x00000000 | |
| 100 | #define xpcs_reg4_data 0x00000084 | |
| 101 | #define xpcs_reg5_data 0x00000000 | |
| 102 | #define xpcs_reg6_data 0x00000000 | |
| 103 | #define xpcs_reg7_data 0x00000080 | |
| 104 | #define xpcs_reg8_data 0x00000000 | |
| 105 | #define xpcs_reg9_data 0x00000001 | |
| 106 | #define xpcs_reg10_data 0xC0000008 | |
| 107 | #define xpcs_reg11_data 0x00000001 | |
| 108 | #define xpcs_reg12_data 0x00000802 | |
| 109 | #define xpcs_reg13_data 0x00000000 | |
| 110 | #define xpcs_reg14_data 0x00000800 | |
| 111 | #define xpcs_reg15_data 0x0000000C | |
| 112 | ||
| 113 | #define txc_dma0_addr mpeval(TXC_DMA0_BASE + TXC_DMA_MAXBURST) | |
| 114 | #define fzc_txc_addr mpeval(TXC_FZC_BASE + TXC_PORT0_CONTROL) | |
| 115 | #define txc_pio_addr mpeval(TXC_PIO_BASE + TXC_CONTROL) | |
| 116 | ||
| 117 | #define txc_dma0_data 0xa5a5a5a5a5a5a5a5 | |
| 118 | #define fzc_txc_data 0xffffffffffffffff | |
| 119 | #define txc_pio_data 0x1f | |
| 120 | ||
| 121 | #define FZC_PIO_BASE_ADDRESS 0x80000 | |
| 122 | #define FZC_PIO_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_PIO_BASE_ADDRESS) | |
| 123 | #define ZCP_BASE_ADDRESS 0x500000 | |
| 124 | #define ZCP_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + ZCP_BASE_ADDRESS) | |
| 125 | #define FZC_ZCP_BASE_ADDRESS 0x580000 | |
| 126 | #define FZC_ZCP_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_ZCP_BASE_ADDRESS) | |
| 127 | #define PIO_LDSV_BASE_ADDRESS 0x800000 | |
| 128 | #define PIO_LDSV_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + PIO_LDSV_BASE_ADDRESS) | |
| 129 | #define PIO_IMASK0_BASE_ADDRESS 0xa00000 | |
| 130 | #define PIO_IMASK0_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + PIO_IMASK0_BASE_ADDRESS) | |
| 131 | #define PIO_IMASK1_BASE_ADDRESS 0xb00000 | |
| 132 | #define PIO_IMASK1_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + PIO_IMASK1_BASE_ADDRESS) | |
| 133 | ||
| 134 | #define LDG_NUM mpeval(FZC_PIO_ADDRESS_RANGE+0x20000) | |
| 135 | #define LDG_NUM_COUNT 69 | |
| 136 | #define LDG_NUM_STEP 8 | |
| 137 | ||
| 138 | #define LDSV0 mpeval(PIO_LDSV_ADDRESS_RANGE+0x0) | |
| 139 | #define LDSV0_COUNT 64 | |
| 140 | #define LDSV0_STEP 8192 | |
| 141 | #define LDSV1 mpeval(PIO_LDSV_ADDRESS_RANGE+0x8) | |
| 142 | #define LDSV1_COUNT 64 | |
| 143 | #define LDSV1_STEP 8192 | |
| 144 | #define LDSV2 mpeval(PIO_LDSV_ADDRESS_RANGE+0x10) | |
| 145 | #define LDSV2_COUNT 64 | |
| 146 | #define LDSV2_STEP 8192 | |
| 147 | ||
| 148 | #define LD_IM0 mpeval(PIO_IMASK0_ADDRESS_RANGE+0x00000) | |
| 149 | #define LD_IM0_COUNT 64 | |
| 150 | #define LD_IM0_STEP 8192 | |
| 151 | #define LD_IM1 mpeval(PIO_IMASK1_ADDRESS_RANGE+0x00000) | |
| 152 | #define LD_IM1_COUNT 5 | |
| 153 | #define LD_IM1_STEP 8192 | |
| 154 | ||
| 155 | #define LDGIMGN mpeval(PIO_LDSV_ADDRESS_RANGE+0x00018) | |
| 156 | #define LDGIMGN_COUNT 64 | |
| 157 | #define LDGIMGN_STEP 8192 | |
| 158 | ||
| 159 | #define LDGITMRES mpeval(FZC_PIO_ADDRESS_RANGE+0x00008) | |
| 160 | ||
| 161 | #define SID mpeval(FZC_PIO_ADDRESS_RANGE+0x10200) | |
| 162 | #define SID_COUNT 64 | |
| 163 | #define SID_STEP 8 | |
| 164 | ||
| 165 | #define SMX_CFIG_DAT mpeval(FZC_PIO_ADDRESS_RANGE+0x40) | |
| 166 | #define SMX_INT_STAT mpeval(FZC_PIO_ADDRESS_RANGE+0x48) | |
| 167 | ||
| 168 | #define SYS_ERR_MASK mpeval(FZC_PIO_ADDRESS_RANGE+0x00090) | |
| 169 | #define SYS_ERR_STAT mpeval(FZC_PIO_ADDRESS_RANGE+0x00098) | |
| 170 | ||
| 171 | #define ZCP_INT_STAT mpeval(FZC_ZCP+0x8) | |
| 172 | #define ZCP_INT_MASK mpeval(FZC_ZCP+0x10) | |
| 173 | ||
| 174 | ||
| 175 | #define DMC_BASE_ADDRESS 0x600000 | |
| 176 | #define FZC_DMC_BASE_ADDRESS 0x680000 | |
| 177 | #define DMC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + DMC_BASE_ADDRESS) | |
| 178 | #define FZC_DMC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_DMC_BASE_ADDRESS) | |
| 179 | ||
| 180 | #define DEF_PORT0_RDC mpeval(FZC_DMC_ADDRESS_RANGE+0x00008) | |
| 181 | #define DEF_PORT1_RDC mpeval(FZC_DMC_ADDRESS_RANGE+0x00010) | |
| 182 | ||
| 183 | #define RX_ADDR_MD mpeval(FZC_DMC_ADDRESS_RANGE+0x00070) | |
| 184 | #define RDC_TABLE_BASE mpeval(FZC_DMC_ADDRESS_RANGE+0x10000) | |
| 185 | #define RX_LOG_PAGE_VLD mpeval(FZC_DMC_ADDRESS_RANGE+0x20000) | |
| 186 | #define RX_LOG_PAGE1 mpeval(FZC_DMC_ADDRESS_RANGE+0x20008) | |
| 187 | #define RX_LOG_PAGE2 mpeval(FZC_DMC_ADDRESS_RANGE+0x20010) | |
| 188 | #define RX_LOG_PAGE_RELO1 mpeval(FZC_DMC_ADDRESS_RANGE+0x20018) | |
| 189 | #define RX_LOG_PAGE_RELO2 mpeval(FZC_DMC_ADDRESS_RANGE+0x20020) | |
| 190 | #define Rx_LOG_PAGE_HDL mpeval(FZC_DMC_ADDRESS_RANGE+0x20028) | |
| 191 | #define RDC_RED_PARA mpeval(FZC_DMC_ADDRESS_RANGE+0x30000) | |
| 192 | ||
| 193 | #define RXDMA_CFIG_BASE mpeval(DMC_ADDRESS_RANGE+0x00000) | |
| 194 | #define RBR_CFIG_A mpeval(DMC_ADDRESS_RANGE+0x00010) | |
| 195 | #define RBR_CFIG_B mpeval(DMC_ADDRESS_RANGE+0x00018) | |
| 196 | #define RCRCFIG_A mpeval(DMC_ADDRESS_RANGE+0x00040) | |
| 197 | #define TBR_CFIG_A mpeval(DMC_ADDRESS_RANGE+0x10000) | |
| 198 | #define RBR_KICK mpeval(DMC_ADDRESS_RANGE+0x00020) | |
| 199 | #define RBR_HD mpeval(DMC_ADDRESS_RANGE+0x00030) | |
| 200 | #define RBR_TL mpeval(DMC_ADDRESS_RANGE+0x00038) | |
| 201 | #define RCR_STAT_A mpeval(DMC_ADDRESS_RANGE+0x00050) | |
| 202 | #define RCRCFIG_B mpeval(DMC_ADDRESS_RANGE+0x00048) | |
| 203 | #define RX_DMA_ENT_MSK mpeval(DMC_ADDRESS_RANGE+0x00068) | |
| 204 | #define THRES_MASK 0xffffffffffffbfff | |
| 205 | #define THRES_INT 0x0000800000000000 | |
| 206 | ||
| 207 | #define RX_DMA_CTL_STAT mpeval(DMC_ADDRESS_RANGE+0x70) | |
| 208 | #define RX_DMA_CTL_STAT_COUNT 16 | |
| 209 | #define RX_DMA_CTL_STAT_STEP 0x200 | |
| 210 | #define RX_DMA_CTL_STAT_DBG mpeval(DMC_ADDRESS_RANGE+0x98) | |
| 211 | #define RX_DMA_CTL_STAT_DBG_STEP 0x200 | |
| 212 | #define RX_DMA_CTL_STAT_DBG_COUNT 16 | |
| 213 | ||
| 214 | #define FZC_FFLP_BASE_ADDRESS 0x380000 | |
| 215 | #define FZC_FFLP_BASE_OFFSET 0x020000 | |
| 216 | #define FFLP_CONFIG 0x00100 | |
| 217 | #define FFLP_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_FFLP_BASE_ADDRESS + FZC_FFLP_BASE_OFFSET) | |
| 218 | #define XTxMAC_SW_RST mpeval(0x000 <<1) | |
| 219 | #define XRxMAC_SW_RST mpeval(0x004 <<1) | |
| 220 | #define XTxMAC_STATUS mpeval(0x010 <<1) | |
| 221 | #define XRxMAC_STATUS mpeval(0x014 <<1) | |
| 222 | #define XTxMAC_STAT_MSK mpeval(0x020 <<1) | |
| 223 | #define XRxMAC_STAT_MSK mpeval(0x024 <<1) | |
| 224 | #define xMAC_FLOW_STAT mpeval(0x018 <<1) | |
| 225 | #define xMAC_FLOW_STAT_MSK mpeval(0x028 <<1) | |
| 226 | #define IPP_0_RANGE 0x00000000 | |
| 227 | #define IPP_1_RANGE 0x00008000 /* 071405 #define IPP_1_RANGE 0x00001000 */ | |
| 228 | #define IPP_2_RANGE 0x00002000 | |
| 229 | #define IPP_3_RANGE 0x00003000 | |
| 230 | #define FZC_IPP_BASE_ADDRESS 0x280000 | |
| 231 | #define IPP_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_IPP_BASE_ADDRESS) | |
| 232 | #define IPP0_BASE mpeval(IPP_ADDRESS_RANGE + IPP_0_RANGE) | |
| 233 | #define IPP1_BASE mpeval(IPP_ADDRESS_RANGE + IPP_1_RANGE) | |
| 234 | #define IPP2_BASE mpeval(IPP_ADDRESS_RANGE + IPP_2_RANGE) | |
| 235 | #define IPP3_BASE mpeval(IPP_ADDRESS_RANGE + IPP_3_RANGE) | |
| 236 | ||
| 237 | #define IPP_CONFIG 0x000000000 | |
| 238 | #define PORT_RANGE_MASK 0x0000F000 | |
| 239 | #define PORT_OFFSET 0x00001000 | |
| 240 | #define PORT_0_RANGE 0x00000000 | |
| 241 | #define XPCS_0_RANGE mpeval(0x00001000 << 1) | |
| 242 | #define PCS_0_RANGE mpeval(0x00002000 << 1) | |
| 243 | #define PORT_1_RANGE mpeval(0x00003000 << 1) | |
| 244 | #define XPCS_1_RANGE mpeval(0x00004000 << 1) | |
| 245 | #define PCS_1_RANGE mpeval(0x00005000 << 1) | |
| 246 | #define PORT_2_RANGE mpeval(0x00006000 << 1) | |
| 247 | #define PCS_2_RANGE mpeval(0x00007000 << 1) | |
| 248 | #define PORT_3_RANGE mpeval(0x00008000 << 1) | |
| 249 | #define PCS_3_RANGE mpeval(0x00009000 << 1) | |
| 250 | #define ESER_RANGE mpeval(0x0000a000 << 1) | |
| 251 | #define MAC0_BASE mpeval(MAC_ADDRESS_RANGE + PORT_0_RANGE) | |
| 252 | #define MAC1_BASE mpeval(MAC_ADDRESS_RANGE + PORT_1_RANGE) | |
| 253 | #define MAC2_BASE mpeval(MAC_ADDRESS_RANGE + PORT_2_RANGE) | |
| 254 | #define MAC3_BASE mpeval(MAC_ADDRESS_RANGE + PORT_3_RANGE) | |
| 255 | ||
| 256 | #define XMAC_MAX mpeval(0x048 <<1) | |
| 257 | #define XMAC_CONFIG mpeval(0x030 <<1) | |
| 258 | #define xmac_config0 mpeval(MAC0_BASE + XMAC_CONFIG) | |
| 259 | #define xmac_config1 mpeval(MAC1_BASE + XMAC_CONFIG) | |
| 260 | #define XMAC0_MAX_addr mpeval(MAC0_BASE + XMAC_MAX) | |
| 261 | #define XMAC1_MAX_addr mpeval(MAC1_BASE + XMAC_MAX) | |
| 262 | #define XMAC0_MAX_data 0x00003fff | |
| 263 | #define XMAC1_MAX_data 0x00003fff | |
| 264 | #define xpcs0_config_vendor1 mpeval(XPCS0_BASE + XPCS_CONFIG_VENDOR1) | |
| 265 | #define xpcs1_config_vendor1 mpeval(XPCS1_BASE + XPCS_CONFIG_VENDOR1) | |
| 266 | #define fflp_reg0 mpeval(FFLP_ADDRESS_RANGE +FFLP_CONFIG) | |
| 267 | #define txc_reg0 mpeval(TXC_DMA0_BASE + TXC_DMA_MAXBURST) | |
| 268 | #define txc_reg1 mpeval(TXC_FZC_BASE+ TXC_PORT0_CONTROL) | |
| 269 | #define txc_reg2 mpeval(TXC_FZC_BASE+ TXC_PORT1_CONTROL) | |
| 270 | #define txc_reg3 mpeval(TXC_PIO_BASE + TXC_CONTROL) | |
| 271 | #define xtxmac_sw_rst0_addr mpeval(MAC0_BASE + XTxMAC_SW_RST) | |
| 272 | #define xrxmac_sw_rst0_addr mpeval(MAC0_BASE + XRxMAC_SW_RST) | |
| 273 | #define xtxmac_sw_rst1_addr mpeval(MAC1_BASE + XTxMAC_SW_RST) | |
| 274 | #define xrxmac_sw_rst1_addr mpeval(MAC1_BASE + XRxMAC_SW_RST) | |
| 275 | #define xtxmac_status0_addr mpeval(MAC0_BASE + XTxMAC_STATUS) | |
| 276 | #define xrxmac_status0_addr mpeval(MAC0_BASE + XRxMAC_STATUS) | |
| 277 | #define xtxmac_status1_addr mpeval(MAC1_BASE + XTxMAC_STATUS) | |
| 278 | #define xrxmac_status1_addr mpeval(MAC1_BASE + XRxMAC_STATUS) | |
| 279 | #define xtxmac_stat_msk0_addr mpeval(MAC0_BASE + XTxMAC_STAT_MSK) | |
| 280 | #define xrxmac_stat_msk0_addr mpeval(MAC0_BASE + XRxMAC_STAT_MSK) | |
| 281 | #define xtxmac_stat_msk1_addr mpeval(MAC1_BASE + XTxMAC_STAT_MSK) | |
| 282 | #define xrxmac_stat_msk1_addr mpeval(MAC1_BASE + XRxMAC_STAT_MSK) | |
| 283 | #define xmac_flow_stat0_addr mpeval(MAC0_BASE + xMAC_FLOW_STAT) | |
| 284 | #define xmac_flow_stat1_addr mpeval(MAC1_BASE + xMAC_FLOW_STAT) | |
| 285 | #define xmac_flow_msk0_addr mpeval(MAC0_BASE + xMAC_FLOW_STAT_MSK) | |
| 286 | #define xmac_flow_msk1_addr mpeval(MAC1_BASE + xMAC_FLOW_STAT_MSK) | |
| 287 | #define Time_out 0x10 | |
| 288 | #define delay_10_count 0x5 | |
| 289 | #define zcp_16_count 0x10 | |
| 290 | #define zcp_32_count 0x20 | |
| 291 | #define zcp_64_count 0x40 | |
| 292 | #define zcp_128_count 0x80 | |
| 293 | #define ipp_config0_addr mpeval(IPP0_BASE + IPP_CONFIG) | |
| 294 | #define ipp_config1_addr mpeval(IPP1_BASE + IPP_CONFIG) | |
| 295 | #define ipp_config_data 0x0000000001ffff11 /* 071405 0x0000000000000101 */ | |
| 296 | #define fflp_config_addr mpeval(FFLP_ADDRESS_RANGE +FFLP_CONFIG) | |
| 297 | #define fflp_config_data 0x0000000000043301 | |
| 298 | ||
| 299 | #define FFLP_L2_CLS_2 0x00000 | |
| 300 | #define FFLP_L2_CLS_3 0x00008 | |
| 301 | #define FFLP_L3_CLS_4 0x00010 | |
| 302 | #define FFLP_L3_CLS_5 0x00018 | |
| 303 | #define FFLP_L3_CLS_6 0x00020 | |
| 304 | #define FFLP_L3_CLS_7 0x00028 | |
| 305 | #define FFLP_CAM_KEY_REG0 0x00090 | |
| 306 | #define FFLP_CAM_KEY_REG1 0x00098 | |
| 307 | #define FFLP_CAM_KEY_REG2 0x000a0 | |
| 308 | #define FFLP_CAM_KEY_REG3 0x000a8 | |
| 309 | #define FFLP_CAM_KEY_MASK_REG0 0x000b0 | |
| 310 | #define FFLP_CAM_KEY_MASK_REG1 0x000b8 | |
| 311 | #define FFLP_CAM_KEY_MASK_REG2 0x000c0 | |
| 312 | #define FFLP_CAM_KEY_MASK_REG3 0x000c8 | |
| 313 | #define FFLP_CAM_CONTROL 0x000d0 | |
| 314 | ||
| 315 | #define xpcs0_control1_addr mpeval(XPCS0_BASE + XPCS_CONTROL1) | |
| 316 | #define xpcs1_control1_addr mpeval(XPCS1_BASE + XPCS_CONTROL1) | |
| 317 | #define xpcs0_control1_data 0x00008000 | |
| 318 | #define xpcs1_control1_data 0x00008000 | |
| 319 | #define fflp_l2_cls_2_addr mpeval(FFLP_ADDRESS_RANGE + FFLP_L2_CLS_2) | |
| 320 | #define fflp_l2_cls_3_addr mpeval(FFLP_ADDRESS_RANGE + FFLP_L2_CLS_3) | |
| 321 | #define fflp_l3_cls_4_start mpeval(FFLP_ADDRESS_RANGE + FFLP_L3_CLS_4) | |
| 322 | #define fflp_l3_cls_4_end mpeval(FFLP_ADDRESS_RANGE + FFLP_L3_CLS_7) | |
| 323 | #define fflp_cam_key_reg0_start mpeval(FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG0) | |
| 324 | #define fflp_cam_key_reg0_end mpeval(FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG3) | |
| 325 | #define fflp_cam_key_mask_reg0_start mpeval(FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG0) | |
| 326 | #define fflp_cam_key_mask_reg0_end mpeval(FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG3) | |
| 327 | #define fflp_cam_control_addr mpeval(FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL) | |
| 328 | #define fflp_cam_ram_data 0x100000 | |
| 329 | #define txc_dma_maxburst_addr mpeval(TXC_DMA0_BASE + TXC_DMA_MAXBURST) | |
| 330 | #define txc_dma_maxburst_data 0x00000000000005ea | |
| 331 | #define txc_port0_control_addr mpeval(TXC_FZC_BASE + TXC_PORT0_CONTROL) | |
| 332 | #define txc_port0_control_data 0x0000000000000001 | |
| 333 | #define txc_port1_control_addr mpeval(TXC_FZC_BASE + TXC_PORT1_CONTROL) | |
| 334 | #define txc_port1_control_data 0x0000000000000000 | |
| 335 | #define txc_control_addr mpeval(TXC_FZC_BASE + TXC_CONTROL) | |
| 336 | #define txc_control_data 0x1f | |
| 337 | ||
| 338 | #define RX_ADDR_MD_data 0x0000000000000001 | |
| 339 | #define RXDMA_CFIG_BASE_data 0x8000000000000001 | |
| 340 | #define RXDMA_CFIG1 mpeval(DMC_ADDRESS_RANGE+0x00000) | |
| 341 | #define RXDMA_CFIG1_data 0x0000000080000000 /* b31 DMA-EN */ | |
| 342 | #define RBR_CFIG_A_data 0x00FF000100000200 /* LEN FF , START ADDR 100000200 */ | |
| 343 | #define RBR_CFIG_B_data 0x0000000000808080 /* Set all 3 sizes S,M &L */ | |
| 344 | #define RX_LOG_PAGE_VLD_data 0x0000000000000003 /* Logical Page0&1 valid */ | |
| 345 | #define RBR_KICK_data 0x0000000000000128 /* KICK 8 buffers */ | |
| 346 | #define RBR_HDH mpeval(DMC_ADDRESS_RANGE + 0x00030) | |
| 347 | #define RBR_HDH_data 0x0000000000000200 | |
| 348 | #define RBR_HDL mpeval(DMC_ADDRESS_RANGE + 0x00038) | |
| 349 | #define RBR_HDL_data 0x0000000000000006 | |
| 350 | ||
| 351 | #define XMAC_ADDR_CMPEN_LSB mpeval( 0x104 <<1) | |
| 352 | #define XMAC_HOST_INFO0 mpeval( 0x480 <<1) | |
| 353 | #define XMAC_HOST_INFO1 mpeval( 0x484 <<1) | |
| 354 | #define XMAC_HOST_INFO2 mpeval( 0x488 <<1) | |
| 355 | #define XMAC_HOST_INFO3 mpeval( 0x48C <<1) | |
| 356 | #define XMAC_HOST_INFO4 mpeval( 0x490 <<1) | |
| 357 | #define XMAC_HOST_INFO5 mpeval( 0x494 <<1) | |
| 358 | #define XMAC_HOST_INFO6 mpeval( 0x498 <<1) | |
| 359 | #define XMAC_HOST_INFO7 mpeval( 0x49C <<1) | |
| 360 | #define XMAC_ADDR3 mpeval( 0x10C <<1) | |
| 361 | #define XMAC_ADDR4 mpeval( 0x110 <<1) | |
| 362 | #define XMAC_ADDR5 mpeval( 0x114 <<1) | |
| 363 | #define XMAC_ADDR6 mpeval( 0x118 <<1) | |
| 364 | #define XMAC_ADDR7 mpeval( 0x11C <<1) | |
| 365 | #define XMAC_ADDR8 mpeval( 0x120 <<1) | |
| 366 | #define XMAC_ADDR9 mpeval( 0x124 <<1) | |
| 367 | #define XMAC_ADDR10 mpeval( 0x128 <<1) | |
| 368 | #define XMAC_ADDR11 mpeval( 0x12C <<1) | |
| 369 | #define XMAC_ADDR12 mpeval( 0x130 <<1) | |
| 370 | #define XMAC_ADDR13 mpeval( 0x134 <<1) | |
| 371 | #define XMAC_ADDR14 mpeval( 0x138 <<1) | |
| 372 | #define XMAC_ADDR15 mpeval( 0x13C <<1) | |
| 373 | #define XMAC_ADDR16 mpeval( 0x140 <<1) | |
| 374 | #define XMAC_ADDR17 mpeval( 0x144 <<1) | |
| 375 | #define XMAC_ADDR18 mpeval( 0x148 <<1) | |
| 376 | #define XMAC_ADDR19 mpeval( 0x14C <<1) | |
| 377 | #define XMAC_ADDR20 mpeval( 0x150 <<1) | |
| 378 | #define XMAC_ADDR21 mpeval( 0x154 <<1) | |
| 379 | #define XMAC_ADDR22 mpeval( 0x158 <<1) | |
| 380 | #define XMAC_ADDR23 mpeval( 0x15C <<1) | |
| 381 | #define XMAC_ADDR24 mpeval( 0x160 <<1) | |
| 382 | #define XMAC_ADDR25 mpeval( 0x164 <<1) | |
| 383 | #define XMAC_ADDR26 mpeval( 0x168 <<1) | |
| 384 | #define XMAC_ADDR27 mpeval( 0x16C <<1) | |
| 385 | #define XMAC_ADDR28 mpeval( 0x170 <<1) | |
| 386 | #define XMAC_ADDR29 mpeval( 0x174 <<1) | |
| 387 | #define XMAC_ADDR30 mpeval( 0x178 <<1) | |
| 388 | #define XMAC_ADDR31 mpeval( 0x17C <<1) | |
| 389 | #define XMAC_ADDR32 mpeval( 0x180 <<1) | |
| 390 | #define XMAC_ADDR33 mpeval( 0x184 <<1) | |
| 391 | #define XMAC_ADDR34 mpeval( 0x188 <<1) | |
| 392 | #define XMAC_ADDR35 mpeval( 0x18C <<1) | |
| 393 | #define XMAC_ADDR36 mpeval( 0x190 <<1) | |
| 394 | #define XMAC_ADDR37 mpeval( 0x194 <<1) | |
| 395 | #define XMAC_ADDR38 mpeval( 0x198 <<1) | |
| 396 | #define XMAC_ADDR39 mpeval( 0x19C <<1) | |
| 397 | #define XMAC_ADDR40 mpeval( 0x1A0 <<1) | |
| 398 | #define XMAC_ADDR41 mpeval( 0x1A4 <<1) | |
| 399 | #define XMAC_ADDR42 mpeval( 0x1A8 <<1) | |
| 400 | #define XMAC_ADDR43 mpeval( 0x1AC <<1) | |
| 401 | #define XMAC_ADDR44 mpeval( 0x1B0 <<1) | |
| 402 | #define XMAC_ADDR45 mpeval( 0x1B4 <<1) | |
| 403 | #define XMAC_ADDR46 mpeval( 0x1B8 <<1) | |
| 404 | #define XMAC_ADDR47 mpeval( 0x1BC <<1) | |
| 405 | #define XMAC_ADDR48 mpeval( 0x1C0 <<1) | |
| 406 | #define XMAC_ADDR49 mpeval( 0x1C4 <<1) | |
| 407 | #define XMAC_ADDR50 mpeval( 0x1C8 <<1) | |
| 408 | ||
| 409 | ||
| 410 | ||
| 411 | #define XMAC_ADDR_CMPEN_LSB_data 0xFFFFFFFF | |
| 412 | #define XMAC_CONFIG_mask 0xFFFFF9FF | |
| 413 | #define XMAC_CONFIG_mask1 0x00010000 | |
| 414 | #define ctrl_word0 0x00000002 | |
| 415 | #define ctrl_word1 0x00000006 | |
| 416 | #define ctrl_word2 0x0000000A | |
| 417 | #define ctrl_word3 0x0000000E | |
| 418 | #define XMAC_ADDR3_data 0x0001 /* MAC-Address:Change the Address in Vera,if this changes */ | |
| 419 | #define XMAC_ADDR4_data 0xFFFF | |
| 420 | #define XMAC_ADDR5_data 0x0100 | |
| 421 | #define XMAC_ADDR6_data 0x0003 | |
| 422 | #define XMAC_ADDR7_data 0xFFFF | |
| 423 | #define XMAC_ADDR8_data 0x1111 | |
| 424 | #define XMAC_ADDR9_data 0x0005 | |
| 425 | #define XMAC_ADDR10_data 0xFFFF | |
| 426 | #define XMAC_ADDR11_data 0x2722 | |
| 427 | #define XMAC_ADDR12_data 0x0007 | |
| 428 | #define XMAC_ADDR13_data 0xFFFF | |
| 429 | #define XMAC_ADDR14_data 0x3333 | |
| 430 | ||
| 431 | #ifdef NIU_RX_MULTI_PORT | |
| 432 | #define mac0_ctrl_word0 0x00000000 | |
| 433 | #define mac0_ctrl_word1 0x00000002 | |
| 434 | #define mac0_ctrl_word2 0x00000004 | |
| 435 | #define mac0_ctrl_word3 0x00000006 | |
| 436 | #define mac0_ctrl_word4 0x00000000 | |
| 437 | #define mac0_ctrl_word5 0x00000002 | |
| 438 | #define mac0_ctrl_word6 0x00000004 | |
| 439 | #define mac0_ctrl_word7 0x00000006 | |
| 440 | ||
| 441 | #define mac1_ctrl_word0 0x00000001 | |
| 442 | #define mac1_ctrl_word1 0x00000003 | |
| 443 | #define mac1_ctrl_word2 0x00000005 | |
| 444 | #define mac1_ctrl_word3 0x00000007 | |
| 445 | #define mac1_ctrl_word4 0x00000001 | |
| 446 | #define mac1_ctrl_word5 0x00000003 | |
| 447 | #define mac1_ctrl_word6 0x00000005 | |
| 448 | #define mac1_ctrl_word7 0x00000007 | |
| 449 | #else | |
| 450 | #define mac0_ctrl_word0 0x00000000 | |
| 451 | #define mac0_ctrl_word1 0x00000001 | |
| 452 | #define mac0_ctrl_word2 0x00000002 | |
| 453 | #define mac0_ctrl_word3 0x00000003 | |
| 454 | #define mac0_ctrl_word4 0x00000004 | |
| 455 | #define mac0_ctrl_word5 0x00000005 | |
| 456 | #define mac0_ctrl_word6 0x00000006 | |
| 457 | #define mac0_ctrl_word7 0x00000007 | |
| 458 | ||
| 459 | #define mac1_ctrl_word0 0x00000007 | |
| 460 | #define mac1_ctrl_word1 0x00000006 | |
| 461 | #define mac1_ctrl_word2 0x00000005 | |
| 462 | #define mac1_ctrl_word3 0x00000004 | |
| 463 | #define mac1_ctrl_word4 0x00000003 | |
| 464 | #define mac1_ctrl_word5 0x00000002 | |
| 465 | #define mac1_ctrl_word6 0x00000001 | |
| 466 | #define mac1_ctrl_word7 0x00000000 | |
| 467 | #endif | |
| 468 | ||
| 469 | #define XMAC0_ADDR3_data 0xa000 /* MAC-Address:Change the Address in Vera,if this changes */ | |
| 470 | #define XMAC0_ADDR4_data 0x56a0 | |
| 471 | #define XMAC0_ADDR5_data 0x1234 | |
| 472 | ||
| 473 | #define XMAC0_ADDR6_data 0xa001 | |
| 474 | #define XMAC0_ADDR7_data 0x56a0 | |
| 475 | #define XMAC0_ADDR8_data 0x1234 | |
| 476 | ||
| 477 | #define XMAC0_ADDR9_data 0xa002 | |
| 478 | #define XMAC0_ADDR10_data 0x56a0 | |
| 479 | #define XMAC0_ADDR11_data 0x1234 | |
| 480 | ||
| 481 | #define XMAC0_ADDR12_data 0xa003 | |
| 482 | #define XMAC0_ADDR13_data 0x56a0 | |
| 483 | #define XMAC0_ADDR14_data 0x1234 | |
| 484 | ||
| 485 | #define XMAC0_ADDR15_data 0xa004 | |
| 486 | #define XMAC0_ADDR16_data 0x56a0 | |
| 487 | #define XMAC0_ADDR17_data 0x1234 | |
| 488 | ||
| 489 | #define XMAC0_ADDR18_data 0xa005 | |
| 490 | #define XMAC0_ADDR19_data 0x56a0 | |
| 491 | #define XMAC0_ADDR20_data 0x1234 | |
| 492 | ||
| 493 | #define XMAC0_ADDR21_data 0xa006 | |
| 494 | #define XMAC0_ADDR22_data 0x56a0 | |
| 495 | #define XMAC0_ADDR23_data 0x1234 | |
| 496 | ||
| 497 | #define XMAC0_ADDR24_data 0xa007 | |
| 498 | #define XMAC0_ADDR25_data 0x56a0 | |
| 499 | #define XMAC0_ADDR26_data 0x1234 | |
| 500 | ||
| 501 | #define XMAC1_ADDR3_data 0xb000 /* MAC-Address:Change the Address in Vera,if this changes */ | |
| 502 | #define XMAC1_ADDR4_data 0x56b0 | |
| 503 | #define XMAC1_ADDR5_data 0x1234 | |
| 504 | ||
| 505 | #define XMAC1_ADDR6_data 0xb001 | |
| 506 | #define XMAC1_ADDR7_data 0x56b0 | |
| 507 | #define XMAC1_ADDR8_data 0x1234 | |
| 508 | ||
| 509 | #define XMAC1_ADDR9_data 0xb002 | |
| 510 | #define XMAC1_ADDR10_data 0x56b0 | |
| 511 | #define XMAC1_ADDR11_data 0x1234 | |
| 512 | ||
| 513 | #define XMAC1_ADDR12_data 0xb003 | |
| 514 | #define XMAC1_ADDR13_data 0x56b0 | |
| 515 | #define XMAC1_ADDR14_data 0x1234 | |
| 516 | ||
| 517 | #define XMAC1_ADDR15_data 0xb004 | |
| 518 | #define XMAC1_ADDR16_data 0x56b0 | |
| 519 | #define XMAC1_ADDR17_data 0x1234 | |
| 520 | ||
| 521 | #define XMAC1_ADDR18_data 0xb005 | |
| 522 | #define XMAC1_ADDR19_data 0x56b0 | |
| 523 | #define XMAC1_ADDR20_data 0x1234 | |
| 524 | ||
| 525 | #define XMAC1_ADDR21_data 0xb006 | |
| 526 | #define XMAC1_ADDR22_data 0x56b0 | |
| 527 | #define XMAC1_ADDR23_data 0x1234 | |
| 528 | ||
| 529 | #define XMAC1_ADDR24_data 0xb007 | |
| 530 | #define XMAC1_ADDR25_data 0x56b0 | |
| 531 | #define XMAC1_ADDR26_data 0x1234 | |
| 532 | ||
| 533 | #define RCRCFIG_A_data 0x000F000000000040 | |
| 534 | #define TBR_CFIG_A_data mpeval(0x000F000000000080 + 0x100010000) | |
| 535 | #define RBR_HD_data 0x0000000000000200 | |
| 536 | #define RBR_TL_data 0x0000000000000006 | |
| 537 | ||
| 538 | #define TDMC_STEP 0x200 | |
| 539 | #define TDMC_COUNT 16 | |
| 540 | #define TX_RNG_CFIG mpeval(DMC_ADDRESS_RANGE+0x40000) | |
| 541 | #define TX_RING_KICK mpeval(DMC_ADDRESS_RANGE+0x40018) | |
| 542 | #define TX_CS mpeval(DMC_ADDRESS_RANGE+0x40028) | |
| 543 | #define TX_ENT_MSK mpeval(DMC_ADDRESS_RANGE+0x40020) | |
| 544 | #define TDMC_INTR_DBG mpeval(DMC_ADDRESS_RANGE+0x40060) | |
| 545 | ||
| 546 | #define TxRingConfig_data 0x000F000100000000 | |
| 547 | #define SetTxCs_data 0x00000000C0000000 | |
| 548 | #define Tx_Ring_Kick_data 0x0000000100000040 | |
| 549 | #ifndef loop_count | |
| 550 | #define loop_count 0x10 | |
| 551 | #endif | |
| 552 | #define Rx_loop_count 0x20 | |
| 553 | ||
| 554 | /* 04/25/05 ***/ | |
| 555 | #define TX_LOG_PAGE_VLD_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x40000) | |
| 556 | #define TX_LOG_MASK1_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x40008) | |
| 557 | #define TX_LOG_VALUE1_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x40010) | |
| 558 | #define TX_LOG_MASK2_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x40018) | |
| 559 | #define TX_LOG_VALUE2_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x40020) | |
| 560 | #define TX_LOG_PAGE_RELO1_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x40028) | |
| 561 | #define TX_LOG_PAGE_RELO2_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x40030) | |
| 562 | ||
| 563 | #define TX_RNG_CFIG_Addr mpeval(DMC_ADDRESS_RANGE+0x40000) | |
| 564 | #define TX_RING_KICK_Addr mpeval(DMC_ADDRESS_RANGE+0x40018) | |
| 565 | #define TX_CS_Addr mpeval(DMC_ADDRESS_RANGE+0x40028) | |
| 566 | #define TX_CS_Data 0x0 | |
| 567 | ||
| 568 | #define TXC_DMA0_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x00 << 12)) | |
| 569 | #define TXC_DMA1_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x01 << 12)) | |
| 570 | #define TXC_DMA2_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x02 << 12)) | |
| 571 | #define TXC_DMA3_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x03 << 12)) | |
| 572 | #define TXC_DMA4_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x04 << 12)) | |
| 573 | #define TXC_DMA5_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x05 << 12)) | |
| 574 | #define TXC_DMA6_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x06 << 12)) | |
| 575 | #define TXC_DMA7_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x07 << 12)) | |
| 576 | #define TXC_DMA8_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x08 << 12)) | |
| 577 | #define TXC_DMA9_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x09 << 12)) | |
| 578 | #define TXC_DMA10_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x0a << 12)) | |
| 579 | #define TXC_DMA11_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x0b << 12)) | |
| 580 | #define TXC_DMA12_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x0c << 12)) | |
| 581 | #define TXC_DMA13_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x0d << 12)) | |
| 582 | #define TXC_DMA14_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x0e << 12)) | |
| 583 | #define TXC_DMA15_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x0f << 12)) | |
| 584 | #define TXC_DMA16_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x10 << 12)) | |
| 585 | #define TXC_DMA17_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x11 << 12)) | |
| 586 | #define TXC_DMA18_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x12 << 12)) | |
| 587 | #define TXC_DMA19_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x13 << 12)) | |
| 588 | #define TXC_DMA20_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x14 << 12)) | |
| 589 | #define TXC_DMA21_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x15 << 12)) | |
| 590 | #define TXC_DMA22_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x16 << 12)) | |
| 591 | #define TXC_DMA23_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x17 << 12)) | |
| 592 | ||
| 593 | ||
| 594 | #define SetTxMaxBurst_DMA0_Addr mpeval(TXC_DMA0_BASE + TXC_DMA_MAXBURST) | |
| 595 | #define SetTxMaxBurst_DMA1_Addr mpeval(TXC_DMA1_BASE + TXC_DMA_MAXBURST) | |
| 596 | #define SetTxMaxBurst_DMA2_Addr mpeval(TXC_DMA2_BASE + TXC_DMA_MAXBURST) | |
| 597 | #define SetTxMaxBurst_DMA3_Addr mpeval(TXC_DMA3_BASE + TXC_DMA_MAXBURST) | |
| 598 | #define SetTxMaxBurst_DMA4_Addr mpeval(TXC_DMA4_BASE + TXC_DMA_MAXBURST) | |
| 599 | #define SetTxMaxBurst_DMA5_Addr mpeval(TXC_DMA5_BASE + TXC_DMA_MAXBURST) | |
| 600 | #define SetTxMaxBurst_DMA6_Addr mpeval(TXC_DMA6_BASE + TXC_DMA_MAXBURST) | |
| 601 | #define SetTxMaxBurst_DMA7_Addr mpeval(TXC_DMA7_BASE + TXC_DMA_MAXBURST) | |
| 602 | #define SetTxMaxBurst_DMA8_Addr mpeval(TXC_DMA8_BASE + TXC_DMA_MAXBURST) | |
| 603 | #define SetTxMaxBurst_DMA9_Addr mpeval(TXC_DMA9_BASE + TXC_DMA_MAXBURST) | |
| 604 | #define SetTxMaxBurst_DMA10_Addr mpeval(TXC_DMA10_BASE + TXC_DMA_MAXBURST) | |
| 605 | #define SetTxMaxBurst_DMA11_Addr mpeval(TXC_DMA11_BASE + TXC_DMA_MAXBURST) | |
| 606 | #define SetTxMaxBurst_DMA12_Addr mpeval(TXC_DMA12_BASE + TXC_DMA_MAXBURST) | |
| 607 | #define SetTxMaxBurst_DMA13_Addr mpeval(TXC_DMA13_BASE + TXC_DMA_MAXBURST) | |
| 608 | #define SetTxMaxBurst_DMA14_Addr mpeval(TXC_DMA14_BASE + TXC_DMA_MAXBURST) | |
| 609 | #define SetTxMaxBurst_DMA15_Addr mpeval(TXC_DMA15_BASE + TXC_DMA_MAXBURST) | |
| 610 | #define SetTxMaxBurst_DMA16_Addr mpeval(TXC_DMA16_BASE + TXC_DMA_MAXBURST) | |
| 611 | #define SetTxMaxBurst_DMA17_Addr mpeval(TXC_DMA17_BASE + TXC_DMA_MAXBURST) | |
| 612 | #define SetTxMaxBurst_DMA18_Addr mpeval(TXC_DMA18_BASE + TXC_DMA_MAXBURST) | |
| 613 | #define SetTxMaxBurst_DMA19_Addr mpeval(TXC_DMA19_BASE + TXC_DMA_MAXBURST) | |
| 614 | #define SetTxMaxBurst_DMA20_Addr mpeval(TXC_DMA20_BASE + TXC_DMA_MAXBURST) | |
| 615 | #define SetTxMaxBurst_DMA21_Addr mpeval(TXC_DMA21_BASE + TXC_DMA_MAXBURST) | |
| 616 | #define SetTxMaxBurst_DMA22_Addr mpeval(TXC_DMA22_BASE + TXC_DMA_MAXBURST) | |
| 617 | #define SetTxMaxBurst_DMA23_Addr mpeval(TXC_DMA23_BASE + TXC_DMA_MAXBURST) | |
| 618 | ||
| 619 | ||
| 620 | #define TXC_PKT_XMIT 0x038 | |
| 621 | #define TXC_PKT_XMIT_Addr mpeval(TXC_FZC_BASE + TXC_PKT_XMIT) | |
| 622 | #define TXC_PKT_XMIT_Mask 0xffff /* bit[15:0] */ | |
| 623 | ||
| 624 | #define port_offset 0 /* port_offset = 256*i; */ | |
| 625 | #define TXC_PORT0_DMA_ENBALE 0x028 | |
| 626 | #define TXC_PORT1_DMA_ENBALE 0x128 /* PORT1_DMA_list */ | |
| 627 | #define SetPort0TxDMAActive_Addr mpeval(TXC_FZC_BASE+ (TXC_PORT0_DMA_ENBALE + port_offset)) | |
| 628 | #define SetPort1TxDMAActive_Addr mpeval(TXC_FZC_BASE+ (TXC_PORT1_DMA_ENBALE + port_offset)) | |
| 629 | /* #define SetTxDMAActive_list 0x00ffffff For All Channels */ | |
| 630 | /* #define TxDmaActive_list 00ffffff For All Channels */ | |
| 631 | #define SetTxMaxBurst_Data 0x500 | |
| 632 | #define TxMaxBurst_Data 500 | |
| 633 | ||
| 634 | #define RX_LOG_MASK1_START_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x20008) | |
| 635 | #define RX_LOG_VAL1_START_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x20010) | |
| 636 | #define RX_LOG_MASK2_START_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x20018) | |
| 637 | #define RX_LOG_VAL2_START_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x20020) | |
| 638 | #define RX_LOG_RELO1_START_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x20028) | |
| 639 | #define RX_LOG_RELO2_START_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x20030) | |
| 640 | #define RBR_CFIG_A_Addr mpeval(DMC_ADDRESS_RANGE+0x00010) | |
| 641 | #define RBR_CFIG_B_Addr mpeval(DMC_ADDRESS_RANGE+0x00018) | |
| 642 | #define RXDMA_CFIG1_Addr mpeval(DMC_ADDRESS_RANGE+0x00000) | |
| 643 | #define RXDMA_CFIG2_Addr mpeval(DMC_ADDRESS_RANGE+0x00008) | |
| 644 | #define RXDMA_CFIG2_START_Addr mpeval(DMC_ADDRESS_RANGE+0x00008) | |
| 645 | #define RXDMA_CFIG1_START_Addr mpeval(DMC_ADDRESS_RANGE+0x00000) | |
| 646 | #define RXDMA_CFIG1_Addr mpeval(DMC_ADDRESS_RANGE+0x00000) | |
| 647 | #define RXDMA_CFIG2_Addr mpeval(DMC_ADDRESS_RANGE+0x00008) | |
| 648 | #define RBR_KICK_Addr mpeval(DMC_ADDRESS_RANGE+0x00020) | |
| 649 | #define ZCP_RDC_TBL_Addr mpeval(FZC_ZCP_ADDRESS_RANGE + 0x10000) | |
| 650 | #define RX_LOG_PAGE_VLD_Addr mpeval(FZC_DMC_ADDRESS_RANGE+0x20000) | |
| 651 | #define RCR_CFIG_A_Addr mpeval(DMC_ADDRESS_RANGE+0x00040) | |
| 652 | ||
| 653 | #define PCS0_BASE mpeval(MAC_ADDRESS_RANGE + PCS_0_RANGE) | |
| 654 | #define PCS1_BASE mpeval(MAC_ADDRESS_RANGE + PCS_1_RANGE) | |
| 655 | #define PCS_CONFIGURATION mpeval(0x010 << 1) | |
| 656 | #define PCS_DATAPATH_MODE mpeval(0x050 << 1) | |
| 657 | ||
| 658 | #define PCS0_CONFIGURATION_Addr mpeval(PCS0_BASE + PCS_CONFIGURATION) | |
| 659 | #define PCS0_DATAPATH_MODE_Addr mpeval(PCS0_BASE + PCS_DATAPATH_MODE) | |
| 660 | #define PCS1_CONFIGURATION_Addr mpeval(PCS1_BASE + PCS_CONFIGURATION) | |
| 661 | #define PCS1_DATAPATH_MODE_Addr mpeval(PCS1_BASE + PCS_DATAPATH_MODE) | |
| 662 | ||
| 663 | /* 04/25/05 ***/ | |
| 664 | ||
| 665 | #ifndef NIU_RX_PKT_LEN | |
| 666 | #define NIU_RX_PKT_LEN 60 /* 64B packet */ | |
| 667 | #endif | |
| 668 | ||
| 669 | #ifndef NIU_TX_PKT_LEN_P0 | |
| 670 | #define NIU_TX_PKT_LEN_P0 40 /* 64B packet */ | |
| 671 | #endif | |
| 672 | ||
| 673 | #ifndef NIU_TX_PKT_LEN_P1 | |
| 674 | #define NIU_TX_PKT_LEN_P1 64 /* 70B packet */ | |
| 675 | #endif | |
| 676 | ||
| 677 | #ifndef MAC_SPEED0 | |
| 678 | #define MAC_SPEED0 10000 /* Default to 10G speed for Port-0 */ | |
| 679 | #endif | |
| 680 | ||
| 681 | #ifndef MAC_SPEED1 | |
| 682 | #define MAC_SPEED1 10000 /* Default to 10G speed for Port-1 */ | |
| 683 | #endif | |
| 684 | ||
| 685 | #define mac_config_10000 0x01000701 | |
| 686 | #define mac_config_1000 0x6D000600 /* 0x6D800600 */ | |
| 687 | #define mac_config_1000_pcs_serdes 0x0D000600 /* 0x09000600 */ | |
| 688 | ||
| 689 | #ifdef MAC_ER_CK_EN | |
| 690 | #define data11 0x0 | |
| 691 | #else | |
| 692 | #define data11 0x800 /* data[11] = check_cmd(cmd, MAC_ER_CK_EN) ? 0 : 1; */ | |
| 693 | #endif | |
| 694 | ||
| 695 | #if (MAC_SPEED0==10000) | |
| 696 | #define mac0_config_data mpeval(mac_config_10000 | data11) | |
| 697 | #endif /* (MAC_SPEED0==10000) */ | |
| 698 | ||
| 699 | #if (MAC_SPEED0==1000) | |
| 700 | #ifdef PCS_SERDES | |
| 701 | #define mac0_config_data mpeval(mac_config_1000_pcs_serdes | data11) | |
| 702 | #else | |
| 703 | #define mac0_config_data mpeval(mac_config_1000 | data11) | |
| 704 | #endif | |
| 705 | #endif /* (MAC_SPEED0==1000) */ | |
| 706 | ||
| 707 | #if (MAC_SPEED1==10000) | |
| 708 | #define mac1_config_data mpeval(mac_config_10000 | data11) | |
| 709 | #endif /* (MAC_SPEED1==10000) */ | |
| 710 | ||
| 711 | #if (MAC_SPEED1==1000) | |
| 712 | #ifdef PCS_SERDES | |
| 713 | #define mac1_config_data mpeval(mac_config_1000_pcs_serdes | data11) | |
| 714 | #else | |
| 715 | #define mac1_config_data mpeval(mac_config_1000 | data11) | |
| 716 | #endif | |
| 717 | #endif /* (MAC_SPEED1==1000) */ | |
| 718 | ||
| 719 | #ifndef TX_PKT_LEN | |
| 720 | #define TX_PKT_LEN 34 /* Default to 64Bytes */ | |
| 721 | #endif | |
| 722 | ||
| 723 | #ifndef HTRAP_NIU_TX_PKT_LEN | |
| 724 | #define HTRAP_NIU_TX_PKT_LEN 34 /* Packet_len for ISR : Default to 64Bytes */ | |
| 725 | #endif | |
| 726 | ||
| 727 | #ifndef HTRAP_NIU_TX_PKT_CNT | |
| 728 | #define HTRAP_NIU_TX_PKT_CNT 0x10 /* Packet Count for IST : Default to 16 packets; */ | |
| 729 | #endif | |
| 730 | ||
| 731 | #ifndef NIU_TX_PKT_CNT | |
| 732 | #define NIU_TX_PKT_CNT 0x10 /* Default to 16 packets; in IOS (random() % 16); */ | |
| 733 | #endif | |
| 734 | ||
| 735 | /* #ifdef TX_PKT_SIZE_SWEEP */ | |
| 736 | #ifndef TX_PKT_INCR | |
| 737 | #define TX_PKT_INCR 0 /* Byte increment = 0 */ | |
| 738 | #endif | |
| 739 | /* #endif */ | |
| 740 | ||
| 741 | #ifndef NO_OF_TX_DMA | |
| 742 | #define NO_OF_TX_DMA 1 /* Default to 1 DMA channel only */ | |
| 743 | #endif | |
| 744 | ||
| 745 | #ifdef DESC_START_ADDR | |
| 746 | #define DESC_START_ADDR 0x400000 /* Need to update with Random within the range */ | |
| 747 | #endif | |
| 748 | ||
| 749 | #ifndef TXQ_RNG_BUFFSZ | |
| 750 | #define TXQ_RNG_BUFFSZ 0xf /* Default to 16 */ | |
| 751 | #endif | |
| 752 | ||
| 753 | #ifndef TX_KICK_INTERVAL | |
| 754 | #define TX_KICK_INTERVAL TX_PKT_CNT /* Kick after last packet */ | |
| 755 | #endif | |
| 756 | ||
| 757 | #ifndef MAC_ID | |
| 758 | #define MAC_ID 0 /* Default to MAC_ID = 0 */ | |
| 759 | #endif | |
| 760 | ||
| 761 | #ifndef HTRAP_NIU_MAC_PKT_LEN | |
| 762 | #define HTRAP_NIU_MAC_PKT_LEN 0x40 /* Packet Length for ISR : Default packet size = 64 */ | |
| 763 | #endif | |
| 764 | ||
| 765 | #ifndef MAC_PKT_LEN | |
| 766 | #define MAC_PKT_LEN 0x40 /* Default packet size = 64 */ | |
| 767 | #endif | |
| 768 | ||
| 769 | #ifndef HTRAP_NIU_RXMAC_PKTCNT | |
| 770 | #define HTRAP_NIU_RXMAC_PKTCNT 0x1 /* Packet count for ISR : default no. of Packets to receive = 1 */ | |
| 771 | #endif | |
| 772 | ||
| 773 | #ifndef RXMAC_PKTCNT | |
| 774 | #define RXMAC_PKTCNT 0x1 /* default no. of Packets to receive = 1 */ | |
| 775 | #endif | |
| 776 | ||
| 777 | #ifndef RXDMA_CHNL | |
| 778 | #define RXDMA_CHNL 0x0 | |
| 779 | #endif | |
| 780 | ||
| 781 | ||
| 782 | #ifndef RX_BLKSZ | |
| 783 | #define RX_BLKSZ 32 /* lowest value = 4 */ | |
| 784 | #endif | |
| 785 | ||
| 786 | #ifndef RX_BUF_SIZ0 | |
| 787 | #define RX_BUF_SIZ0 2048 /* lowest value = 256 */ | |
| 788 | #endif | |
| 789 | ||
| 790 | #ifndef RX_BUF_SIZ1 | |
| 791 | #define RX_BUF_SIZ1 8192 /* lowest value = 1024 */ | |
| 792 | #endif | |
| 793 | ||
| 794 | #ifndef RX_BUF_SIZ2 | |
| 795 | #define RX_BUF_SIZ2 16384 /* lowest value = 2048 */ | |
| 796 | #endif | |
| 797 | ||
| 798 | #ifndef VLD0 | |
| 799 | #define VLD0 1 | |
| 800 | #endif | |
| 801 | ||
| 802 | #ifndef VLD1 | |
| 803 | #define VLD1 1 | |
| 804 | #endif | |
| 805 | ||
| 806 | #ifndef VLD2 | |
| 807 | #define VLD2 1 | |
| 808 | #endif | |
| 809 | ||
| 810 | #if (RX_BLKSZ==4) | |
| 811 | #define rbr_config_B_data_25_24 0x0 | |
| 812 | #endif | |
| 813 | ||
| 814 | #if (RX_BLKSZ==8) | |
| 815 | #define rbr_config_B_data_25_24 0x1000000 | |
| 816 | #endif | |
| 817 | ||
| 818 | #if (RX_BLKSZ==16) | |
| 819 | #define rbr_config_B_data_25_24 0x2000000 | |
| 820 | #endif | |
| 821 | ||
| 822 | #if (RX_BLKSZ==32) | |
| 823 | #define rbr_config_B_data_25_24 0x3000000 | |
| 824 | #endif | |
| 825 | ||
| 826 | #if (RX_BUF_SIZ2==2048) | |
| 827 | #define rbr_config_B_data_17_16 0x0 | |
| 828 | #endif | |
| 829 | ||
| 830 | #if (RX_BUF_SIZ2==4096) | |
| 831 | #define rbr_config_B_data_17_16 0x10000 | |
| 832 | #endif | |
| 833 | ||
| 834 | #if (RX_BUF_SIZ2==8192) | |
| 835 | #define rbr_config_B_data_17_16 0x20000 | |
| 836 | #endif | |
| 837 | ||
| 838 | #if (RX_BUF_SIZ2==16384) | |
| 839 | #define rbr_config_B_data_17_16 0x30000 | |
| 840 | #endif | |
| 841 | ||
| 842 | #if (RX_BUF_SIZ1==1024) | |
| 843 | #define rbr_config_B_data_9_8 0x0 | |
| 844 | #endif | |
| 845 | ||
| 846 | #if (RX_BUF_SIZ1==2048) | |
| 847 | #define rbr_config_B_data_9_8 0x100 | |
| 848 | #endif | |
| 849 | ||
| 850 | #if (RX_BUF_SIZ1==4096) | |
| 851 | #define rbr_config_B_data_9_8 0x200 | |
| 852 | #endif | |
| 853 | ||
| 854 | #if (RX_BUF_SIZ1==8192) | |
| 855 | #define rbr_config_B_data_9_8 0x300 | |
| 856 | #endif | |
| 857 | ||
| 858 | #if (RX_BUF_SIZ0==256) | |
| 859 | #define rbr_config_B_data_1_0 0x0 | |
| 860 | #endif | |
| 861 | ||
| 862 | #if (RX_BUF_SIZ0==512) | |
| 863 | #define rbr_config_B_data_1_0 0x1 | |
| 864 | #endif | |
| 865 | ||
| 866 | #if (RX_BUF_SIZ0==1024) | |
| 867 | #define rbr_config_B_data_1_0 0x2 | |
| 868 | #endif | |
| 869 | ||
| 870 | #if (RX_BUF_SIZ0==2048) | |
| 871 | #define rbr_config_B_data_1_0 0x3 | |
| 872 | #endif | |
| 873 | ||
| 874 | #define RBR_CONFIG_B_DATA mpeval( rbr_config_B_data_25_24 + \ | |
| 875 | (VLD2 << 23) + \ | |
| 876 | rbr_config_B_data_17_16 + \ | |
| 877 | (VLD1 << 15) + \ | |
| 878 | rbr_config_B_data_9_8 + \ | |
| 879 | (VLD0 << 7) + \ | |
| 880 | rbr_config_B_data_1_0 , 16) | |
| 881 | #ifndef RBR_CONFIG_B_DATA_UE | |
| 882 | #define RBR_CONFIG_B_DATA_UE 80 | |
| 883 | #endif | |
| 884 | ||
| 885 | #ifndef RX_COMPL_RING_LEN | |
| 886 | #define RX_COMPL_RING_LEN 0x2000 | |
| 887 | #endif | |
| 888 | ||
| 889 | #ifndef RX_RING_START_ADDRESS | |
| 890 | #define RX_RING_START_ADDRESS 0x0 | |
| 891 | #endif | |
| 892 | ||
| 893 | #ifndef RX_INITIAL_KICK | |
| 894 | #define RX_INITIAL_KICK 0xff | |
| 895 | #endif | |
| 896 | ||
| 897 | #ifndef RX_DESC_RING_LENGTH | |
| 898 | #define RX_DESC_RING_LENGTH 0x1fff | |
| 899 | #endif | |
| 900 | ||
| 901 | #ifndef RX_NIU_MULTI_DMA | |
| 902 | #define RX_NIU_MULTI_DMA 0 | |
| 903 | #endif | |
| 904 | ||
| 905 | #ifndef TX_NIU_MULTI_DMA | |
| 906 | #define TX_NIU_MULTI_DMA 0x0 | |
| 907 | #endif | |
| 908 | ||
| 909 | #ifndef NIU_TX_DMA_NUM | |
| 910 | #define NIU_TX_DMA_NUM 0 | |
| 911 | #endif | |
| 912 | ||
| 913 | #define NIU_TxDmaNo NIU_TX_DMA_NUM | |
| 914 | ||
| 915 | #ifndef NIU_TX_DMA_ACT_LIST | |
| 916 | #define NIU_TX_DMA_ACT_LIST 1 | |
| 917 | #endif | |
| 918 | ||
| 919 | #define SetTxDMAActive_list NIU_TX_DMA_ACT_LIST | |
| 920 | ||
| 921 | #if (NIU_TX_DMA_NUM==0) | |
| 922 | #define NIU_TxDmaNoUE 0 | |
| 923 | #define TxDmaActive_list 1 | |
| 924 | #endif | |
| 925 | ||
| 926 | #if (NIU_TX_DMA_NUM==1) | |
| 927 | #define NIU_TxDmaNoUE 1 | |
| 928 | #define TxDmaActive_list 2 | |
| 929 | #endif | |
| 930 | ||
| 931 | #if (NIU_TX_DMA_NUM==2) | |
| 932 | #define NIU_TxDmaNoUE 2 | |
| 933 | #define TxDmaActive_list 4 | |
| 934 | #endif | |
| 935 | ||
| 936 | #if (NIU_TX_DMA_NUM==3) | |
| 937 | #define NIU_TxDmaNoUE 3 | |
| 938 | #define TxDmaActive_list 8 | |
| 939 | #endif | |
| 940 | ||
| 941 | #if (NIU_TX_DMA_NUM==4) | |
| 942 | #define NIU_TxDmaNoUE 4 | |
| 943 | #define TxDmaActive_list 10 | |
| 944 | #endif | |
| 945 | ||
| 946 | #if (NIU_TX_DMA_NUM==5) | |
| 947 | #define NIU_TxDmaNoUE 5 | |
| 948 | #define TxDmaActive_list 20 | |
| 949 | #endif | |
| 950 | ||
| 951 | #if (NIU_TX_DMA_NUM==6) | |
| 952 | #define NIU_TxDmaNoUE 6 | |
| 953 | #define TxDmaActive_list 40 | |
| 954 | #endif | |
| 955 | ||
| 956 | #if (NIU_TX_DMA_NUM==7) | |
| 957 | #define NIU_TxDmaNoUE 7 | |
| 958 | #define TxDmaActive_list 80 | |
| 959 | #endif | |
| 960 | ||
| 961 | #if (NIU_TX_DMA_NUM==8) | |
| 962 | #define NIU_TxDmaNoUE 8 | |
| 963 | #define TxDmaActive_list 100 | |
| 964 | #endif | |
| 965 | ||
| 966 | #if (NIU_TX_DMA_NUM==9) | |
| 967 | #define NIU_TxDmaNoUE 9 | |
| 968 | #define TxDmaActive_list 200 | |
| 969 | #endif | |
| 970 | ||
| 971 | #if (NIU_TX_DMA_NUM==10) | |
| 972 | #define NIU_TxDmaNoUE a | |
| 973 | #define TxDmaActive_list 400 | |
| 974 | #endif | |
| 975 | ||
| 976 | #if (NIU_TX_DMA_NUM==11) | |
| 977 | #define NIU_TxDmaNoUE b | |
| 978 | #define TxDmaActive_list 800 | |
| 979 | #endif | |
| 980 | ||
| 981 | #if (NIU_TX_DMA_NUM==12) | |
| 982 | #define NIU_TxDmaNoUE c | |
| 983 | #define TxDmaActive_list 1000 | |
| 984 | #endif | |
| 985 | ||
| 986 | #if (NIU_TX_DMA_NUM==13) | |
| 987 | #define NIU_TxDmaNoUE d | |
| 988 | #define TxDmaActive_list 2000 | |
| 989 | #endif | |
| 990 | ||
| 991 | #if (NIU_TX_DMA_NUM==14) | |
| 992 | #define NIU_TxDmaNoUE e | |
| 993 | #define TxDmaActive_list 4000 | |
| 994 | #endif | |
| 995 | ||
| 996 | #if (NIU_TX_DMA_NUM==15) | |
| 997 | #define NIU_TxDmaNoUE f | |
| 998 | #define TxDmaActive_list 8000 | |
| 999 | #endif | |
| 1000 | ||
| 1001 | #if (NIU_TX_DMA_NUM==16) | |
| 1002 | #define NIU_TxDmaNoUE 10 | |
| 1003 | #define TxDmaActive_list 10000 | |
| 1004 | #endif | |
| 1005 | ||
| 1006 | #if (NIU_TX_DMA_NUM==17) | |
| 1007 | #define NIU_TxDmaNoUE 11 | |
| 1008 | #define TxDmaActive_list 20000 | |
| 1009 | #endif | |
| 1010 | ||
| 1011 | #if (NIU_TX_DMA_NUM==18) | |
| 1012 | #define NIU_TxDmaNoUE 12 | |
| 1013 | #define TxDmaActive_list 40000 | |
| 1014 | #endif | |
| 1015 | ||
| 1016 | #if (NIU_TX_DMA_NUM==19) | |
| 1017 | #define NIU_TxDmaNoUE 13 | |
| 1018 | #define TxDmaActive_list 80000 | |
| 1019 | #endif | |
| 1020 | ||
| 1021 | #if (NIU_TX_DMA_NUM==20) | |
| 1022 | #define NIU_TxDmaNoUE 14 | |
| 1023 | #define TxDmaActive_list 100000 | |
| 1024 | #endif | |
| 1025 | ||
| 1026 | #if (NIU_TX_DMA_NUM==21) | |
| 1027 | #define NIU_TxDmaNoUE 15 | |
| 1028 | #define TxDmaActive_list 200000 | |
| 1029 | #endif | |
| 1030 | ||
| 1031 | #if (NIU_TX_DMA_NUM==22) | |
| 1032 | #define NIU_TxDmaNoUE 16 | |
| 1033 | #define TxDmaActive_list 400000 | |
| 1034 | #endif | |
| 1035 | ||
| 1036 | #if (NIU_TX_DMA_NUM==23) | |
| 1037 | #define NIU_TxDmaNoUE 17 | |
| 1038 | #define TxDmaActive_list 800000 | |
| 1039 | #endif | |
| 1040 | ||
| 1041 | ||
| 1042 | /* ------------------------------------------------------- */ | |
| 1043 | /* NIU Tx Packet Types */ | |
| 1044 | /* ------------------------------------------------------- */ | |
| 1045 | #define DELTA 0x13 | |
| 1046 | ||
| 1047 | #define CL_IP 0x7 | |
| 1048 | #define CL_UDP 0xd | |
| 1049 | #define CL_TCP 0x10 | |
| 1050 | #define CL_IP_V6 0x1a /* mpeval(DELTA + CL_IP) */ | |
| 1051 | #define CL_UDP_IP_V6 0x20 /* mpeval(DELTA + CL_UDP) */ | |
| 1052 | #define CL_TCP_IP_V6 0x23 /* mpeval(DELTA + CL_TCP) */ | |
| 1053 | ||
| 1054 | ||
| 1055 | #ifndef VLAN | |
| 1056 | #define VLAN 0 | |
| 1057 | #endif | |
| 1058 | ||
| 1059 | #ifndef LLC | |
| 1060 | #define LLC 0 | |
| 1061 | #endif | |
| 1062 | ||
| 1063 | #ifndef IP_VER | |
| 1064 | #define IP_VER 4 | |
| 1065 | #endif | |
| 1066 | ||
| 1067 | #ifndef UDP | |
| 1068 | #define UDP 0 | |
| 1069 | #endif | |
| 1070 | ||
| 1071 | #ifndef TCP | |
| 1072 | #define TCP 0 | |
| 1073 | #endif | |
| 1074 | ||
| 1075 | #ifndef IP | |
| 1076 | #define IP 1 | |
| 1077 | #endif | |
| 1078 | ||
| 1079 | #if (IP_VER == 4) | |
| 1080 | #if (LLC == 0) && (VLAN == 0) | |
| 1081 | #define FRAME_TYPE 0x2 | |
| 1082 | #endif | |
| 1083 | ||
| 1084 | #if (LLC == 0) && (VLAN == 1) | |
| 1085 | #define FRAME_TYPE 0x6 | |
| 1086 | #endif | |
| 1087 | ||
| 1088 | #if (LLC == 1) && (VLAN == 0) | |
| 1089 | #define FRAME_TYPE 0x3 | |
| 1090 | #endif | |
| 1091 | ||
| 1092 | #if (LLC == 1) && (VLAN == 1) | |
| 1093 | #define FRAME_TYPE 0x7 | |
| 1094 | #endif | |
| 1095 | ||
| 1096 | #if (IP == 1) | |
| 1097 | #define FRAME_CLASS CL_IP | |
| 1098 | #endif | |
| 1099 | ||
| 1100 | #if (UDP == 1) | |
| 1101 | #define FRAME_CLASS CL_UDP | |
| 1102 | #endif | |
| 1103 | ||
| 1104 | #if (TCP == 1) | |
| 1105 | #define FRAME_CLASS CL_TCP | |
| 1106 | #endif | |
| 1107 | ||
| 1108 | #else /* IP_VER == 6 */ | |
| 1109 | ||
| 1110 | #if (LLC == 0) && (VLAN == 0) | |
| 1111 | #define FRAME_TYPE 0xa | |
| 1112 | #endif | |
| 1113 | ||
| 1114 | #if (LLC == 0) && (VLAN == 1) | |
| 1115 | #define FRAME_TYPE 0xe | |
| 1116 | #endif | |
| 1117 | ||
| 1118 | #if (LLC == 1) && (VLAN == 0) | |
| 1119 | #define FRAME_TYPE 0xb | |
| 1120 | #endif | |
| 1121 | ||
| 1122 | #if (LLC == 1) && (VLAN == 1) | |
| 1123 | #define FRAME_TYPE 0xf | |
| 1124 | #endif | |
| 1125 | ||
| 1126 | #if (IP == 1) | |
| 1127 | #define FRAME_CLASS CL_IP_V6 | |
| 1128 | #endif | |
| 1129 | ||
| 1130 | #if (UDP == 1) | |
| 1131 | #define FRAME_CLASS CL_UDP_IP_V6 | |
| 1132 | #endif | |
| 1133 | ||
| 1134 | #if (TCP == 1) | |
| 1135 | #define FRAME_CLASS CL_TCP_IP_V6 | |
| 1136 | #endif | |
| 1137 | ||
| 1138 | #endif | |
| 1139 | ||
| 1140 | /* ------------------------------------------------------- */ | |
| 1141 | ||
| 1142 | #ifdef XLATE_ON | |
| 1143 | #define NIU_Xlate_On 1 | |
| 1144 | #else | |
| 1145 | #define NIU_Xlate_On 0 | |
| 1146 | #endif | |
| 1147 | ||
| 1148 | /* ------------------------------------------------------- */ | |
| 1149 | ||
| 1150 | #include "../../../env/fc/vera/include/niu_pktgen_csr_ev2a.vrh" |