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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / niu_init.h
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niu_init.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38.global N2_NIU_INIT
39N2_NIU_INIT:
40NIU_INIT_START:
41 save
42
43 ! IMPORTANT
44 ! ---------
45 ! Initialize the NIU Packet generator from Vera.
46 ! Some of the initialization routines are
47 ! packet_db_init();
48 ! flow_db_init();
49 ! node_db_init();
50
51#ifdef MAC_REG_TEST
52#else
53
54 set 0x1, %o2
55 set 0x3, %o3
56 best_set_reg(0x6000, %l7, %o4)
57 best_set_reg(0x1000901, %l7, %o5)
58mac_util_xmii_init_tmp:
59! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.mac_util_xmii_init_tmp) - 4, 16, 16)) -> printf("Initializing mac_util_xmii_init_tmp",*,1)
60 setx xtxmac_sw_rst0_addr, %l7, %l0
61 brgz %o2, mac_reset
62 nop
63 or %l0, %o4, %l0
64mac_reset:
65 stxa %o3, [%l0]ASI_PRIMARY_LITTLE
66 add %l0, 0x8, %l0
67 stxa %o3, [%l0]ASI_PRIMARY_LITTLE
68 xor %l0, 0x68, %l0
69 stxa %o5, [%l0]ASI_PRIMARY_LITTLE
70 subcc %o2, 1, %o2
71 be mac_util_xmii_init_tmp
72 nop
73#endif
74#ifdef JUMBO_FRAME_EN
75 setx XMAC0_MAX_addr, %l7, %l0
76 setx XMAC0_MAX_data, %l7, %l1
77 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
78
79 setx XMAC1_MAX_addr, %l7, %l0
80 setx XMAC1_MAX_data, %l7, %l1
81 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
82#endif
83
84xpcs_init:
85#if (MAC_SPEED0==1000) && (MAC_SPEED1==1000)
86 setx xpcs0_config_vendor1, %l7, %l0
87 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
88
89 setx xpcs1_config_vendor1, %l7, %l0
90 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
91#else /*Default to 10G */
92! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.xpcs_init) + 8, 16, 16)) -> printf("Initializing xpcs_init for 10G Speed",*,1)
93 setx xpcs0_control1_addr, %l7, %l0
94 setx xpcs0_control1_data, %l7, %l1
95 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
96 add %l0, %l2, %l0
97 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
98#endif /* (MAC_SPEED0==1000) && (MAC_SPEED1==1000) */
99
100/* This section only applicable to 1G not 10
101 mov %g0, %o2
102 call pcs_util_pcs_init
103 nop
104
105 set 0x1, %o2
106 call pcs_util_pcs_init
107 nop
108
109*/
110
111
112/* Program ipp config register and enable the ipp0 & ipp1 */
113ipp_init:
114! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.ipp_init) + 8, 16, 16)) -> printf("Initializing ipp_init",*,1)
115 setx ipp_config0_addr, %l7, %l0
116 setx ipp_config_data, %l7, %l3
117 stxa %l3, [%l0]ASI_PRIMARY_LITTLE
118 best_set_reg(0x8000, %l1, %l2)
119 or %l0, %l2, %l0
120 stxa %l3, [%l0]ASI_PRIMARY_LITTLE
121
122#ifdef FFLP_TEST
123 call fflp_util_fflp_init
124 nop
125#endif
126
127txc_init:
128! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.txc_init) + 8, 16, 16)) -> printf("Initializing txc_init",*,1)
129 setx txc_dma_maxburst_addr, %l7, %l0
130 best_set_reg(txc_dma_maxburst_data, %l7, %l1)
131 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
132
133 setx txc_port0_control_addr, %l7, %l0
134 best_set_reg(txc_port0_control_data, %l7, %l1)
135 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
136 add %l0, 0x100, %l0
137 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
138
139 setx txc_control_addr, %l7, %l0
140 best_set_reg(txc_control_data, %l7, %l1)
141 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
142
143
144#ifdef RX_TEST
145#ifdef MULTI_TEST
146! This portion programs MAC_DA addresses and MAC control words
147! for supporting multi-port/multi-dma in the environment:
148! - 8 MAC_DA addresses and 8 MAC Control word info. relative
149! to each MAC_DA address for port 0. The MAC_DA addresses
150! and the mMAC control words are defined in niu_defines.h.
151! - 8 MAC_DA addresses and 8 MAC Control word info. relative
152! to each MAC_DA address for port 1. The MAC_DA addresses
153! and the mMAC control words are defined in niu_defines.h.
154! - If no MULTI_TEST, then the programming falls back to the
155! single port/single dma testing.
156
157 mov %g0, %o2
158 call xmac_host_config
159 nop
160
161 setx XMAC0_ADDR3_data, %o1, %o3
162 setx XMAC0_ADDR4_data, %o1, %o4
163 setx XMAC0_ADDR5_data, %o1, %o5
164 call mac_base_wr3
165 nop
166
167 setx XMAC0_ADDR6_data, %o1, %o3
168 setx XMAC0_ADDR7_data, %o1, %o4
169 setx XMAC0_ADDR8_data, %o1, %o5
170 call mac_base_wr6
171 nop
172
173 setx XMAC0_ADDR9_data, %o1, %o3
174 setx XMAC0_ADDR10_data, %o1, %o4
175 setx XMAC0_ADDR11_data, %o1, %o5
176 call mac_base_wr9
177 nop
178
179 setx XMAC0_ADDR12_data, %o1, %o3
180 setx XMAC0_ADDR13_data, %o1, %o4
181 setx XMAC0_ADDR14_data, %o1, %o5
182 call mac_base_wr12
183 nop
184
185 setx XMAC0_ADDR15_data, %o1, %o3
186 setx XMAC0_ADDR16_data, %o1, %o4
187 setx XMAC0_ADDR17_data, %o1, %o5
188 call mac_base_wr15
189 nop
190
191 setx XMAC0_ADDR18_data, %o1, %o3
192 setx XMAC0_ADDR19_data, %o1, %o4
193 setx XMAC0_ADDR20_data, %o1, %o5
194 call mac_base_wr18
195 nop
196
197 setx XMAC0_ADDR21_data, %o1, %o3
198 setx XMAC0_ADDR22_data, %o1, %o4
199 setx XMAC0_ADDR23_data, %o1, %o5
200 call mac_base_wr21
201 nop
202
203 setx XMAC0_ADDR24_data, %o1, %o3
204 setx XMAC0_ADDR25_data, %o1, %o4
205 setx XMAC0_ADDR26_data, %o1, %o5
206 call mac_base_wr24
207 nop
208
209 set 0x1, %o2
210 call xmac_host_config /* MAQ : Port-1 configured */
211 nop
212
213 setx XMAC1_ADDR3_data, %o1, %o3
214 setx XMAC1_ADDR4_data, %o1, %o4
215 setx XMAC1_ADDR5_data, %o1, %o5
216 call mac_base_wr3
217 nop
218
219 setx XMAC1_ADDR6_data, %o1, %o3
220 setx XMAC1_ADDR7_data, %o1, %o4
221 setx XMAC1_ADDR8_data, %o1, %o5
222 call mac_base_wr6
223 nop
224
225 setx XMAC1_ADDR9_data, %o1, %o3
226 setx XMAC1_ADDR10_data, %o1, %o4
227 setx XMAC1_ADDR11_data, %o1, %o5
228 call mac_base_wr9
229 nop
230
231 setx XMAC1_ADDR12_data, %o1, %o3
232 setx XMAC1_ADDR13_data, %o1, %o4
233 setx XMAC1_ADDR14_data, %o1, %o5
234 call mac_base_wr12
235 nop
236
237 setx XMAC1_ADDR15_data, %o1, %o3
238 setx XMAC1_ADDR16_data, %o1, %o4
239 setx XMAC1_ADDR17_data, %o1, %o5
240 call mac_base_wr15
241 nop
242
243 setx XMAC1_ADDR18_data, %o1, %o3
244 setx XMAC1_ADDR19_data, %o1, %o4
245 setx XMAC1_ADDR20_data, %o1, %o5
246 call mac_base_wr18
247 nop
248
249 setx XMAC1_ADDR21_data, %o1, %o3
250 setx XMAC1_ADDR22_data, %o1, %o4
251 setx XMAC1_ADDR23_data, %o1, %o5
252 call mac_base_wr21
253 nop
254
255 setx XMAC1_ADDR24_data, %o1, %o3
256 setx XMAC1_ADDR25_data, %o1, %o4
257 setx XMAC1_ADDR26_data, %o1, %o5
258 call mac_base_wr24
259 nop
260#else
261
262 mov %g0, %o2
263 call xmac_config
264 nop
265
266 best_set_reg(XMAC_ADDR3_data, %o1, %o3)
267 best_set_reg(XMAC_ADDR4_data, %o1, %o4)
268 best_set_reg(XMAC_ADDR5_data, %o1, %o5)
269 call mac_base_wr3
270 nop
271
272 best_set_reg(XMAC_ADDR6_data, %o1, %o3)
273 best_set_reg(XMAC_ADDR7_data, %o1, %o4)
274 best_set_reg(XMAC_ADDR8_data, %o1, %o5)
275 call mac_base_wr6
276 nop
277
278 best_set_reg(XMAC_ADDR9_data, %o1, %o3)
279 best_set_reg(XMAC_ADDR10_data, %o1, %o4)
280 best_set_reg(XMAC_ADDR11_data, %o1, %o5)
281 call mac_base_wr9
282 nop
283
284 best_set_reg(XMAC_ADDR12_data, %o1, %o3)
285 best_set_reg(XMAC_ADDR13_data, %o1, %o4)
286 best_set_reg(XMAC_ADDR14_data, %o1, %o5)
287 call mac_base_wr12
288 nop
289
290 set 0x1, %o2
291 call xmac_config /* MAQ : Port-1 configured */
292 nop
293
294 best_set_reg(XMAC_ADDR3_data, %o1, %o3)
295 best_set_reg(XMAC_ADDR4_data, %o1, %o4)
296 best_set_reg(XMAC_ADDR5_data, %o1, %o5)
297 call mac_base_wr3
298 nop
299
300 best_set_reg(XMAC_ADDR6_data, %o1, %o3)
301 best_set_reg(XMAC_ADDR7_data, %o1, %o4)
302 best_set_reg(XMAC_ADDR8_data, %o1, %o5)
303 call mac_base_wr6
304 nop
305
306 best_set_reg(XMAC_ADDR9_data, %o1, %o3)
307 best_set_reg(XMAC_ADDR10_data, %o1, %o4)
308 best_set_reg(XMAC_ADDR11_data, %o1, %o5)
309 call mac_base_wr9
310 nop
311
312 best_set_reg(XMAC_ADDR12_data, %o1, %o3)
313 best_set_reg(XMAC_ADDR13_data, %o1, %o4)
314 best_set_reg(XMAC_ADDR14_data, %o1, %o5)
315 call mac_base_wr12
316 nop
317#endif
318#endif
319 ret
320 restore ! Return to Main program
321
322NIU_INIT_END:
323
324!/********************************************************************************
325!* mac_util_xmii_init:
326!* Reset the MAC(s) and program all other MAC registers such as config. registers
327!* Parameters in registers:
328!* %o2: <=0 for Port 0, >0 for Port 1
329!********************************************************************************/
330mac_util_xmii_init:
331 save
332! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.mac_util_xmii_init) + 8, 16, 16)) -> printf("Initializing mac_util_xmii_init",*,1)
333 brgz %i2, xtx_mac_reset1
334 nop
335 setx xtxmac_sw_rst0_addr, %l7, %l0
336 ba xtx_mac_reset_d
337 nop
338xtx_mac_reset1:
339 setx xtxmac_sw_rst1_addr, %l7, %l0
340xtx_mac_reset_d:
341 setx 0x03, %l7, %l1
342 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
343
344 call delay_1
345 nop
346
347 brgz %i2, xrx_mac_reset1
348 nop
349 setx xrxmac_sw_rst0_addr, %l7, %l0
350 ba xrx_mac_reset_d
351 nop
352xrx_mac_reset1:
353 setx xrxmac_sw_rst1_addr, %l7, %l0
354xrx_mac_reset_d:
355 setx 0x03, %l7, %l1
356 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
357 call delay_1
358 nop
359
360 mov %i2, %o2
361 call tx_mac_reset
362 nop
363 mov %i2, %o2
364 call rx_mac_reset
365 nop
366
367 brgz %i2, mac_port_1
368 nop
369mac_port_0:
370 setx mac0_config_data, %l7, %l0
371 setx xmac_config0, %l7, %l1
372 stxa %l0, [%l1]ASI_PRIMARY_LITTLE
373 ba mac_port_config_done
374 nop
375mac_port_1:
376 setx mac1_config_data, %l7, %l0
377 setx xmac_config1, %l7, %l1
378 stxa %l0, [%l1]ASI_PRIMARY_LITTLE
379mac_port_config_done:
380 mov %i2, %o2
381 call tx_mac_reset
382 nop
383 mov %i2, %o2
384 call rx_mac_reset
385 nop
386
387 brgz %i2, mac1_port
388 nop
389mac0_port:
390 setx xmac_config0, %l7, %l0
391 ldxa [%l0]ASI_PRIMARY_LITTLE, %l1
392 or 0x00000101, %l1, %l1
393 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
394 ba mac_port_done
395 nop
396mac1_port:
397 setx xmac_config1, %l7, %l0
398 ldxa [%l0]ASI_PRIMARY_LITTLE, %l1
399 or 0x00000101, %l1, %l1
400 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
401mac_port_done:
402 mov %i2, %o2
403 call tx_mac_reset
404 nop
405 mov %i2, %o2
406 call rx_mac_reset
407 nop
408
409#ifdef JUMBO_FRAME_EN
410 setx XMAC0_MAX_addr, %l7, %l0
411 setx XMAC0_MAX_data, %l7, %l1
412 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
413 setx XMAC1_MAX_addr, %l7, %l0
414 setx XMAC1_MAX_data, %l7, %l1
415 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
416#endif
417 ret
418 restore
419
420!/********************************************************************************
421!* xpcs_util_xpcs_init:
422!* Initialize both ports of XPCS to desired speed (usually 10G)
423!* Parameters in registers:
424!* None
425!********************************************************************************/
426xpcs_util_xpcs_init:
427 save
428#if (MAC_SPEED0==1000) && (MAC_SPEED1==1000)
429 setx xpcs0_config_vendor1, %l7, %l0
430 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
431
432 setx xpcs1_config_vendor1, %l7, %l0
433 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
434#else
435! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.xpcs_util_xpcs_init) + 8, 16, 16)) -> printf("Initializing xpcs_util_xpcs_init for 10G Speed",*,1)
436 setx xpcs0_control1_addr, %l7, %l0
437 setx xpcs0_control1_data, %l7, %l1
438 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
439 setx Time_out, %l7, %l6
440xpcs0_loop:
441 ldxa [%l0]ASI_PRIMARY_LITTLE, %l4
442 setx 0x8000, %l7, %l5
443 and %l5, %l4, %l4
444 brz %l4, xpcs0_done
445 nop
446 dec %l6
447 brnz %l6, xpcs0_loop
448 nop
449 call Timeout
450 nop
451xpcs0_done:
452 setx xpcs1_control1_addr, %l7, %l0
453 setx xpcs1_control1_data, %l7, %l1
454 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
455 setx Time_out, %l7, %l6
456xpcs1_loop:
457 ldxa [%l0]ASI_PRIMARY_LITTLE, %l4
458 setx 0x8000, %l7, %l5
459 and %l5, %l4, %l4
460 brz %l4, xpcs1_done
461 nop
462 dec %l6
463 brnz %l6, xpcs1_loop
464 nop
465 call Timeout
466 nop
467xpcs1_done:
468#endif /* (MAC_SPEED0==1000) && (MAC_SPEED1==1000) */
469 ret
470 restore
471
472!/********************************************************************************
473!* pcs_util_pcs_init:
474!* Bringing up pcs0 and pcs1 with 1G speed
475!* Parameters in registers:
476!* %o2: <=0 for Port 0, >0 for Port 1
477!********************************************************************************/
478pcs_util_pcs_init:
479#if (MAC_SPEED0==1000) && (MAC_SPEED1==1000)
480
481 save
482 brgz %i2, pcs_init_mac1
483 nop
484pcs_init_mac0:
485 setx PCS0_CONFIGURATION_Addr, %l7, %l0
486 setx PCS0_DATAPATH_MODE_Addr, %l7, %l2
487 ba pcs_init_mac
488 nop
489pcs_init_mac1:
490 setx PCS1_CONFIGURATION_Addr, %l7, %l0
491 setx PCS1_DATAPATH_MODE_Addr, %l7, %l2
492
493pcs_init_mac:
494#ifdef PCS_SERDES
495 set 0x23, %l1
496 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
497 stxa %g0, [%l2]ASI_PRIMARY_LITTLE
498#else
499 set 0x2, %l1
500 stxa %l1, [%l2]ASI_PRIMARY_LITTLE
501#endif
502 ret
503 restore
504#endif /* (MAC_SPEED0==1000) && (MAC_SPEED1==1000) */
505
506!/********************************************************************************
507!* ipp_util_ipp_init:
508!* Programming ipp config register and enabling the ipp0 & ipp1
509!* Parameters in registers:
510!* %o2: <=0 for Port 0, >0 for Port 1
511!********************************************************************************/
512ipp_util_ipp_init:
513 save
514! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.ipp_util_ipp_init) + 8, 16, 16)) -> printf("Initializing ipp_util_ipp_init",*,1)
515 brgz %i2, ipp_config1
516 nop
517 setx ipp_config0_addr, %l7, %l0
518 ba ipp_config_d
519 nop
520ipp_config1:
521 setx ipp_config1_addr, %l7, %l0
522ipp_config_d:
523 setx ipp_config_data, %l7, %l1
524 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
525 ret
526 restore
527
528!/********************************************************************************
529!* fflp_util_fflp_init:
530!* This is a mini version of programming FFLP block in NIU.
531!* Config register, couple of class and cam_key entries are programmed.
532!* Parameters in registers:
533!* None
534!********************************************************************************/
535fflp_util_fflp_init:
536 save
537! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.fflp_util_fflp_init) + 8, 16, 16)) -> printf("Initializing fflp_util_fflp_init",*,1)
538Lable_FFLP_CONFIG:
539 setx fflp_config_addr, %l7, %l0
540 setx fflp_config_data, %l7, %l1
541 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
542Lable_FFLP_L2_CLS_2:
543 setx fflp_l2_cls_2_addr, %l7, %l0
544 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
545Lable_FFLP_L2_CLS_3:
546 setx fflp_l2_cls_3_addr, %l7, %l0
547 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
548FFLP_L3_class4_7:
549 setx fflp_l3_cls_4_start, %l7, %l0
550 setx fflp_l3_cls_4_end, %l7, %l1
551fflp_loop0:
552 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
553 add %l0, 0x8, %l0
554 cmp %l0, %l1
555 bne fflp_loop0
556 nop
557FFLP_CAM_KEY_0_3:
558 setx fflp_cam_key_reg0_start, %l7, %l0
559 setx fflp_cam_key_reg0_end, %l7, %l1
560fflp_loop1:
561 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
562 add %l0, 0x8, %l0
563 cmp %l0, %l1
564 bne fflp_loop1
565 nop
566FFLP_CAM_KEY_MASK_0_3:
567 setx fflp_cam_key_mask_reg0_start, %l7, %l0
568 setx fflp_cam_key_mask_reg0_end, %l7, %l1
569fflp_loop2:
570 stxa %g0, [%l0]ASI_PRIMARY_LITTLE
571 add %l0, 0x8, %l0
572 cmp %l0, %l1
573 bne fflp_loop2
574 nop
575FFLP_CAM_128_entry:
576 setx fflp_cam_control_addr, %l7, %l0
577 mov %g0, %l1
578fflp_loop4:
579 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
580 inc %l1
581 cmp %l1, 127
582 bne fflp_loop4
583 nop
584FFLP_CAM_RAM_128_entry:
585 setx fflp_cam_ram_data, %l7, %l1
586 mov %g0, %l2
587fflp_loop5:
588 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
589 inc %l2
590 cmp %l2, 127
591 bne fflp_loop5
592 nop
593 ret
594 restore
595
596!/********************************************************************************
597!* txc_util_txc_init:
598!* Program txc max. burst per port registers.
599!* Parameters in registers:
600!* None
601!********************************************************************************/
602txc_util_txc_init:
603 save
604! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.txc_util_txc_init) + 8, 16, 16)) -> printf("Initializing txc_util_txc_init",*,1)
605 setx txc_dma_maxburst_addr, %l7, %l0
606 setx txc_dma_maxburst_data, %l7, %l1
607 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
608
609 setx txc_port0_control_addr, %l7, %l0
610 setx txc_port0_control_data, %l7, %l1
611 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
612
613 setx txc_port1_control_addr, %l7, %l0
614 setx txc_port1_control_data, %l7, %l1
615 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
616
617 setx txc_control_addr, %l7, %l0
618 setx txc_control_data, %l7, %l1
619 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
620
621 ret
622 restore
623
624
625!/********************************************************************************
626!* dmc_util_dmc_init:
627!* Program RDMC config and Ring Buffer and kick registers.
628!* Parameters in registers:
629!* None
630!********************************************************************************/
631dmc_util_dmc_init:
632 save
633! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.dmc_util_dmc_init) + 8, 16, 16)) -> printf("Initializing dmc_util_dmc_init",*,1)
634 setx RXDMA_CFIG1, %l7, %l0
635 setx RXDMA_CFIG1_data, %l7, %l1
636 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
637
638 setx RBR_CFIG_A, %l7, %l0
639 setx RBR_CFIG_A_data, %l7, %l1
640 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
641
642 setx RBR_CFIG_B, %l7, %l0
643 setx RBR_CFIG_B_data, %l7, %l1
644 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
645
646 setx RX_LOG_PAGE_VLD, %l7, %l0
647 setx RX_LOG_PAGE_VLD_data, %l7, %l1
648 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
649
650 setx RBR_KICK, %l7, %l0
651 setx RBR_KICK_data, %l7, %l1
652 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
653
654 setx RBR_HDH, %l7, %l0
655 setx RBR_HDH_data, %l7, %l1
656 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
657
658 setx RBR_HDL, %l7, %l0
659 setx RBR_HDL_data, %l7, %l1
660 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
661
662 ret
663 restore
664
665
666!/********************************************************************************
667!* xmac_config:
668!* Program MAC host register for the existing tests (before
669!* multi port implementation).
670!* Parameters in registers:
671!* %o2: <=0 for Port 0, >0 for Port 1
672!********************************************************************************/
673xmac_config:
674 save
675 brgz %i2, xmac_config_1
676 nop
677 setx MAC0_BASE, %l1, %l2
678 ba xmac_config_final
679 nop
680xmac_config_1:
681 setx MAC1_BASE, %l1, %l2
682xmac_config_final:
683 setx XMAC_CONFIG, %l1, %l3
684 add %l2, %l3, %l3
685 ldxa [%l3]ASI_PRIMARY_LITTLE, %l4
686 setx XMAC_CONFIG_mask, %l1, %l5
687 and %l4, %l5, %l5
688 stxa %l5, [%l3]ASI_PRIMARY_LITTLE
689
690 ldxa [%l3]ASI_PRIMARY_LITTLE, %l4
691 setx XMAC_CONFIG_mask1, %l1, %l5
692 or %l4, %l5, %l5
693 stxa %l5, [%l3]ASI_PRIMARY_LITTLE
694
695 setx XMAC_ADDR_CMPEN_LSB, %l1, %l3
696 add %l2, %l3, %l3
697 setx XMAC_ADDR_CMPEN_LSB_data, %l1, %l4
698 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
699
700 setx XMAC_HOST_INFO0, %l1, %l3
701 add %l2, %l3, %l3
702 setx ctrl_word0, %l1, %l4
703 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
704
705 setx XMAC_HOST_INFO1, %l1, %l3
706 add %l2, %l3, %l3
707 setx ctrl_word1, %l1, %l4
708 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
709
710 setx XMAC_HOST_INFO2, %l1, %l3
711 add %l2, %l3, %l3
712 setx ctrl_word2, %l1, %l4
713 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
714
715 setx XMAC_HOST_INFO3, %l1, %l3
716 add %l2, %l3, %l3
717 setx ctrl_word3, %l1, %l4
718 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
719
720 ret
721 restore
722
723
724!/********************************************************************************
725!* xmac_host_config:
726!* Program MAC host (mac control word) registers for MAC0
727!* and MAC1 for single-port/multi-dma and multi-port/multi-dma.
728!* Parameters in registers:
729!* %o2: <=0 for Port 0, >0 for Port 1
730!********************************************************************************/
731xmac_host_config:
732 save
733 brgz %i2, xmac_host_config_1
734 nop
735 setx MAC0_BASE, %l1, %l2
736 ba xmac0_host_config
737 nop
738xmac_host_config_1:
739 setx MAC1_BASE, %l1, %l2
740xmac1_host_config:
741 setx XMAC_CONFIG, %l1, %l3
742 add %l2, %l3, %l3
743 ldxa [%l3]ASI_PRIMARY_LITTLE, %l4
744 setx XMAC_CONFIG_mask, %l1, %l5
745 and %l4, %l5, %l5
746 stxa %l5, [%l3]ASI_PRIMARY_LITTLE
747
748 ldxa [%l3]ASI_PRIMARY_LITTLE, %l4
749 setx XMAC_CONFIG_mask1, %l1, %l5
750 or %l4, %l5, %l5
751 stxa %l5, [%l3]ASI_PRIMARY_LITTLE
752
753 setx XMAC_ADDR_CMPEN_LSB, %l1, %l3
754 add %l2, %l3, %l3
755 setx XMAC_ADDR_CMPEN_LSB_data, %l1, %l4
756 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
757
758 setx XMAC_HOST_INFO0, %l1, %l3
759 add %l2, %l3, %l3
760 setx mac1_ctrl_word0, %l1, %l4
761 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
762
763 setx XMAC_HOST_INFO1, %l1, %l3
764 add %l2, %l3, %l3
765 setx mac1_ctrl_word1, %l1, %l4
766 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
767
768 setx XMAC_HOST_INFO2, %l1, %l3
769 add %l2, %l3, %l3
770 setx mac1_ctrl_word2, %l1, %l4
771 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
772
773 setx XMAC_HOST_INFO3, %l1, %l3
774 add %l2, %l3, %l3
775 setx mac1_ctrl_word3, %l1, %l4
776 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
777
778 setx XMAC_HOST_INFO4, %l1, %l3
779 add %l2, %l3, %l3
780 setx mac1_ctrl_word4, %l1, %l4
781 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
782
783 setx XMAC_HOST_INFO5, %l1, %l3
784 add %l2, %l3, %l3
785 setx mac1_ctrl_word5, %l1, %l4
786 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
787
788 setx XMAC_HOST_INFO6, %l1, %l3
789 add %l2, %l3, %l3
790 setx mac1_ctrl_word6, %l1, %l4
791 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
792
793 setx XMAC_HOST_INFO7, %l1, %l3
794 add %l2, %l3, %l3
795 setx mac1_ctrl_word7, %l1, %l4
796 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
797
798 ret
799 restore
800xmac0_host_config:
801 setx XMAC_CONFIG, %l1, %l3
802 add %l2, %l3, %l3
803 ldxa [%l3]ASI_PRIMARY_LITTLE, %l4
804 setx XMAC_CONFIG_mask, %l1, %l5
805 and %l4, %l5, %l5
806 stxa %l5, [%l3]ASI_PRIMARY_LITTLE
807
808 ldxa [%l3]ASI_PRIMARY_LITTLE, %l4
809 setx XMAC_CONFIG_mask1, %l1, %l5
810 or %l4, %l5, %l5
811 stxa %l5, [%l3]ASI_PRIMARY_LITTLE
812
813 setx XMAC_ADDR_CMPEN_LSB, %l1, %l3
814 add %l2, %l3, %l3
815 setx XMAC_ADDR_CMPEN_LSB_data, %l1, %l4
816 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
817
818 setx XMAC_HOST_INFO0, %l1, %l3
819 add %l2, %l3, %l3
820 setx mac0_ctrl_word0, %l1, %l4
821 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
822
823 setx XMAC_HOST_INFO1, %l1, %l3
824 add %l2, %l3, %l3
825 setx mac0_ctrl_word1, %l1, %l4
826 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
827
828 setx XMAC_HOST_INFO2, %l1, %l3
829 add %l2, %l3, %l3
830 setx mac0_ctrl_word2, %l1, %l4
831 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
832
833 setx XMAC_HOST_INFO3, %l1, %l3
834 add %l2, %l3, %l3
835 setx mac0_ctrl_word3, %l1, %l4
836 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
837
838 setx XMAC_HOST_INFO4, %l1, %l3
839 add %l2, %l3, %l3
840 setx mac0_ctrl_word4, %l1, %l4
841 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
842
843 setx XMAC_HOST_INFO5, %l1, %l3
844 add %l2, %l3, %l3
845 setx mac0_ctrl_word5, %l1, %l4
846 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
847
848 setx XMAC_HOST_INFO6, %l1, %l3
849 add %l2, %l3, %l3
850 setx mac0_ctrl_word6, %l1, %l4
851 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
852
853 setx XMAC_HOST_INFO7, %l1, %l3
854 add %l2, %l3, %l3
855 setx mac0_ctrl_word7, %l1, %l4
856 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
857
858 ret
859 restore
860
861!/********************************************************************************
862!* mac_base_wr3:
863!* ???
864!* Parameters in registers:
865!* %o2: <=0 for Port 0, >0 for Port 1
866!* %o3: Value to write to XMAC_ADDR3
867!* %o4: Value to write to XMAC_ADDR4
868!* %o5: Value to write to XMAC_ADDR3
869!********************************************************************************/
870mac_base_wr3:
871 save
872 brgz %i2, mac1_base_wr3
873 nop
874 setx MAC0_BASE, %l1, %l2
875 setx XMAC_ADDR3, %l1, %l3
876 add %l2, %l3, %l3
877 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
878
879 setx XMAC_ADDR4, %l1, %l3
880 add %l2, %l3, %l3
881 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
882
883 setx XMAC_ADDR5, %l1, %l3
884 add %l2, %l3, %l3
885 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
886
887 ba mac_base_wr3_done
888 nop
889mac1_base_wr3:
890 setx MAC1_BASE, %l1, %l2
891 setx XMAC_ADDR3, %l1, %l3
892 add %l2, %l3, %l3
893 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
894
895 setx XMAC_ADDR4, %l1, %l3
896 add %l2, %l3, %l3
897 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
898
899 setx XMAC_ADDR5, %l1, %l3
900 add %l2, %l3, %l3
901 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
902
903mac_base_wr3_done:
904 ret
905 restore
906
907!/********************************************************************************
908!* mac_base_wr6:
909!* ???
910!* Parameters in registers:
911!* %o2: <=0 for Port 0, >0 for Port 1
912!* %o3: Value to write to XMAC_ADDR6
913!* %o4: Value to write to XMAC_ADDR7
914!* %o5: Value to write to XMAC_ADDR8
915!********************************************************************************/
916mac_base_wr6:
917 save
918 brgz %i2, mac1_base_wr6
919 nop
920 setx MAC0_BASE, %l1, %l2
921 setx XMAC_ADDR6, %l1, %l3
922 add %l2, %l3, %l3
923 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
924
925 setx XMAC_ADDR7, %l1, %l3
926 add %l2, %l3, %l3
927 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
928
929 setx XMAC_ADDR8, %l1, %l3
930 add %l2, %l3, %l3
931 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
932
933 ba mac_base_wr6_done
934 nop
935mac1_base_wr6:
936 setx MAC1_BASE, %l1, %l2
937 setx XMAC_ADDR6, %l1, %l3
938 add %l2, %l3, %l3
939 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
940
941 setx XMAC_ADDR7, %l1, %l3
942 add %l2, %l3, %l3
943 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
944
945 setx XMAC_ADDR8, %l1, %l3
946 add %l2, %l3, %l3
947 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
948
949mac_base_wr6_done:
950 ret
951 restore
952
953!/********************************************************************************
954!* mac_base_wr9:
955!* ???
956!* Parameters in registers:
957!* %o2: <=0 for Port 0, >0 for Port 1
958!* %o3: Value to write to XMAC_ADDR9
959!* %o4: Value to write to XMAC_ADDR10
960!* %o5: Value to write to XMAC_ADDR11
961!********************************************************************************/
962mac_base_wr9:
963 save
964 brgz %i2, mac1_base_wr9
965 nop
966 setx MAC0_BASE, %l1, %l2
967 setx XMAC_ADDR9, %l1, %l3
968 add %l2, %l3, %l3
969 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
970
971 setx XMAC_ADDR10, %l1, %l3
972 add %l2, %l3, %l3
973 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
974
975 setx XMAC_ADDR11, %l1, %l3
976 add %l2, %l3, %l3
977 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
978
979 ba mac_base_wr9_done
980 nop
981mac1_base_wr9:
982 setx MAC1_BASE, %l1, %l2
983 setx XMAC_ADDR9, %l1, %l3
984 add %l2, %l3, %l3
985 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
986
987 setx XMAC_ADDR10, %l1, %l3
988 add %l2, %l3, %l3
989 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
990
991 setx XMAC_ADDR11, %l1, %l3
992 add %l2, %l3, %l3
993 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
994
995mac_base_wr9_done:
996 ret
997 restore
998
999!/********************************************************************************
1000!* mac_base_wr12:
1001!* ???
1002!* Parameters in registers:
1003!* %o2: <=0 for Port 0, >0 for Port 1
1004!* %o3: Value to write to XMAC_ADDR12
1005!* %o4: Value to write to XMAC_ADDR13
1006!* %o5: Value to write to XMAC_ADDR14
1007!********************************************************************************/
1008mac_base_wr12:
1009 save
1010 brgz %i2, mac1_base_wr12
1011 nop
1012 setx MAC0_BASE, %l1, %l2
1013 setx XMAC_ADDR12, %l1, %l3
1014 add %l2, %l3, %l3
1015 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1016
1017 setx XMAC_ADDR13, %l1, %l3
1018 add %l2, %l3, %l3
1019 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1020
1021 setx XMAC_ADDR14, %l1, %l3
1022 add %l2, %l3, %l3
1023 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1024
1025 ba mac_base_wr12_done
1026 nop
1027mac1_base_wr12:
1028 setx MAC1_BASE, %l1, %l2
1029 setx XMAC_ADDR12, %l1, %l3
1030 add %l2, %l3, %l3
1031 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1032
1033 setx XMAC_ADDR13, %l1, %l3
1034 add %l2, %l3, %l3
1035 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1036
1037 setx XMAC_ADDR14, %l1, %l3
1038 add %l2, %l3, %l3
1039 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1040
1041mac_base_wr12_done:
1042 ret
1043 restore
1044
1045!/********************************************************************************
1046!* mac_base_wr15:
1047!* ???
1048!* Parameters in registers:
1049!* %o2: <=0 for Port 0, >0 for Port 1
1050!* %o3: Value to write to XMAC_ADDR15
1051!* %o4: Value to write to XMAC_ADDR16
1052!* %o5: Value to write to XMAC_ADDR17
1053!********************************************************************************/
1054mac_base_wr15:
1055 save
1056 brgz %i2, mac1_base_wr15
1057 nop
1058 setx MAC0_BASE, %l1, %l2
1059 setx XMAC_ADDR15, %l1, %l3
1060 add %l2, %l3, %l3
1061 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1062
1063 setx XMAC_ADDR16, %l1, %l3
1064 add %l2, %l3, %l3
1065 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1066
1067 setx XMAC_ADDR17, %l1, %l3
1068 add %l2, %l3, %l3
1069 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1070
1071 ba mac_base_wr15_done
1072 nop
1073mac1_base_wr15:
1074 setx MAC1_BASE, %l1, %l2
1075 setx XMAC_ADDR15, %l1, %l3
1076 add %l2, %l3, %l3
1077 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1078
1079 setx XMAC_ADDR16, %l1, %l3
1080 add %l2, %l3, %l3
1081 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1082
1083 setx XMAC_ADDR17, %l1, %l3
1084 add %l2, %l3, %l3
1085 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1086
1087mac_base_wr15_done:
1088 ret
1089 restore
1090
1091!/********************************************************************************
1092!* mac_base_wr18:
1093!* ???
1094!* Parameters in registers:
1095!* %o2: <=0 for Port 0, >0 for Port 1
1096!* %o3: Value to write to XMAC_ADDR18
1097!* %o4: Value to write to XMAC_ADDR19
1098!* %o5: Value to write to XMAC_ADDR20
1099!********************************************************************************/
1100mac_base_wr18:
1101 save
1102 brgz %i2, mac1_base_wr18
1103 nop
1104 setx MAC0_BASE, %l1, %l2
1105 setx XMAC_ADDR18, %l1, %l3
1106 add %l2, %l3, %l3
1107 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1108
1109 setx XMAC_ADDR19, %l1, %l3
1110 add %l2, %l3, %l3
1111 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1112
1113 setx XMAC_ADDR20, %l1, %l3
1114 add %l2, %l3, %l3
1115 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1116
1117 ba mac_base_wr18_done
1118 nop
1119mac1_base_wr18:
1120 setx MAC1_BASE, %l1, %l2
1121 setx XMAC_ADDR18, %l1, %l3
1122 add %l2, %l3, %l3
1123 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1124
1125 setx XMAC_ADDR19, %l1, %l3
1126 add %l2, %l3, %l3
1127 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1128
1129 setx XMAC_ADDR20, %l1, %l3
1130 add %l2, %l3, %l3
1131 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1132
1133mac_base_wr18_done:
1134 ret
1135 restore
1136
1137!/********************************************************************************
1138!* mac_base_wr21:
1139!* ???
1140!* Parameters in registers:
1141!* %o2: <=0 for Port 0, >0 for Port 1
1142!* %o3: Value to write to XMAC_ADDR21
1143!* %o4: Value to write to XMAC_ADDR22
1144!* %o5: Value to write to XMAC_ADDR23
1145!********************************************************************************/
1146mac_base_wr21:
1147 save
1148 brgz %i2, mac1_base_wr21
1149 nop
1150 setx MAC0_BASE, %l1, %l2
1151 setx XMAC_ADDR21, %l1, %l3
1152 add %l2, %l3, %l3
1153 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1154
1155 setx XMAC_ADDR22, %l1, %l3
1156 add %l2, %l3, %l3
1157 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1158
1159 setx XMAC_ADDR23, %l1, %l3
1160 add %l2, %l3, %l3
1161 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1162
1163 ba mac_base_wr21_done
1164 nop
1165mac1_base_wr21:
1166 setx MAC1_BASE, %l1, %l2
1167 setx XMAC_ADDR21, %l1, %l3
1168 add %l2, %l3, %l3
1169 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1170
1171 setx XMAC_ADDR22, %l1, %l3
1172 add %l2, %l3, %l3
1173 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1174
1175 setx XMAC_ADDR23, %l1, %l3
1176 add %l2, %l3, %l3
1177 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1178
1179mac_base_wr21_done:
1180 ret
1181 restore
1182
1183!/********************************************************************************
1184!* mac_base_wr24:
1185!* ???
1186!* Parameters in registers:
1187!* %o2: <=0 for Port 0, >0 for Port 1
1188!* %o3: Value to write to XMAC_ADDR24
1189!* %o4: Value to write to XMAC_ADDR25
1190!* %o5: Value to write to XMAC_ADDR26
1191!********************************************************************************/
1192mac_base_wr24:
1193 save
1194 brgz %i2, mac1_base_wr24
1195 nop
1196 setx MAC0_BASE, %l1, %l2
1197 setx XMAC_ADDR24, %l1, %l3
1198 add %l2, %l3, %l3
1199 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1200
1201 setx XMAC_ADDR25, %l1, %l3
1202 add %l2, %l3, %l3
1203 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1204
1205 setx XMAC_ADDR26, %l1, %l3
1206 add %l2, %l3, %l3
1207 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1208
1209 ba mac_base_wr24_done
1210 nop
1211mac1_base_wr24:
1212 setx MAC1_BASE, %l1, %l2
1213 setx XMAC_ADDR24, %l1, %l3
1214 add %l2, %l3, %l3
1215 stxa %i3, [%l3]ASI_PRIMARY_LITTLE
1216
1217 setx XMAC_ADDR25, %l1, %l3
1218 add %l2, %l3, %l3
1219 stxa %i4, [%l3]ASI_PRIMARY_LITTLE
1220
1221 setx XMAC_ADDR26, %l1, %l3
1222 add %l2, %l3, %l3
1223 stxa %i5, [%l3]ASI_PRIMARY_LITTLE
1224
1225mac_base_wr24_done:
1226 ret
1227 restore
1228
1229!/********************************************************************************
1230!* tx_mac_reset:
1231!* Reset the TX MAC for one port
1232!* Parameters in registers:
1233!* %o2: <=0 for Port 0, >0 for Port 1
1234!********************************************************************************/
1235tx_mac_reset:
1236 save
1237 brgz %i2, tx_mac_reset1
1238 nop
1239 setx xtxmac_sw_rst0_addr, %l1, %l2
1240 ba tx_mac_reset_d
1241 nop
1242tx_mac_reset1:
1243 setx xtxmac_sw_rst1_addr, %l1, %l2
1244tx_mac_reset_d:
1245 setx 0x01, %l1, %l3
1246 stxa %l3, [%l2]ASI_PRIMARY_LITTLE
1247
1248 call delay_1
1249 nop
1250 setx Time_out, %l1, %l3
1251loop_t0:
1252 ldxa [%l2]ASI_PRIMARY_LITTLE, %l4
1253
1254 brz %l4, return_back
1255 nop
1256 dec %l3
1257 brnz %l3, loop_t0
1258 nop
1259 call Timeout
1260 nop
1261
1262!/********************************************************************************
1263!* rx_mac_reset:
1264!* Reset the RX MAC for one port
1265!* Parameters in registers:
1266!* %o2: <=0 for Port 0, >0 for Port 1
1267!********************************************************************************/
1268rx_mac_reset:
1269 save
1270 brgz %i2, rx_mac_reset1
1271 nop
1272 setx xrxmac_sw_rst0_addr, %l1, %l2
1273 ba rx_mac_reset_d
1274 nop
1275rx_mac_reset1:
1276 setx xrxmac_sw_rst1_addr, %l1, %l2
1277rx_mac_reset_d:
1278 setx 0x01, %l1, %l3
1279 stxa %l3, [%l2]ASI_PRIMARY_LITTLE
1280
1281 call delay_1
1282 nop
1283 setx Time_out, %l1, %l3
1284loop_r0:
1285 ldxa [%l2]ASI_PRIMARY_LITTLE, %l4
1286
1287 brz %l4, return_back
1288 nop
1289 dec %l3
1290 brnz %l3, loop_r0
1291 nop
1292 call Timeout
1293 nop
1294
1295return_back:
1296 ret
1297 restore
1298
1299!/********************************************************************************
1300!* delay_1:
1301!* ???
1302!* Parameters in registers:
1303!* None
1304!********************************************************************************/
1305delay_1:
1306 save
1307 setx TX_CS, %l1, %l2
1308 ldxa [%l2]ASI_PRIMARY_LITTLE, %l1
1309 nop
1310 nop
1311 ret
1312 restore
1313
1314!/********************************************************************************
1315!* delay_10:
1316!* ???
1317!* Parameters in registers:
1318!* None
1319!********************************************************************************/
1320delay_10:
1321 save
1322 setx delay_10_count, %l1, %l5
1323 setx TX_CS, %l1, %l2
1324loop_delay:
1325 ldxa [%l2]ASI_PRIMARY_LITTLE, %l1
1326 nop
1327 dec %l5
1328 brnz %l5, loop_delay
1329 nop
1330 ret
1331 restore
1332
1333!/********************************************************************************
1334!* init_zcp_tbl_2dma:
1335!* Program DMA Table in zcp block for 2 dma variation
1336!* (It is also used for Multi-port)
1337!* Parameters in registers:
1338!* None
1339!********************************************************************************/
1340init_zcp_tbl_2dma:
1341 save
1342 setx ZCP_RDC_TBL_Addr, %l7, %l0
1343 mov %g0, %l1
1344zcp_16_table:
1345 setx zcp_16_count, %l1, %l5
1346zcp_16_count_0:
1347 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1348 add 0x8, %l0, %l0
1349 dec %l5
1350 brnz %l5, zcp_16_count_0
1351 nop
1352 inc %l1
1353 cmp %l1, 0x8
1354 bne zcp_16_table
1355 nop
1356 ret
1357 restore
1358
1359
1360!/********************************************************************************
1361!* init_zcp_tbl_1dma:
1362!* Program DMA Table in zcp block for one dma variation.
1363!* Parameters in registers:
1364!* None
1365!********************************************************************************/
1366init_zcp_tbl_1dma:
1367 save
1368 mov %g0, %l1
1369 setx ZCP_RDC_TBL_Addr, %l7, %l0
1370 setx zcp_128_count, %l1, %l5
1371zcp_128_count0:
1372 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1373 add 0x8, %l0, %l0
1374 dec %l5
1375 brnz %l5, zcp_128_count0
1376 nop
1377 ret
1378 restore
1379
1380!/********************************************************************************
1381!* init_zcp_tbl_4dma:
1382!* Program DMA Table in zcp block for 4 dma variation.
1383!* Parameters in registers:
1384!* None
1385!********************************************************************************/
1386init_zcp_tbl_4dma:
1387 save
1388 mov %g0, %l1
1389 setx ZCP_RDC_TBL_Addr, %l7, %l0
1390 setx zcp_32_count, %l7, %l5
1391zcp_32_count0:
1392 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1393 add 0x8, %l0, %l0
1394 dec %l5
1395 brnz %l5, zcp_32_count0
1396 nop
1397 inc %l1
1398 setx zcp_32_count, %l7, %l5
1399zcp_32_count1:
1400 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1401 add 0x8, %l0, %l0
1402 dec %l5
1403 brnz %l5, zcp_32_count1
1404 nop
1405 inc %l1
1406 setx zcp_32_count, %l7, %l5
1407zcp_32_count2:
1408 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1409 add 0x8, %l0, %l0
1410 dec %l5
1411 brnz %l5, zcp_32_count2
1412 nop
1413 inc %l1
1414 setx zcp_32_count, %l7, %l5
1415zcp_32_count3:
1416 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1417 add 0x8, %l0, %l0
1418 dec %l5
1419 brnz %l5, zcp_32_count3
1420 nop
1421 ret
1422 restore
1423
1424!/********************************************************************************
1425!* init_zcp_tbl_8dma:
1426!* Program DMA Table in zcp block for 8 dma variation.
1427!* Parameters in registers:
1428!* None
1429!********************************************************************************/
1430init_zcp_tbl_8dma:
1431 save
1432 mov %g0, %l1
1433 setx ZCP_RDC_TBL_Addr, %l7, %l0
1434 setx zcp_16_count, %l7, %l5
1435zcp_16_count0:
1436 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1437 add 0x8, %l0, %l0
1438 dec %l5
1439 brnz %l5, zcp_16_count0
1440 nop
1441 inc %l1
1442 setx zcp_16_count, %l7, %l5
1443zcp_16_count1:
1444 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1445 add 0x8, %l0, %l0
1446 dec %l5
1447 brnz %l5, zcp_16_count1
1448 nop
1449 inc %l1
1450 setx zcp_16_count, %l7, %l5
1451zcp_16_count2:
1452 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1453 add 0x8, %l0, %l0
1454 dec %l5
1455 brnz %l5, zcp_16_count2
1456 nop
1457 inc %l1
1458 setx zcp_16_count, %l7, %l5
1459zcp_16_count3:
1460 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1461 add 0x8, %l0, %l0
1462 dec %l5
1463 brnz %l5, zcp_16_count3
1464 nop
1465 inc %l1
1466 setx zcp_16_count, %l7, %l5
1467zcp_16_count4:
1468 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1469 add 0x8, %l0, %l0
1470 dec %l5
1471 brnz %l5, zcp_16_count4
1472 nop
1473 inc %l1
1474 setx zcp_16_count, %l7, %l5
1475zcp_16_count5:
1476 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1477 add 0x8, %l0, %l0
1478 dec %l5
1479 brnz %l5, zcp_16_count5
1480 nop
1481 inc %l1
1482 setx zcp_16_count, %l7, %l5
1483zcp_16_count6:
1484 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1485 add 0x8, %l0, %l0
1486 dec %l5
1487 brnz %l5, zcp_16_count6
1488 nop
1489 inc %l1
1490 setx zcp_16_count, %l7, %l5
1491zcp_16_count7:
1492 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
1493 add 0x8, %l0, %l0
1494 dec %l5
1495 brnz %l5, zcp_16_count7
1496 nop
1497 ret
1498 restore
1499
1500
1501Timeout:
1502 call test_failed
1503 nop
1504
1505/***************************************************************************
1506** Subroutines for TX
1507**
1508** cpp/m4 text macros:
1509** NIU_TX_MULTI_TEST => if not defined, only support one DMA channel
1510** if defined, support multiple DMA channels:
1511** DMA 0-7 for port 0
1512** DMA 8-15 for port 1
1513***************************************************************************/
1514#ifdef NIU_TX_MULTI_TEST
1515!/********************************************************************************
1516!* AddTxChannels:
1517!* Currently unused
1518!* Parameters in registers:
1519!* None
1520!********************************************************************************/
1521AddTxChannels:
1522 save
1523 ret
1524 restore
1525
1526!/********************************************************************************
1527!* SetTxMaxBurst:
1528!* Set the maximum TX burst size for the DMA channel
1529!* Parameters in registers:
1530!* %o1: Maximum TX burst size
1531!* %o2: Is multi-port (not currently used)
1532!* %o3: Bit-mask of Port 0 DMA channels to set; bit 0 == DMA channel 0, etc.
1533!* %o4: Bit-mask of Port 1 DMA channels to set; bit 0 == DMA channel 0, etc.
1534!********************************************************************************/
1535.global SetTxMaxBurst
1536SetTxMaxBurst:
1537 save
1538
1539 mov %i1, %o1 ! MAX_BURST_DATA
1540! mov %i2, %o2 ! NIU_TX_MULTI_PORT
1541! mov %i3, %o3 ! NIU_TX_MULTI_DMA_P0
1542! mov %i4, %o4 ! NIU_TX_MULTI_DMA_P1
1543
1544check_p0_SetMaxBurst:
1545 brgz %i3, p0_SetMaxBurst_call
1546 nop
1547 brgz %i4, p1_SetMaxBurst_call
1548 nop
1549 ret
1550 restore
1551
1552p0_SetMaxBurst_call:
1553 mov %i3, %o0
1554 call Start_Check_SetMaxBurst
1555 nop
1556 brgz %i4, p1_SetMaxBurst_call
1557 nop
1558 ret
1559 restore
1560p1_SetMaxBurst_call:
1561 mov %i4, %o0
1562 call Start_Check_SetMaxBurst
1563 nop
1564 ret
1565 restore
1566
1567Start_Check_SetMaxBurst:
1568 save
1569 mov 0x1, %l0
1570 andcc %i0, %l0, %g0
1571 bz %xcc, Check_SetMaxBurst_Dma1
1572 nop
1573SetMaxBurstValue_DMA0:
1574 setx SetTxMaxBurst_DMA0_Addr, %l7, %l2
1575 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1576
1577Check_SetMaxBurst_Dma1:
1578 sllx %l0, 1, %l0
1579 andcc %i0, %l0, %g0
1580 bz %xcc, Check_SetMaxBurst_Dma2
1581 nop
1582SetMaxBurstValue_DMA1:
1583 setx SetTxMaxBurst_DMA1_Addr, %l7, %l2
1584 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1585
1586Check_SetMaxBurst_Dma2:
1587 sllx %l0, 1, %l0
1588 andcc %i0, %l0, %g0
1589 bz %xcc, Check_SetMaxBurst_Dma3
1590 nop
1591SetMaxBurstValue_DMA2:
1592 setx SetTxMaxBurst_DMA2_Addr, %l7, %l2
1593 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1594
1595Check_SetMaxBurst_Dma3:
1596 sllx %l0, 1, %l0
1597 andcc %i0, %l0, %g0
1598 bz %xcc, Check_SetMaxBurst_Dma4
1599 nop
1600SetMaxBurstValue_DMA3:
1601 setx SetTxMaxBurst_DMA3_Addr, %l7, %l2
1602 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1603
1604Check_SetMaxBurst_Dma4:
1605 sllx %l0, 1, %l0
1606 andcc %i0, %l0, %g0
1607 bz %xcc, Check_SetMaxBurst_Dma5
1608 nop
1609SetMaxBurstValue_DMA4:
1610 setx SetTxMaxBurst_DMA4_Addr, %l7, %l2
1611 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1612
1613Check_SetMaxBurst_Dma5:
1614 sllx %l0, 1, %l0
1615 andcc %i0, %l0, %g0
1616 bz %xcc, Check_SetMaxBurst_Dma6
1617 nop
1618SetMaxBurstValue_DMA5:
1619 setx SetTxMaxBurst_DMA5_Addr, %l7, %l2
1620 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1621
1622Check_SetMaxBurst_Dma6:
1623 sllx %l0, 1, %l0
1624 andcc %i0, %l0, %g0
1625 bz %xcc, Check_SetMaxBurst_Dma7
1626 nop
1627SetMaxBurstValue_DMA6:
1628 setx SetTxMaxBurst_DMA6_Addr, %l7, %l2
1629 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1630
1631Check_SetMaxBurst_Dma7:
1632 sllx %l0, 1, %l0
1633 andcc %i0, %l0, %g0
1634 bz %xcc, Check_SetMaxBurst_Dma8
1635 nop
1636SetMaxBurstValue_DMA7:
1637 setx SetTxMaxBurst_DMA7_Addr, %l7, %l2
1638 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1639
1640Check_SetMaxBurst_Dma8:
1641 sllx %l0, 1, %l0
1642 andcc %i0, %l0, %g0
1643 bz %xcc, Check_SetMaxBurst_Dma9
1644 nop
1645SetMaxBurstValue_DMA8:
1646 setx SetTxMaxBurst_DMA8_Addr, %l7, %l2
1647 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1648
1649Check_SetMaxBurst_Dma9:
1650 sllx %l0, 1, %l0
1651 andcc %i0, %l0, %g0
1652 bz %xcc, Check_SetMaxBurst_Dma10
1653 nop
1654SetMaxBurstValue_DMA9:
1655 setx SetTxMaxBurst_DMA9_Addr, %l7, %l2
1656 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1657
1658Check_SetMaxBurst_Dma10:
1659 sllx %l0, 1, %l0
1660 andcc %i0, %l0, %g0
1661 bz %xcc, Check_SetMaxBurst_Dma11
1662 nop
1663SetMaxBurstValue_DMA10:
1664 setx SetTxMaxBurst_DMA10_Addr, %l7, %l2
1665 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1666
1667Check_SetMaxBurst_Dma11:
1668 sllx %l0, 1, %l0
1669 andcc %i0, %l0, %g0
1670 bz %xcc, Check_SetMaxBurst_Dma12
1671 nop
1672SetMaxBurstValue_DMA11:
1673 setx SetTxMaxBurst_DMA11_Addr, %l7, %l2
1674 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1675
1676Check_SetMaxBurst_Dma12:
1677 sllx %l0, 1, %l0
1678 andcc %i0, %l0, %g0
1679 bz %xcc, Check_SetMaxBurst_Dma13
1680 nop
1681SetMaxBurstValue_DMA12:
1682 setx SetTxMaxBurst_DMA12_Addr, %l7, %l2
1683 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1684
1685Check_SetMaxBurst_Dma13:
1686 sllx %l0, 1, %l0
1687 andcc %i0, %l0, %g0
1688 bz %xcc, Check_SetMaxBurst_Dma14
1689 nop
1690SetMaxBurstValue_DMA13:
1691 setx SetTxMaxBurst_DMA13_Addr, %l7, %l2
1692 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1693
1694Check_SetMaxBurst_Dma14:
1695 sllx %l0, 1, %l0
1696 andcc %i0, %l0, %g0
1697 bz %xcc, Check_SetMaxBurst_Dma15
1698 nop
1699SetMaxBurstValue_DMA14:
1700 setx SetTxMaxBurst_DMA14_Addr, %l7, %l2
1701 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1702
1703Check_SetMaxBurst_Dma15:
1704 sllx %l0, 1, %l0
1705 andcc %i0, %l0, %g0
1706 bz %xcc, SetMaxBurstValue_end
1707 nop
1708SetMaxBurstValue_DMA15:
1709 setx SetTxMaxBurst_DMA15_Addr, %l7, %l2
1710 stxa %i1, [%l2]ASI_PRIMARY_LITTLE
1711
1712SetMaxBurstValue_end:
1713 ret
1714 restore
1715
1716
1717!/********************************************************************************
1718!* SetTxDMAActive:
1719!* Activate specified TX DMA channels
1720!* Parameters in registers:
1721!* %o0: Unused
1722!* %o1: Unused
1723!* %o2: >0 means both ports
1724!* %o3: Bit-mask of Port 0 DMA channels to set; bit 0 == DMA channel 0, etc.
1725!* %o4: Bit-mask of Port 1 DMA channels to set; bit 0 == DMA channel 0, etc.
1726!********************************************************************************/
1727.global SetTxDMAActive
1728SetTxDMAActive:
1729 save
1730! mov %i1, %g3
1731! mov %i2, %g4 ! NIU_TX_MULTI_PORT
1732! mov %i3, %g5 ! NIU_TX_MULTI_DMA_P0
1733! mov %i4, %l5 ! NIU_TX_MULTI_DMA_P1
1734
1735check_Port0DMAActive:
1736 brgz %i3, SetPort0DMAActive
1737 nop
1738 brgz %i4, SetPort1DMAActive
1739 nop
1740
1741 ret
1742 restore
1743
1744
1745SetPort0DMAActive :
1746 setx 0xffff, %l7, %l0
1747 and %i3, %l0, %l0
1748 brnz %l0, SetPort0Active_DMA
1749 nop
1750
1751 brz %i2, SetTxDMAActive_End
1752 nop
1753
1754SetPort1DMAActive :
1755 setx 0xffff, %l7, %l0
1756 and %i4, %l0, %l0
1757 brnz %l0, SetPort1Active_DMA
1758 nop
1759
1760SetTxDMAActive_End :
1761 ret
1762 restore
1763
1764SetPort0Active_DMA:
1765 setx SetPort0TxDMAActive_Addr, %l7, %l1
1766 stxa %l0, [%l1]ASI_PRIMARY_LITTLE
1767
1768 brgz %i2, 1f
1769 nop
1770 ret
1771 restore
17721:
1773SetPort1Active_DMA:
1774 setx 0xffff, %l7, %l0
1775 and %i4, %l0, %l0
1776 setx SetPort1TxDMAActive_Addr, %l7, %l1
1777 stxa %l0, [%l1]ASI_PRIMARY_LITTLE
1778
1779 ret
1780 restore
1781
1782!/********************************************************************************
1783!* InitTxDma:
1784!* This routine programs the transmit path registers for one DMA channel.
1785!* The caller must use the NIU_InitTxDma user event to write the registers's
1786!* data to PEU_SRAM.
1787!* This subroutine retrieves the data from the PEU_SRAM and write the data
1788!* to each TX register mentioned below in assembly.
1789!* TX_MASK1
1790!* TX_VALUE1
1791!* TX_RELOC1
1792!* TX_MASK2
1793!* TX_VALUE2
1794!* TX_RELOC2
1795!* TX_PAGE_VALID
1796!* TX_RING_CONFIG
1797!* This routine must be called for each enabled DMA channel.
1798!* Parameters in registers:
1799!* %o0: DMA NUMBER
1800!* %o1: Unused
1801!* %o2: NIU_TX_MULTI_PORT
1802!* %o3: NIU_TX_MULTI_DMA_P0
1803!* %o4: NIU_TX_MULTI_DMA_P1
1804!********************************************************************************/
1805.global InitTxDma
1806InitTxDma:
1807 save
1808
1809 mov %i0, %o0 ! DMA NUMBER
1810 mov %i2, %o2 ! NIU_TX_MULTI_PORT
1811 mov %i3, %o3 ! NIU_TX_MULTI_DMA_P0
1812 mov %i4, %o4 ! NIU_TX_MULTI_DMA_P1
1813
1814 or %i3, %i4, %l0
1815 brgz %l0, check_p0_dmas
1816 nop
1817 call SetPage0Registers
1818 nop
1819 ret
1820 restore
1821
1822check_p0_dmas:
1823 brgz %o3, Set_Tx_Reg_Multi_Dma
1824 nop
1825 brgz %o4, P1_Tx_Dma0
1826 nop
1827 ret
1828 restore ! Return InitTxDMA
1829
1830Set_Tx_Reg_Multi_Dma:
1831 mov 0x1, %l0
1832 andcc %o3, %l0, %g0
1833 bz %xcc, P0_Tx_Dma1
1834 nop
1835 set 0, %o0
1836Do_P0_Tx_Dma0:
1837! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma0)) -> NIU_InitTxDma (0, 0, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1838 call SetPage0Registers
1839 nop
1840P0_Tx_Dma1:
1841 sllx %l0, 1, %l0
1842 andcc %o3, %l0, %g0
1843 bz %xcc, P0_Tx_Dma2
1844 nop
1845 set 1, %o0
1846Do_P0_Tx_Dma1:
1847! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma1)) -> NIU_InitTxDma (0, 1, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1848 call SetPage0Registers
1849 nop
1850P0_Tx_Dma2:
1851 sllx %l0, 1, %l0
1852 andcc %o3, %l0, %g0
1853 bz %xcc, P0_Tx_Dma3
1854 nop
1855 set 2, %o0
1856Do_P0_Tx_Dma2:
1857! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma2)) -> NIU_InitTxDma (0, 2, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1858 call SetPage0Registers
1859 nop
1860P0_Tx_Dma3:
1861 sllx %l0, 1, %l0
1862 andcc %o3, %l0, %g0
1863 bz %xcc, P0_Tx_Dma4
1864 nop
1865 set 3, %o0
1866Do_P0_Tx_Dma3:
1867! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma3)) -> NIU_InitTxDma (0, 3, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1868 call SetPage0Registers
1869 nop
1870P0_Tx_Dma4:
1871 sllx %l0, 1, %l0
1872 andcc %o3, %l0, %g0
1873 bz %xcc, P0_Tx_Dma5
1874 nop
1875 set 4, %o0
1876Do_P0_Tx_Dma4:
1877! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma4)) -> NIU_InitTxDma (0, 4, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1878 call SetPage0Registers
1879 nop
1880P0_Tx_Dma5:
1881 sllx %l0, 1, %l0
1882 andcc %o3, %l0, %g0
1883 bz %xcc, P0_Tx_Dma6
1884 nop
1885 set 5, %o0
1886Do_P0_Tx_Dma5:
1887! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma5)) -> NIU_InitTxDma (0, 5, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1888 call SetPage0Registers
1889 nop
1890P0_Tx_Dma6:
1891 sllx %l0, 1, %l0
1892 andcc %o3, %l0, %g0
1893 bz %xcc, P0_Tx_Dma7
1894 nop
1895 set 6, %o0
1896Do_P0_Tx_Dma6:
1897! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma6)) -> NIU_InitTxDma (0, 6, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1898 call SetPage0Registers
1899 nop
1900P0_Tx_Dma7:
1901 sllx %l0, 1, %l0
1902 andcc %o3, %l0, %g0
1903 bz %xcc, P0_Tx_Dma8
1904 nop
1905 set 7, %o0
1906Do_P0_Tx_Dma7:
1907! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma7)) -> NIU_InitTxDma (0, 7, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1908 call SetPage0Registers
1909 nop
1910P0_Tx_Dma8:
1911 sllx %l0, 1, %l0
1912 andcc %o3, %l0, %g0
1913 bz %xcc, P0_Tx_Dma9
1914 nop
1915 set 8, %o0
1916Do_P0_Tx_Dma8:
1917! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma8)) -> NIU_InitTxDma (0, 8, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1918 call SetPage0Registers
1919 nop
1920P0_Tx_Dma9:
1921 sllx %l0, 1, %l0
1922 andcc %o3, %l0, %g0
1923 bz %xcc, P0_Tx_Dma10
1924 nop
1925 set 9, %o0
1926Do_P0_Tx_Dma9:
1927! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma9)) -> NIU_InitTxDma (0, 9, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1928 call SetPage0Registers
1929 nop
1930P0_Tx_Dma10:
1931 sllx %l0, 1, %l0
1932 andcc %o3, %l0, %g0
1933 bz %xcc, P0_Tx_Dma11
1934 nop
1935 set 10, %o0
1936Do_P0_Tx_Dma10:
1937! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma10)) -> NIU_InitTxDma (0, a, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1938 call SetPage0Registers
1939 nop
1940P0_Tx_Dma11:
1941 sllx %l0, 1, %l0
1942 andcc %o3, %l0, %g0
1943 bz %xcc, P0_Tx_Dma12
1944 nop
1945 set 11, %o0
1946Do_P0_Tx_Dma11:
1947! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma11)) -> NIU_InitTxDma (0, b, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1948 call SetPage0Registers
1949 nop
1950P0_Tx_Dma12:
1951 sllx %l0, 1, %l0
1952 andcc %o3, %l0, %g0
1953 bz %xcc, P0_Tx_Dma13
1954 nop
1955 set 12, %o0
1956Do_P0_Tx_Dma12:
1957! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma12)) -> NIU_InitTxDma (0, c, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1958 call SetPage0Registers
1959 nop
1960P0_Tx_Dma13:
1961 sllx %l0, 1, %l0
1962 andcc %o3, %l0, %g0
1963 bz %xcc, P0_Tx_Dma14
1964 nop
1965 set 13, %o0
1966Do_P0_Tx_Dma13:
1967! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma13)) -> NIU_InitTxDma (0, d, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1968 call SetPage0Registers
1969 nop
1970P0_Tx_Dma14:
1971 sllx %l0, 1, %l0
1972 andcc %o3, %l0, %g0
1973 bz %xcc, P0_Tx_Dma15
1974 nop
1975 set 14, %o0
1976Do_P0_Tx_Dma14:
1977! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma14)) -> NIU_InitTxDma (0, e, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1978 call SetPage0Registers
1979 nop
1980P0_Tx_Dma15:
1981 sllx %l0, 1, %l0
1982 andcc %o3, %l0, %g0
1983 bz %xcc, P1_Tx_Dma0
1984 nop
1985 set 15, %o0
1986Do_P0_Tx_Dma15:
1987! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_P0_Tx_Dma15)) -> NIU_InitTxDma (0, f, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1988 call SetPage0Registers
1989 nop
1990P1_Tx_Dma0:
1991 mov 0x1, %l0
1992 andcc %o4, %l0, %g0
1993 bz %xcc, p1_Tx_Dma1
1994 nop
1995 set 0, %o0
1996Do_p1_Tx_Dma0:
1997! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma0)) -> NIU_InitTxDma (1, 0, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
1998 call SetPage0Registers
1999 nop
2000p1_Tx_Dma1:
2001 sllx %l0, 1, %l0
2002 andcc %o4, %l0, %g0
2003 bz %xcc, p1_Tx_Dma2
2004 nop
2005 set 1, %o0
2006Do_p1_Tx_Dma1:
2007! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma1)) -> NIU_InitTxDma (1, 1, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2008 call SetPage0Registers
2009 nop
2010p1_Tx_Dma2:
2011 sllx %l0, 1, %l0
2012 andcc %o4, %l0, %g0
2013 bz %xcc, p1_Tx_Dma3
2014 nop
2015 set 2, %o0
2016Do_p1_Tx_Dma2:
2017! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma2)) -> NIU_InitTxDma (1, 2, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2018 call SetPage0Registers
2019 nop
2020p1_Tx_Dma3:
2021 sllx %l0, 1, %l0
2022 andcc %o4, %l0, %g0
2023 bz %xcc, p1_Tx_Dma4
2024 nop
2025 set 3, %o0
2026Do_p1_Tx_Dma3:
2027! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma3)) -> NIU_InitTxDma (1, 3, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2028 call SetPage0Registers
2029 nop
2030p1_Tx_Dma4:
2031 sllx %l0, 1, %l0
2032 andcc %o4, %l0, %g0
2033 bz %xcc, p1_Tx_Dma5
2034 nop
2035 set 4, %o0
2036Do_p1_Tx_Dma4:
2037! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma4)) -> NIU_InitTxDma (1, 4, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2038 call SetPage0Registers
2039 nop
2040p1_Tx_Dma5:
2041 sllx %l0, 1, %l0
2042 andcc %o4, %l0, %g0
2043 bz %xcc, p1_Tx_Dma6
2044 nop
2045 set 5, %o0
2046Do_p1_Tx_Dma5:
2047! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma5)) -> NIU_InitTxDma (1, 5, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2048 call SetPage0Registers
2049 nop
2050p1_Tx_Dma6:
2051 sllx %l0, 1, %l0
2052 andcc %o4, %l0, %g0
2053 bz %xcc, p1_Tx_Dma7
2054 nop
2055 set 6, %o0
2056Do_p1_Tx_Dma6:
2057! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma6)) -> NIU_InitTxDma (1, 6, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2058 call SetPage0Registers
2059 nop
2060p1_Tx_Dma7:
2061 sllx %l0, 1, %l0
2062 andcc %o4, %l0, %g0
2063 bz %xcc, p1_Tx_Dma8
2064 nop
2065 set 7, %o0
2066Do_p1_Tx_Dma7:
2067! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma7)) -> NIU_InitTxDma (1, 7, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2068 call SetPage0Registers
2069 nop
2070p1_Tx_Dma8:
2071 sllx %l0, 1, %l0
2072 andcc %o4, %l0, %g0
2073 bz %xcc, p1_Tx_Dma9
2074 nop
2075 set 8, %o0
2076Do_p1_Tx_Dma8:
2077! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma8)) -> NIU_InitTxDma (1, 8, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2078 call SetPage0Registers
2079 nop
2080p1_Tx_Dma9:
2081 sllx %l0, 1, %l0
2082 andcc %o4, %l0, %g0
2083 bz %xcc, p1_Tx_Dma10
2084 nop
2085 set 9, %o0
2086Do_p1_Tx_Dma9:
2087! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma9)) -> NIU_InitTxDma (1, 9, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2088 call SetPage0Registers
2089 nop
2090p1_Tx_Dma10:
2091 sllx %l0, 1, %l0
2092 andcc %o4, %l0, %g0
2093 bz %xcc, p1_Tx_Dma11
2094 nop
2095 set 10, %o0
2096Do_p1_Tx_Dma10:
2097! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma10)) -> NIU_InitTxDma (1, a, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2098 call SetPage0Registers
2099 nop
2100p1_Tx_Dma11:
2101 sllx %l0, 1, %l0
2102 andcc %o4, %l0, %g0
2103 bz %xcc, p1_Tx_Dma12
2104 nop
2105 set 11, %o0
2106Do_p1_Tx_Dma11:
2107! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma11)) -> NIU_InitTxDma (1, b, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2108 call SetPage0Registers
2109 nop
2110p1_Tx_Dma12:
2111 sllx %l0, 1, %l0
2112 andcc %o4, %l0, %g0
2113 bz %xcc, p1_Tx_Dma13
2114 nop
2115 set 12, %o0
2116Do_p1_Tx_Dma12:
2117! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma12)) -> NIU_InitTxDma (1, c, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2118 call SetPage0Registers
2119 nop
2120p1_Tx_Dma13:
2121 sllx %l0, 1, %l0
2122 andcc %o4, %l0, %g0
2123 bz %xcc, p1_Tx_Dma14
2124 nop
2125 set 13, %o0
2126Do_p1_Tx_Dma13:
2127! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma13)) -> NIU_InitTxDma (1, d, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2128 call SetPage0Registers
2129 nop
2130p1_Tx_Dma14:
2131 sllx %l0, 1, %l0
2132 andcc %o4, %l0, %g0
2133 bz %xcc, p1_Tx_Dma15
2134 nop
2135 set 14, %o0
2136Do_p1_Tx_Dma14:
2137! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma14)) -> NIU_InitTxDma (1, e, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2138 call SetPage0Registers
2139 nop
2140p1_Tx_Dma15:
2141 sllx %l0, 1, %l0
2142 andcc %o4, %l0, %g0
2143 bz %xcc, done_InitTxDma
2144 nop
2145 set 15, %o0
2146Do_p1_Tx_Dma15:
2147! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.Do_p1_Tx_Dma15)) -> NIU_InitTxDma (1, f, NIU_Xlate_On, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
2148 call SetPage0Registers
2149 nop
2150
2151done_InitTxDma:
2152 ret
2153 restore ! Return InitTxDMA
2154
2155SetPage0Registers:
2156 save
2157
2158P_SetTxLPMask1:
2159 mov %i0, %o0
2160 mulx %o0, 0x200, %l2
2161 setx TX_LOG_MASK1_Addr, %l7, %l3
2162 add %l3, %l2, %l3
2163#ifdef XLATE_ON
2164 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_MASK1, %l7, %l0
2165#ifdef FC_NO_PEU_VERA
2166 ! PEP does not support 64-bit access, so use two 32-bit loads
2167 lduw [%l0], %l1
2168 lduw [%l0+4], %l2
2169 sllx %l1, 32, %l1
2170 add %l2, %l1, %l1
2171#else // FC_NO_PEU_VERA
2172 ldx [%l0], %l1
2173#endif // FC_NO_PEU_VERA
2174 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2175#else
2176 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2177#endif // XLATE_ON
2178
2179P_SetTxLPValue1:
2180 mulx %o0, 0x200, %l2
2181 setx TX_LOG_VALUE1_Addr, %l7, %l3
2182 add %l3, %l2, %l3
2183#ifdef XLATE_ON
2184 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_VALUE1, %l7, %l0
2185#ifdef FC_NO_PEU_VERA
2186 ! PEP does not support 64-bit access, so use two 32-bit loads
2187 lduw [%l0], %l1
2188 lduw [%l0+4], %l2
2189 sllx %l1, 32, %l1
2190 add %l2, %l1, %l1
2191#else // FC_NO_PEU_VERA
2192 ldx [%l0], %l1
2193#endif // FC_NO_PEU_VERA
2194 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2195#else
2196 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2197#endif // XLATE_ON
2198
2199P_SetTxLPRELOC1:
2200 mulx %o0, 0x200, %l2
2201 setx TX_LOG_PAGE_RELO1_Addr, %l7, %l3
2202 add %l3, %l2, %l3
2203#ifdef XLATE_ON
2204 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_RELO1, %l7, %l0
2205#ifdef FC_NO_PEU_VERA
2206 ! PEP does not support 64-bit access, so use two 32-bit loads
2207 lduw [%l0], %l1
2208 lduw [%l0+4], %l2
2209 sllx %l1, 32, %l1
2210 add %l2, %l1, %l1
2211#else // FC_NO_PEU_VERA
2212 ldx [%l0], %l1
2213#endif // FC_NO_PEU_VERA
2214 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2215#else
2216 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2217#endif // XLATE_ON
2218
2219
2220SetPage1Registers:
2221
2222P_SetTxLPMask2:
2223 mulx %o0, 0x200, %l2
2224 setx TX_LOG_MASK2_Addr, %l7, %l3
2225 add %l3, %l2, %l3
2226#ifdef XLATE_ON
2227 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_MASK2, %l7, %l0
2228#ifdef FC_NO_PEU_VERA
2229 ! PEP does not support 64-bit access, so use two 32-bit loads
2230 lduw [%l0], %l1
2231 lduw [%l0+4], %l2
2232 sllx %l1, 32, %l1
2233 add %l2, %l1, %l1
2234#else // FC_NO_PEU_VERA
2235 ldx [%l0], %l1
2236#endif // FC_NO_PEU_VERA
2237 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2238#else
2239 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2240#endif // XLATE_ON
2241
2242P_SetTxLPValue2:
2243 mulx %o0, 0x200, %l2
2244 setx TX_LOG_VALUE2_Addr, %l7, %l3
2245 add %l3, %l2, %l3
2246#ifdef XLATE_ON
2247 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_VALUE2, %l7, %l0
2248#ifdef FC_NO_PEU_VERA
2249 ! PEP does not support 64-bit access, so use two 32-bit loads
2250 lduw [%l0], %l1
2251 lduw [%l0+4], %l2
2252 sllx %l1, 32, %l1
2253 add %l2, %l1, %l1
2254#else // FC_NO_PEU_VERA
2255 ldx [%l0], %l1
2256#endif // FC_NO_PEU_VERA
2257 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2258#else
2259 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2260#endif // XLATE_ON
2261
2262P_SetTxLPRELOC2:
2263 mulx %o0, 0x200, %l2
2264 setx TX_LOG_PAGE_RELO2_Addr, %l7, %l3
2265 add %l3, %l2, %l3
2266#ifdef XLATE_ON
2267 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_RELO2, %l7, %l0
2268#ifdef FC_NO_PEU_VERA
2269 ! PEP does not support 64-bit access, so use two 32-bit loads
2270 lduw [%l0], %l1
2271 lduw [%l0+4], %l2
2272 sllx %l1, 32, %l1
2273 add %l2, %l1, %l1
2274#else // FC_NO_PEU_VERA
2275 ldx [%l0], %l1
2276#endif // FC_NO_PEU_VERA
2277 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2278#else
2279 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2280#endif // XLATE_ON
2281
2282SetPageEnables:
2283
2284P_SetTxLPValid:
2285 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_VLD, %l7, %l0
2286#ifdef FC_NO_PEU_VERA
2287 ! PEP does not support 64-bit access, so use two 32-bit loads
2288 lduw [%l0], %l1
2289 lduw [%l0+4], %l2
2290 sllx %l1, 32, %l1
2291 add %l2, %l1, %l1
2292#else // FC_NO_PEU_VERA
2293 ldx [%l0], %l1
2294#endif // FC_NO_PEU_VERA
2295 mulx %o0, 0x200, %l2
2296 setx TX_LOG_PAGE_VLD_Addr, %l7, %l0
2297 add %l0, %l2, %l0
2298 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2299
2300
2301SetRngConfig:
2302 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_CFIG, %l7, %l0
2303#ifdef FC_NO_PEU_VERA
2304 ! PEP does not support 64-bit access, so use two 32-bit loads
2305 lduw [%l0], %l1
2306 lduw [%l0+4], %l2
2307 sllx %l1, 32, %l1
2308 add %l2, %l1, %l1
2309#else // FC_NO_PEU_VERA
2310 ldx [%l0], %l1
2311#endif // FC_NO_PEU_VERA
2312 mulx %o0, 0x200, %l2
2313 setx TX_RNG_CFIG_Addr, %l7, %l0
2314 add %l0, %l2, %l0
2315 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2316
2317 ret
2318 restore ! Return InitTxDMA
2319#else
2320!/********************************************************************************
2321!* AddTxChannels:
2322!* Currently unused
2323!* Parameters in registers:
2324!* None
2325!********************************************************************************/
2326AddTxChannels:
2327 save
2328 ret
2329 restore
2330
2331.global SetTxMaxBurst
2332SetTxMaxBurst:
2333 save
2334! mov %i0, %g7
2335! mov %i1, %g3
2336 mov %g0, %l6 ! For 16 Tx channel
2337 cmp %i0, %l6
2338 be SetTxMaxBurst_DMA0
2339 nop
2340 inc %l6
2341 cmp %i0, %l6
2342 be SetTxMaxBurst_DMA1
2343 nop
2344 inc %l6
2345 cmp %i0, %l6
2346 be SetTxMaxBurst_DMA2
2347 nop
2348 inc %l6
2349 cmp %i0, %l6
2350 be SetTxMaxBurst_DMA3
2351 nop
2352 inc %l6
2353 cmp %i0, %l6
2354 be SetTxMaxBurst_DMA4
2355 nop
2356 inc %l6
2357 cmp %i0, %l6
2358 be SetTxMaxBurst_DMA5
2359 nop
2360 inc %l6
2361 cmp %i0, %l6
2362 be SetTxMaxBurst_DMA6
2363 nop
2364 inc %l6
2365 cmp %i0, %l6
2366 be SetTxMaxBurst_DMA7
2367 nop
2368 inc %l6
2369 cmp %i0, %l6
2370 be SetTxMaxBurst_DMA8
2371 nop
2372 inc %l6
2373 cmp %i0, %l6
2374 be SetTxMaxBurst_DMA9
2375 nop
2376 inc %l6
2377 cmp %i0, %l6
2378 be SetTxMaxBurst_DMA10
2379 nop
2380 inc %l6
2381 cmp %i0, %l6
2382 be SetTxMaxBurst_DMA11
2383 nop
2384 inc %l6
2385 cmp %i0, %l6
2386 be SetTxMaxBurst_DMA12
2387 nop
2388 inc %l6
2389 cmp %i0, %l6
2390 be SetTxMaxBurst_DMA13
2391 nop
2392 inc %l6
2393 cmp %i0, %l6
2394 be SetTxMaxBurst_DMA14
2395 nop
2396 inc %l6
2397 cmp %i0, %l6
2398 be SetTxMaxBurst_DMA15
2399 nop
2400 inc %l6
2401 cmp %i0, %l6
2402 be SetTxMaxBurst_DMA16
2403 nop
2404 inc %l6
2405 cmp %i0, %l6
2406 be SetTxMaxBurst_DMA17
2407 nop
2408 inc %l6
2409 cmp %i0, %l6
2410 be SetTxMaxBurst_DMA18
2411 nop
2412 inc %l6
2413 cmp %i0, %l6
2414 be SetTxMaxBurst_DMA19
2415 nop
2416 inc %l6
2417 cmp %i0, %l6
2418 be SetTxMaxBurst_DMA20
2419 nop
2420 inc %l6
2421 cmp %i0, %l6
2422 be SetTxMaxBurst_DMA21
2423 nop
2424 inc %l6
2425 cmp %i0, %l6
2426 be SetTxMaxBurst_DMA22
2427 nop
2428 inc %l6
2429 cmp %i0, %l6
2430 be SetTxMaxBurst_DMA23
2431 nop
2432TxDMAGreater:
2433 call test_failed
2434 nop
2435
2436SetTxMaxBurst_DMA0:
2437 setx SetTxMaxBurst_DMA0_Addr, %l7, %l0
2438 ba SetTxMaxBurst_End
2439 nop
2440SetTxMaxBurst_DMA1:
2441 setx SetTxMaxBurst_DMA1_Addr, %l7, %l0
2442 ba SetTxMaxBurst_End
2443 nop
2444SetTxMaxBurst_DMA2:
2445 setx SetTxMaxBurst_DMA2_Addr, %l7, %l0
2446 ba SetTxMaxBurst_End
2447 nop
2448SetTxMaxBurst_DMA3:
2449 setx SetTxMaxBurst_DMA3_Addr, %l7, %l0
2450 ba SetTxMaxBurst_End
2451 nop
2452SetTxMaxBurst_DMA4:
2453 setx SetTxMaxBurst_DMA4_Addr, %l7, %l0
2454 ba SetTxMaxBurst_End
2455 nop
2456SetTxMaxBurst_DMA5:
2457 setx SetTxMaxBurst_DMA5_Addr, %l7, %l0
2458 ba SetTxMaxBurst_End
2459 nop
2460SetTxMaxBurst_DMA6:
2461 setx SetTxMaxBurst_DMA6_Addr, %l7, %l0
2462 ba SetTxMaxBurst_End
2463 nop
2464SetTxMaxBurst_DMA7:
2465 setx SetTxMaxBurst_DMA7_Addr, %l7, %l0
2466 ba SetTxMaxBurst_End
2467 nop
2468SetTxMaxBurst_DMA8:
2469 setx SetTxMaxBurst_DMA8_Addr, %l7, %l0
2470 ba SetTxMaxBurst_End
2471 nop
2472SetTxMaxBurst_DMA9:
2473 setx SetTxMaxBurst_DMA9_Addr, %l7, %l0
2474 ba SetTxMaxBurst_End
2475 nop
2476SetTxMaxBurst_DMA10:
2477 setx SetTxMaxBurst_DMA10_Addr, %l7, %l0
2478 ba SetTxMaxBurst_End
2479 nop
2480SetTxMaxBurst_DMA11:
2481 setx SetTxMaxBurst_DMA11_Addr, %l7, %l0
2482 ba SetTxMaxBurst_End
2483 nop
2484SetTxMaxBurst_DMA12:
2485 setx SetTxMaxBurst_DMA12_Addr, %l7, %l0
2486 ba SetTxMaxBurst_End
2487 nop
2488SetTxMaxBurst_DMA13:
2489 setx SetTxMaxBurst_DMA13_Addr, %l7, %l0
2490 ba SetTxMaxBurst_End
2491 nop
2492SetTxMaxBurst_DMA14:
2493 setx SetTxMaxBurst_DMA14_Addr, %l7, %l0
2494 ba SetTxMaxBurst_End
2495 nop
2496SetTxMaxBurst_DMA15:
2497 setx SetTxMaxBurst_DMA15_Addr, %l7, %l0
2498 ba SetTxMaxBurst_End
2499 nop
2500SetTxMaxBurst_DMA16:
2501 setx SetTxMaxBurst_DMA16_Addr, %l7, %l0
2502 ba SetTxMaxBurst_End
2503 nop
2504SetTxMaxBurst_DMA17:
2505 setx SetTxMaxBurst_DMA17_Addr, %l7, %l0
2506 ba SetTxMaxBurst_End
2507 nop
2508SetTxMaxBurst_DMA18:
2509 setx SetTxMaxBurst_DMA18_Addr, %l7, %l0
2510 ba SetTxMaxBurst_End
2511 nop
2512SetTxMaxBurst_DMA19:
2513 setx SetTxMaxBurst_DMA19_Addr, %l7, %l0
2514 ba SetTxMaxBurst_End
2515 nop
2516SetTxMaxBurst_DMA20:
2517 setx SetTxMaxBurst_DMA20_Addr, %l7, %l0
2518 ba SetTxMaxBurst_End
2519 nop
2520SetTxMaxBurst_DMA21:
2521 setx SetTxMaxBurst_DMA21_Addr, %l7, %l0
2522 ba SetTxMaxBurst_End
2523 nop
2524SetTxMaxBurst_DMA22:
2525 setx SetTxMaxBurst_DMA22_Addr, %l7, %l0
2526 ba SetTxMaxBurst_End
2527 nop
2528SetTxMaxBurst_DMA23:
2529 setx SetTxMaxBurst_DMA23_Addr, %l7, %l0
2530 ba SetTxMaxBurst_End
2531 nop
2532
2533SetTxMaxBurst_End:
2534 stxa %i1, [%l0]ASI_PRIMARY_LITTLE
2535
2536 ret
2537 restore
2538
2539.global SetTxDMAActive
2540SetTxDMAActive:
2541 save
2542 brgz %i0, SetPort1DMAActive
2543 nop
2544 setx SetPort0TxDMAActive_Addr, %l7, %l0
2545 ba SetTxDMAActive_End
2546 nop
2547SetPort1DMAActive :
2548 setx SetPort1TxDMAActive_Addr, %l7, %l0
2549SetTxDMAActive_End :
2550 stxa %i1, [%l0]ASI_PRIMARY_LITTLE
2551
2552 ret
2553 restore
2554
2555.global InitTxDma
2556InitTxDma:
2557 save
2558SetPage0Registers:
2559
2560P_SetTxLPMask1:
2561 mov %i0, %o0
2562 mulx %o0, 0x200, %l2
2563 setx TX_LOG_MASK1_Addr, %l7, %l3
2564 add %l3, %l2, %l3
2565#ifdef XLATE_ON
2566 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_MASK1, %l7, %l0
2567#ifdef FC_NO_PEU_VERA
2568 ! PEP does not support 64-bit access, so use two 32-bit loads
2569 lduw [%l0], %l1
2570 lduw [%l0+4], %l2
2571 sllx %l1, 32, %l1
2572 add %l2, %l1, %l1
2573#else // FC_NO_PEU_VERA
2574 ldx [%l0], %l1
2575#endif // FC_NO_PEU_VERA
2576 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2577#else
2578 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2579#endif // XLATE_ON
2580
2581P_SetTxLPValue1:
2582 mulx %o0, 0x200, %l2
2583 setx TX_LOG_VALUE1_Addr, %l7, %l3
2584 add %l3, %l2, %l3
2585#ifdef XLATE_ON
2586 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_VALUE1, %l7, %l0
2587#ifdef FC_NO_PEU_VERA
2588 ! PEP does not support 64-bit access, so use two 32-bit loads
2589 lduw [%l0], %l1
2590 lduw [%l0+4], %l2
2591 sllx %l1, 32, %l1
2592 add %l2, %l1, %l1
2593#else // FC_NO_PEU_VERA
2594 ldx [%l0], %l1
2595#endif // FC_NO_PEU_VERA
2596 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2597#else
2598 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2599#endif // XLATE_ON
2600
2601P_SetTxLPRELOC1:
2602 mulx %o0, 0x200, %l2
2603 setx TX_LOG_PAGE_RELO1_Addr, %l7, %l3
2604 add %l3, %l2, %l3
2605#ifdef XLATE_ON
2606 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_RELO1, %l7, %l0
2607#ifdef FC_NO_PEU_VERA
2608 ! PEP does not support 64-bit access, so use two 32-bit loads
2609 lduw [%l0], %l1
2610 lduw [%l0+4], %l2
2611 sllx %l1, 32, %l1
2612 add %l2, %l1, %l1
2613#else // FC_NO_PEU_VERA
2614 ldx [%l0], %l1
2615#endif // FC_NO_PEU_VERA
2616 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2617#else
2618 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2619#endif // XLATE_ON
2620
2621
2622SetPage1Registers:
2623
2624P_SetTxLPMask2:
2625 mulx %o0, 0x200, %l2
2626 setx TX_LOG_MASK2_Addr, %l7, %l3
2627 add %l3, %l2, %l3
2628#ifdef XLATE_ON
2629 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_MASK2, %l7, %l0
2630#ifdef FC_NO_PEU_VERA
2631 ! PEP does not support 64-bit access, so use two 32-bit loads
2632 lduw [%l0], %l1
2633 lduw [%l0+4], %l2
2634 sllx %l1, 32, %l1
2635 add %l2, %l1, %l1
2636#else // FC_NO_PEU_VERA
2637 ldx [%l0], %l1
2638#endif // FC_NO_PEU_VERA
2639 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2640#else
2641 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2642#endif // XLATE_ON
2643
2644P_SetTxLPValue2:
2645 mulx %o0, 0x200, %l2
2646 setx TX_LOG_VALUE2_Addr, %l7, %l3
2647 add %l3, %l2, %l3
2648#ifdef XLATE_ON
2649 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_VALUE2, %l7, %l0
2650#ifdef FC_NO_PEU_VERA
2651 ! PEP does not support 64-bit access, so use two 32-bit loads
2652 lduw [%l0], %l1
2653 lduw [%l0+4], %l2
2654 sllx %l1, 32, %l1
2655 add %l2, %l1, %l1
2656#else // FC_NO_PEU_VERA
2657 ldx [%l0], %l1
2658#endif // FC_NO_PEU_VERA
2659 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2660#else
2661 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2662#endif // XLATE_ON
2663
2664P_SetTxLPRELOC2:
2665 mulx %o0, 0x200, %l2
2666 setx TX_LOG_PAGE_RELO2_Addr, %l7, %l3
2667 add %l3, %l2, %l3
2668#ifdef XLATE_ON
2669 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_RELO2, %l7, %l0
2670#ifdef FC_NO_PEU_VERA
2671 ! PEP does not support 64-bit access, so use two 32-bit loads
2672 lduw [%l0], %l1
2673 lduw [%l0+4], %l2
2674 sllx %l1, 32, %l1
2675 add %l2, %l1, %l1
2676#else // FC_NO_PEU_VERA
2677 ldx [%l0], %l1
2678#endif // FC_NO_PEU_VERA
2679 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2680#else
2681 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2682#endif // XLATE_ON
2683
2684SetPageEnables:
2685
2686P_SetTxLPValid:
2687 setx NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_VLD, %l7, %l0
2688#ifdef FC_NO_PEU_VERA
2689 ! PEP does not support 64-bit access, so use two 32-bit loads
2690 lduw [%l0], %l1
2691 lduw [%l0+4], %l2
2692 sllx %l1, 32, %l1
2693 add %l2, %l1, %l1
2694#else // FC_NO_PEU_VERA
2695 ldx [%l0], %l1
2696#endif // FC_NO_PEU_VERA
2697 mulx %o0, 0x200, %l2
2698 setx TX_LOG_PAGE_VLD_Addr, %l7, %l0
2699 add %l0, %l2, %l0
2700 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2701
2702
2703SetRngConfig:
2704 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_CFIG, %l7, %l0
2705#ifdef FC_NO_PEU_VERA
2706 ! PEP does not support 64-bit access, so use two 32-bit loads
2707 lduw [%l0], %l1
2708 lduw [%l0+4], %l2
2709 sllx %l1, 32, %l1
2710 add %l2, %l1, %l1
2711#else // FC_NO_PEU_VERA
2712 ldx [%l0], %l1
2713#endif // FC_NO_PEU_VERA
2714 mulx %o0, 0x200, %l2
2715 setx TX_RNG_CFIG_Addr, %l7, %l0
2716 add %l0, %l2, %l0
2717 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2718
2719 ret
2720 restore ! Return InitTxDMA
2721#endif
2722
2723!/********************************************************************************
2724!* NiuInitRxDma:
2725!* This routine programs the receive DMA channel.
2726!* setup_zcp_tbl programs the DMA channel in ZCP block per enabled dma
2727!* parameters. If "MULTI_TEST" is not present, then it program the dma channel
2728!* for single dma for the existing tests (single-port/single-dma).
2729!* NIURX_SetPage0Registers programs the following registers in RDMC block.
2730!* The user event first writes the value of these registers in PEU_SRAM via back
2731!* door. Then the assembly retrieves the data from the PEU_SRAM
2732!* and programs the registers.
2733!* RX_MASK1_START
2734!* RX_VALID1_START
2735!* RX_RELOC1_START
2736!* RX_MASK2_START
2737!* RX_VALID2_START
2738!* RX_RELOC2_START
2739!* RX_PAGE_VALID
2740!* RBR_CFIG_A
2741!* RBR_CFIG_B
2742!* RCR_CFIG_A
2743!* RXDMA_CFIG1
2744!* RXDMA_CFIG2_START
2745!* RXDMA_CFIG1
2746!* RBR_KICK
2747!*
2748!* Parameters in registers:
2749!* %o0: ???
2750!* %o6: ???
2751!********************************************************************************/
2752.global NiuInitRxDma
2753NiuInitRxDma:
2754 save
2755 mov %i0, %o0
2756 mov %i6, %o6
2757! call setup_zcp_tbl
2758! nop
2759
2760
2761
2762#ifdef MULTI_TEST
2763setup_zcp_tbl:
2764! mov %i0, %o0
2765! mov %i6, %o6
2766
2767 brz %i6, 2f
2768 nop
2769prog_zcp_tbl:
2770 call init_zcp_tbl_8dma
2771 nop
27722:
2773#else
2774NIURx_SetZcpRdc:
2775! setx RXDMA_CHNL, %l7, %g3
2776! save
2777 setx ZCP_RDC_TBL_Addr, %l7, %l0
2778 stxa %i0, [%l0]ASI_PRIMARY_LITTLE
2779
2780 add 0x100, %l0, %l0
2781 stxa %i0, [%l0]ASI_PRIMARY_LITTLE
2782
2783 add 0x200, %l0, %l0
2784 stxa %i0, [%l0]ASI_PRIMARY_LITTLE
2785
2786 add 0x200, %l0, %l0
2787 stxa %i0, [%l0]ASI_PRIMARY_LITTLE
2788
2789 add 0x200, %l0, %l0
2790 stxa %i0, [%l0]ASI_PRIMARY_LITTLE
2791
2792! ret
2793! restore
2794#endif
2795NIURX_SetPage0Registers:
2796P_SetRxLogMask1:
2797 mulx %o0, 0x40, %l2
2798 setx RX_LOG_MASK1_START_Addr, %l7, %l3
2799 add %l3, %l2, %l3
2800#ifdef XLATE_ON
2801 setx NIU_PKTGEN_CSR_EV2A_RX_LOG_MASK1, %l7, %l0
2802#ifdef FC_NO_PEU_VERA
2803 ! PEP does not support 64-bit access, so use two 32-bit loads
2804 lduw [%l0], %l1
2805 lduw [%l0+4], %l2
2806 sllx %l1, 32, %l1
2807 add %l2, %l1, %l1
2808#else // FC_NO_PEU_VERA
2809 ldx [%l0], %l1
2810#endif // FC_NO_PEU_VERA
2811 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2812#else
2813 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2814#endif // XLATE_ON
2815
2816P_SetRxLogVal1:
2817 mulx %o0, 0x40, %l2
2818 setx RX_LOG_VAL1_START_Addr, %l7, %l3
2819 add %l3, %l2, %l3
2820#ifdef XLATE_ON
2821 setx NIU_PKTGEN_CSR_EV2A_RX_LOG_VAL1, %l7, %l0
2822#ifdef FC_NO_PEU_VERA
2823 ! PEP does not support 64-bit access, so use two 32-bit loads
2824 lduw [%l0], %l1
2825 lduw [%l0+4], %l2
2826 sllx %l1, 32, %l1
2827 add %l2, %l1, %l1
2828#else // FC_NO_PEU_VERA
2829 ldx [%l0], %l1
2830#endif // FC_NO_PEU_VERA
2831 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2832#else
2833 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2834#endif // XLATE_ON
2835
2836P_SetRxLogRelo1:
2837 mulx %o0, 0x40, %l2
2838 setx RX_LOG_RELO1_START_Addr, %l7, %l3
2839 add %l3, %l2, %l3
2840#ifdef XLATE_ON
2841 setx NIU_PKTGEN_CSR_EV2A_RX_LOG_RELO1, %l7, %l0
2842#ifdef FC_NO_PEU_VERA
2843 ! PEP does not support 64-bit access, so use two 32-bit loads
2844 lduw [%l0], %l1
2845 lduw [%l0+4], %l2
2846 sllx %l1, 32, %l1
2847 add %l2, %l1, %l1
2848#else // FC_NO_PEU_VERA
2849 ldx [%l0], %l1
2850#endif // FC_NO_PEU_VERA
2851 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2852#else
2853 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2854#endif // XLATE_ON
2855
2856NIURX_SetPage1Registers:
2857P_SetRxLogMask2:
2858 mulx %o0, 0x40, %l2
2859 setx RX_LOG_MASK2_START_Addr, %l7, %l3
2860 add %l3, %l2, %l3
2861#ifdef XLATE_ON
2862 setx NIU_PKTGEN_CSR_EV2A_RX_LOG_MASK2, %l7, %l0
2863#ifdef FC_NO_PEU_VERA
2864 ! PEP does not support 64-bit access, so use two 32-bit loads
2865 lduw [%l0], %l1
2866 lduw [%l0+4], %l2
2867 sllx %l1, 32, %l1
2868 add %l2, %l1, %l1
2869#else // FC_NO_PEU_VERA
2870 ldx [%l0], %l1
2871#endif // FC_NO_PEU_VERA
2872 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2873#else
2874 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2875#endif // XLATE_ON
2876
2877P_SetRxLogVal2:
2878 mulx %o0, 0x40, %l2
2879 setx RX_LOG_VAL2_START_Addr, %l7, %l3
2880 add %l3, %l2, %l3
2881#ifdef XLATE_ON
2882 setx NIU_PKTGEN_CSR_EV2A_RX_LOG_VAL2, %l7, %l0
2883#ifdef FC_NO_PEU_VERA
2884 ! PEP does not support 64-bit access, so use two 32-bit loads
2885 lduw [%l0], %l1
2886 lduw [%l0+4], %l2
2887 sllx %l1, 32, %l1
2888 add %l2, %l1, %l1
2889#else // FC_NO_PEU_VERA
2890 ldx [%l0], %l1
2891#endif // FC_NO_PEU_VERA
2892 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2893#else
2894 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2895#endif // XLATE_ON
2896
2897P_SetRxLogRelo2:
2898 mulx %o0, 0x40, %l2
2899 setx RX_LOG_RELO2_START_Addr, %l7, %l3
2900 add %l3, %l2, %l3
2901#ifdef XLATE_ON
2902 setx NIU_PKTGEN_CSR_EV2A_RX_LOG_RELO2, %l7, %l0
2903#ifdef FC_NO_PEU_VERA
2904 ! PEP does not support 64-bit access, so use two 32-bit loads
2905 lduw [%l0], %l1
2906 lduw [%l0+4], %l2
2907 sllx %l1, 32, %l1
2908 add %l2, %l1, %l1
2909#else // FC_NO_PEU_VERA
2910 ldx [%l0], %l1
2911#endif // FC_NO_PEU_VERA
2912 stxa %l1, [%l3]ASI_PRIMARY_LITTLE
2913#else
2914 stxa %g0, [%l3]ASI_PRIMARY_LITTLE
2915#endif // XLATE_ON
2916
2917P_SetRxLogPgVld:
2918 setx NIU_PKTGEN_CSR_EV2A_RX_LOG_PAGE_VLD, %l7, %l0
2919#ifdef FC_NO_PEU_VERA
2920 ! PEP does not support 64-bit access, so use two 32-bit loads
2921 lduw [%l0], %l1
2922 lduw [%l0+4], %l2
2923 sllx %l1, 32, %l1
2924 add %l2, %l1, %l1
2925#else // FC_NO_PEU_VERA
2926 ldx [%l0], %l1
2927#endif // FC_NO_PEU_VERA
2928 mulx %o0, 0x40, %l2
2929 setx RX_LOG_PAGE_VLD_Addr, %l7, %l0
2930 add %l0, %l2, %l0
2931 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2932
2933P_SetRbrConfig_A:
2934 setx NIU_PKTGEN_CSR_EV2A_RBR_CFIG_A, %l7, %l0
2935#ifdef FC_NO_PEU_VERA
2936 ! PEP does not support 64-bit access, so use two 32-bit loads
2937 lduw [%l0], %l1
2938 lduw [%l0+4], %l2
2939 sllx %l1, 32, %l1
2940 add %l2, %l1, %l1
2941#else // FC_NO_PEU_VERA
2942 ldx [%l0], %l1
2943#endif // FC_NO_PEU_VERA
2944 mulx %o0, 0x200, %l2
2945 setx RBR_CFIG_A_Addr, %l7, %l0
2946 add %l0, %l2, %l0
2947 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2948
2949P_SetRbrConfig_B:
2950 setx NIU_PKTGEN_CSR_EV2A_RBR_CFIG_B, %l7, %l0
2951#ifdef FC_NO_PEU_VERA
2952 ! PEP does not support 64-bit access, so use two 32-bit loads
2953 lduw [%l0], %l1
2954 lduw [%l0+4], %l2
2955 sllx %l1, 32, %l1
2956 add %l2, %l1, %l1
2957#else // FC_NO_PEU_VERA
2958 ldx [%l0], %l1
2959#endif // FC_NO_PEU_VERA
2960 mulx %o0, 0x200, %l2
2961 setx RBR_CFIG_B_Addr, %l7, %l0
2962 add %l0, %l2, %l0
2963 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2964
2965P_SetRcrConfig_A:
2966 setx NIU_PKTGEN_CSR_EV2A_RCR_CFIG_A, %l7, %l0
2967#ifdef FC_NO_PEU_VERA
2968 ! PEP does not support 64-bit access, so use two 32-bit loads
2969 lduw [%l0], %l1
2970 lduw [%l0+4], %l2
2971 sllx %l1, 32, %l1
2972 add %l2, %l1, %l1
2973#else // FC_NO_PEU_VERA
2974 ldx [%l0], %l1
2975#endif // FC_NO_PEU_VERA
2976 mulx %o0, 0x200, %l2
2977 setx RCR_CFIG_A_Addr, %l7, %l0
2978 add %l0, %l2, %l0
2979 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2980
2981P_SetRxDmaCfig_1_0:
2982 setx NIU_PKTGEN_CSR_EV2A_RXDMA_CFIG1_0, %l7, %l0
2983#ifdef FC_NO_PEU_VERA
2984 ! PEP does not support 64-bit access, so use two 32-bit loads
2985 lduw [%l0], %l1
2986 lduw [%l0+4], %l2
2987 sllx %l1, 32, %l1
2988 add %l2, %l1, %l1
2989#else // FC_NO_PEU_VERA
2990 ldx [%l0], %l1
2991#endif // FC_NO_PEU_VERA
2992 mulx %o0, 0x200, %l2
2993 setx RXDMA_CFIG1_Addr, %l7, %l0
2994 add %l0, %l2, %l0
2995 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
2996
2997P_SetRxdmaCfig2Start:
2998 setx NIU_PKTGEN_CSR_EV2A_RXDMA_CFIG2, %l7, %l0
2999#ifdef FC_NO_PEU_VERA
3000 ! PEP does not support 64-bit access, so use two 32-bit loads
3001 lduw [%l0], %l1
3002 lduw [%l0+4], %l2
3003 sllx %l1, 32, %l1
3004 add %l2, %l1, %l1
3005#else // FC_NO_PEU_VERA
3006 ldx [%l0], %l1
3007#endif // FC_NO_PEU_VERA
3008 mulx %o0, 0x200, %l2
3009 setx RXDMA_CFIG2_START_Addr, %l7, %l0
3010 add %l0, %l2, %l0
3011 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
3012
3013P_SetRxDmaCfig_1_1:
3014 setx NIU_PKTGEN_CSR_EV2A_RXDMA_CFIG1_1, %l7, %l0
3015#ifdef FC_NO_PEU_VERA
3016 ! PEP does not support 64-bit access, so use two 32-bit loads
3017 lduw [%l0], %l1
3018 lduw [%l0+4], %l2
3019 sllx %l1, 32, %l1
3020 add %l2, %l1, %l1
3021#else // FC_NO_PEU_VERA
3022 ldx [%l0], %l1
3023#endif // FC_NO_PEU_VERA
3024 mulx %o0, 0x200, %l2
3025 setx RXDMA_CFIG1_Addr, %l7, %l0
3026 add %l0, %l2, %l0
3027 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
3028
3029P_SetRxRingKick:
3030 setx NIU_PKTGEN_CSR_EV2A_RBR_KICK, %l7, %l0
3031#ifdef FC_NO_PEU_VERA
3032 ! PEP does not support 64-bit access, so use two 32-bit loads
3033 lduw [%l0], %l1
3034 lduw [%l0+4], %l2
3035 sllx %l1, 32, %l1
3036 add %l2, %l1, %l1
3037#else // FC_NO_PEU_VERA
3038 ldx [%l0], %l1
3039#endif // FC_NO_PEU_VERA
3040 mulx %o0, 0x200, %l2
3041 setx RBR_KICK_Addr, %l7, %l0
3042 add %l0, %l2, %l0
3043 stxa %l1, [%l0]ASI_PRIMARY_LITTLE
3044
3045 ret
3046 restore ! Return NiuInitRxDma
3047
3048!/********************************************************************************
3049!* NiuTx_check_pkt_cnt:
3050!* ???
3051!* Parameters in registers:
3052!* %o0: MAC id
3053!* %o1: Expected number of TX packets
3054!********************************************************************************/
3055.global NiuTx_check_pkt_cnt
3056NiuTx_check_pkt_cnt:
3057 save
3058 mov %i0, %o0 ! %i0 = Mac_id
3059 clr %l6
3060 clr %i3
3061 mov Time_out, %i2
3062
3063 setx TXC_PKT_XMIT_Addr, %l7, %l0
3064 mulx %o0, 0x100, %l2
3065 add %l0, %l2, %l0
3066 setx TXC_PKT_XMIT_Mask, %l7, %l4
3067
3068loop_XMIT_Rd:
3069 clr %i3
3070loop_timeout_XMIT_Rd:
3071 ldxa [%l0]ASI_PRIMARY_LITTLE, %l1
3072
3073 and %l1, %l4, %l1
3074 cmp %i1, %l1 ! %i1 2nd parameter no. of Tx pkts
3075 be Count_match
3076 nop
3077 cmp %l1, %l6
3078 bne loop_XMIT_Rd
3079 mov %l1, %l6 ! save a copy
3080
3081 inc %i3
3082
3083 call delay_1
3084 nop
3085
3086 cmp %i2, %i3 ! %i2 = Timeout value; %i3 = Timeout counter
3087 bne loop_timeout_XMIT_Rd
3088 nop
3089NIUTxcPktXmitTimeout:
3090! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.NIUTxcPktXmitTimeout) + 4, 16, 16)) -> printf("ERROR : NIUTxcPktXmitTimeout",*,1)
3091 call Timeout
3092 nop
3093
3094Count_match:
3095! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.Count_match) + 8, 16, 16)) -> printf("Tx Count Match",*,1)
3096
3097#if (MAC_SPEED0==1000) && (MAC_SPEED1==1000) /* Extra delay for 1G after the last packet is DMA-ed */
3098 call delay_10
3099 nop
3100
3101 call delay_10
3102 nop
3103#endif /* (MAC_SPEED0==1000) && (MAC_SPEED1==1000) */
3104 ret
3105 restore ! Return NiuTx_check_pkt_cnt:
3106
3107
3108/* ************************************************************************
3109 .global Check_NIU_Int
3110Check_NIU_Int:
3111 save
3112 mov %i0, %o0 ! %i0 = Mac_id
3113 clr %l6
3114 clr %i3
3115 mov NIU_Trap_TimeOut, %i2
3116
3117 setx 0x300000000, %l7, %l0
3118
3119loop_NIU_Trap_Rd:
3120 clr %i3
3121loop_timeout_NIU_Trap_Rd:
3122 ldxa [%l0]ASI_PRIMARY_LITTLE, %l1
3123
3124 cmp %i1, %l1 ! %i1 2nd parameter no. of Tx pkts
3125 be NIU_Trap_Count_match
3126 nop
3127 cmp %l1, %l6
3128 bne loop_NIU_Trap_Rd
3129 mov %l1, %l6 ! save a copy
3130
3131 inc %i3
3132
3133 call delay_1
3134 nop
3135
3136 cmp %i2, %i3 ! %i2 = Timeout value; %i3 = Timeout counter
3137 bne loop_timeout_NIU_Trap_Rd
3138 nop
3139NIU_Trap_TimeOut:
3140! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.NIU_Trap_TimeOut) + 4, 16, 16)) -> printf("ERROR : NIU_Trap_TimeOut",*,1)
3141 call Timeout
3142 nop
3143
3144NIU_Trap_Count_match:
3145! $EV trig_pc_d(1, expr(@VA(.RED_EXT_SEC.Count_match) + 8, 16, 16)) -> printf("NIU Trap Count Match",*,1)
3146
3147 ret
3148 restore ! Return Check_NIU_Int
3149
3150 ************************************************************************ */
3151.global test_failed
3152test_failed:
3153 EXIT_BAD
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