projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: peu_init_dtm.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | ! Per DH suggestion, before any PIO access to PCI-E addr space, need to setup | |
| 39 | ! Base and Mask registers in NCU. Copied the code below from ./peu_init.h | |
| 40 | ! - AT, 02/28/06 | |
| 41 | ||
| 42 | #include "peu_defines.h" | |
| 43 | #include "dmu_peu_regs.h" | |
| 44 | ||
| 45 | ! | |
| 46 | ! Set up the Base and Mask registers in the NCU to enable PIO reads and writes | |
| 47 | ! | |
| 48 | setx MEM32_OFFSET_BASE_REG_ADDR, %g2, %g3 ! 0x8000002000 | |
| 49 | setx MEM32_OFFSET_BASE_REG_DATA, %g2, %g4 | |
| 50 | stx %g4, [%g3] | |
| 51 | ||
| 52 | !setx MEM32_OFFSET_MASK_REG_ADDR, %g2, %g3 ! 0x8000002008 | |
| 53 | setx MEM32_OFFSET_MASK_REG_DATA, %g2, %g4 | |
| 54 | stx %g4, [%g3 + 0x8] | |
| 55 | ||
| 56 | !setx MEM64_OFFSET_BASE_REG_ADDR, %g2, %g3 ! 0x8000002010 | |
| 57 | setx MEM64_OFFSET_BASE_REG_DATA, %g2, %g4 | |
| 58 | stx %g4, [%g3 + 0x10] | |
| 59 | ||
| 60 | !setx MEM64_OFFSET_MASK_REG_ADDR, %g2, %g3 ! 0x8000002018 | |
| 61 | setx MEM64_OFFSET_MASK_REG_DATA, %g2, %g4 | |
| 62 | stx %g4, [%g3 + 0x18] | |
| 63 | ||
| 64 | !setx IOCFG_OFFSET_BASE_REG_ADDR, %g2, %g3 ! 0x8000002020 | |
| 65 | setx IOCFG_OFFSET_BASE_REG_DATA, %g2, %g4 | |
| 66 | stx %g4, [%g3 + 0x20] | |
| 67 | ||
| 68 | !setx IOCFG_OFFSET_MASK_REG_ADDR, %g2, %g3 ! 0x8000002028 | |
| 69 | setx IOCFG_OFFSET_MASK_REG_DATA, %g2, %g4 | |
| 70 | stx %g4, [%g3 + 0x28] | |
| 71 | ||
| 72 | ! Load the PCIE MEM64 OFFSET Register (and pio deadlock mode bits) | |
| 73 | ||
| 74 | setx FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR, %g2, %g3 | |
| 75 | #ifndef PEU_PIO_MODE | |
| 76 | #define PCIE_MEM64_OFFSET_PLUS_PIO_MODE PCIE_MEM64_OFFSET | |
| 77 | #else | |
| 78 | #define PCIE_MEM64_OFFSET_PLUS_PIO_MODE mpeval(PCIE_MEM64_OFFSET | (PEU_PIO_MODE & 3)) | |
| 79 | #endif | |
| 80 | setx PCIE_MEM64_OFFSET_PLUS_PIO_MODE, %g2, %g4 | |
| 81 | stx %g4, [%g3] | |
| 82 | ||
| 83 | ! ! enable bypass in IOMMU | |
| 84 | ||
| 85 | ! setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g2, %g3 | |
| 86 | ! mov FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g4 | |
| 87 | ! stx %g4, [%g3] |