[OpenSPARC-T2-DV] / verif / diag / assembly / include / piu_rupt_enable.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: piu_rupt_enable.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
no_intr:
        rdpr    %pstate, %g7
        xor     %g7, 0x2, %g7           ! Reset interrupt enable
        wrpr    %g7, %pstate

	! Initialize NCU's Mondo Interrupt Vector Register
	! VECTOR = 63

ncu_mondo_int_vec:
	set	63, %g1
	setx	MONDO_INT_VEC, %g2, %g3
	stx	%g1, [%g3]

	! Clear NCU's Mondo Interrupt Busy registers.

ncu_mondo_int_busy:
	setx	MONDO_INT_ABUSY, %g1, %g2
	stx	%g0, [%g2]

	! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.

mmu_intr_enable_reg_init:
	setx	PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
	set	0, %g4
	dec	%g4			! all 1s
	stx	%g4, [%g2]

	! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.

imu_intr_enable_reg_init:
	setx	PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
	stx	%g4, [%g2]

        ! Initialize Interrupt Mapping register for Mondos 62 and 63
	! Valid, thread ID 0, no interrupt controller

dmu_intr_map_reg_init:
        setx    PCI_E_INT_MAP_ADDR, %g1, %g7
        setx    PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
        add     %g7, %g3, %g7
        best_set_reg(0x80000040, %g1, %g6)      ! valid = 1, thread id = 0	
#ifdef PORTABLE_CORE
	ldxa	[%g0] ASI_INTR_ID, %l7
	and	%l7, 0x38, %l7			! %l7 = core ID, not thread ID
	sllx	%l7, PCI_E_INT_MAP_THREADID_SHIFT, %l7
	or	%l7, %g6, %g6			! Use core ID of core running on
#endif
        stx     %g6, [%g7]                      ! interrupt controller = 1

        add     %g7, PCI_E_INT_MAP_STEP, %g7
        !setx    0x80000040, %g1, %g6           ! valid = 1, thread id = 0
        stx     %g6, [%g7]                      ! interrupt controller = 1
	

yes_intr:
        rdpr    %pstate, %g7
        or      %g7, 0x2, %g7           ! Set interrupt enable
        wrpr    %g7, %pstate

	! Enable IMU, MMU interrupts in the DMU Core and Block
	! Interrupt Enable register.

dmu_core_block_enable:
	setx	PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
	setx	mpeval(PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK |PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK | PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK), %g1, %g3
	stx	%g3, [%g2]

peu_uncorrectable_err_enable:
	setx	PCI_E_PEU_UE_INT_ENB_ADDR, %g1, %g2
	stx	%g4, [%g2+0x10]		! clear interrupt status bits
	stx	%g4, [%g2]		! set interrupt enables
		
peu_correctable_err_enable:
	setx	PCI_E_PEU_CE_INT_ENB_ADDR, %g1, %g2
	stx	%g4, [%g2+0x10]		! clear interrupt status bits
	stx	%g4, [%g2]		! set interrupt enables
		
peu_dlpl_error_enable:
	setx	PCI_E_PEU_DLPL_INT_ENB_ADDR, %g1, %g2
	best_set_reg(0x0003ffff, %g1, %g4)
	stx	%g4, [%g2+0x10]		! clear interrupt status bits
	stx	%g4, [%g2]		! set interrupt enables
		
peu_other_err_enable:
	setx	PCI_E_PEU_OTHER_INT_ENB_ADDR, %g1, %g2
	stx	%g4, [%g2+0x10]		! clear interrupt status bits
	stx	%g4, [%g2]		! set interrupt enables
		
peu_core_block_enable:
	setx	PCI_E_PEU_INT_ENB_ADDR, %g1, %g2
	stx	%g4, [%g2+0x10]		! clear interrupt status bits
	stx	%g4, [%g2]		! set interrupt enables
		
ilu_block_enable:
	setx	PCI_E_ILU_INT_ENB_ADDR, %g1, %g2
	stx	%g4, [%g2]		! set block enables
		
	membar	#Sync

	b       trap_end
	nop
	
/**********************************************************************
   Interrupt trap handler.
**********************************************************************/
	.align 64
.global my_trap_code
my_trap_code:

	! read DMU error status registers
	
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %g3 ! 631000
	ldx	[%g3+0x808], %l7			! 631808 - DMU Core and Block Error Status Reg
	cmp     %l7, 0
	bz	read_peu_error_regs			! if 0, must be a PEU interrupt
	
	and	%l7, 0x2, %g4				! test if the MMU has an interrupt
	cmp     %g4, 0
	bnz     read_mmu_error_regs
	nop
	
read_imu_error_regs:
	ldx	[%g3+0x10], %l3				! 631010 - IMU Interrupt Status Reg
	ldx	[%g3+0x28], %l4				! 631028 - IMU RDS Error Log Reg
	ldx	[%g3+0x30], %l5				! 631030 - IMU SCS Error Log Reg
	ldx	[%g3+0x38], %l6				! 631038 - IMU EQS Error Log Reg
	b	test_failed				! No errors expected - go to bad trap
	nop
	
read_mmu_error_regs:
	setx	FIRE_DLC_MMU_CSR_A_LOG_ADDR, %g1, %g2	! 641000
	ldx	[%g2+0x10], %l0				! 641010 - MMU Interrupt Status Reg
	ldx	[%g2+0x28], %l1				! 641028 - MMU Translation Fault Address Reg
	ldx	[%g2+0x30], %l2				! 641030 - MMU Translation Fault Status Reg
	b	test_failed				! No errors expected - go to bad trap
	nop
	
	! read PEU error status registers
	
read_peu_error_regs:
	setx	FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR, %g1, %g3	! 651000
	ldx	[%g3+0x808], %l7			! 651808 - PEU Core and Block Interrupt Status Reg
	cmp     %l7, 0
	bz	test_failed				! one of the bits should have been set
	
	and	%l7, 0x8, %g4				! test if the ILU has an interrupt
	cmp     %g4, 0
	bnz     read_ilu_error_regs
	
	and	%l7, 0x4, %g4				! test if its an Uncorrectable error from PEU
	cmp     %g4, 0
	bnz     read_ue_error_regs
	
	and	%l7, 0x2, %g4				! test if its a Correctable error from PEU
	cmp     %g4, 0
	bnz     read_ce_error_regs
	nop

read_oe_error_regs:
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR, %g1, %g3	! 681000
	ldx	[%g3+0x10], %l0				! 681010 - PEU OE Status Reg
	and	%l0, 0x800, %l1				! test if its a Correctable error from PEU
	cmp     %l1, 0
	bnz     read_dlpl_error_regs
	nop
	ldx	[%g2+0x28], %l1				! 681028 - PEU OE Rx Hdr1 Log Reg
	ldx	[%g2+0x30], %l2				! 681030 - PEU OE Rx Hdr2 Log Reg
	ldx	[%g2+0x38], %l3				! 681038 - PEU OE Tx Hdr1 Log Reg
	ldx	[%g2+0x40], %l4				! 681040 - PEU OE Tx Hdr2 Log Reg
	b	test_failed				! No errors expected - go to bad trap
	nop

read_ue_error_regs:
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR, %g1, %g3	! 691000
	ldx	[%g3+0x10], %l0				! 691010 - PEU UE Status Reg
	ldx	[%g2+0x28], %l1				! 691028 - PEU UE Rx Hdr1 Log Reg
	ldx	[%g2+0x30], %l2				! 691030 - PEU UE Rx Hdr2 Log Reg
	ldx	[%g2+0x38], %l3				! 691038 - PEU UE Tx Hdr1 Log Reg
	ldx	[%g2+0x40], %l4				! 691040 - PEU UE Tx Hdr2 Log Reg
	b	test_failed				! No errors expected - go to bad trap
	nop

read_ce_error_regs:
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR, %g1, %g3	! 6a1000
	ldx	[%g3+0x10], %l0				! 6a1010 - PEU CE Status Reg
	b	test_failed				! No errors expected - go to bad trap
	nop

read_dlpl_error_regs:
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g3	! 6e2100
	ldx	[%g3+0x18], %l1				! 6e2118 - PEU DLPL Status Reg
	b	test_failed				! No errors expected - go to bad trap
	nop

read_ilu_error_regs:
	ldx	[%g3+0x10], %l0				! 651010 - ILU Interrupt Status Reg
	b	test_failed				! No errors expected - go to bad trap
	nop
	
	.align 64
trap_end:
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: piu_rupt_enable.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	no_intr:
	39	rdpr %pstate, %g7
	40	xor %g7, 0x2, %g7 ! Reset interrupt enable
	41	wrpr %g7, %pstate
	42
	43	! Initialize NCU's Mondo Interrupt Vector Register
	44	! VECTOR = 63
	45
	46	ncu_mondo_int_vec:
	47	set 63, %g1
	48	setx MONDO_INT_VEC, %g2, %g3
	49	stx %g1, [%g3]
	50
	51	! Clear NCU's Mondo Interrupt Busy registers.
	52
	53	ncu_mondo_int_busy:
	54	setx MONDO_INT_ABUSY, %g1, %g2
	55	stx %g0, [%g2]
	56
	57	! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.
	58
	59	mmu_intr_enable_reg_init:
	60	setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
	61	set 0, %g4
	62	dec %g4 ! all 1s
	63	stx %g4, [%g2]
	64
65	! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.
66
67	imu_intr_enable_reg_init:
68	setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
69	stx %g4, [%g2]
70
71	! Initialize Interrupt Mapping register for Mondos 62 and 63
72	! Valid, thread ID 0, no interrupt controller
73
74	dmu_intr_map_reg_init:
75	setx PCI_E_INT_MAP_ADDR, %g1, %g7
76	setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
77	add %g7, %g3, %g7
78	best_set_reg(0x80000040, %g1, %g6) ! valid = 1, thread id = 0
79	#ifdef PORTABLE_CORE
80	ldxa [%g0] ASI_INTR_ID, %l7
81	and %l7, 0x38, %l7 ! %l7 = core ID, not thread ID
82	sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l7
83	or %l7, %g6, %g6 ! Use core ID of core running on
84	#endif
85	stx %g6, [%g7] ! interrupt controller = 1
86
87	add %g7, PCI_E_INT_MAP_STEP, %g7
88	!setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
89	stx %g6, [%g7] ! interrupt controller = 1
90
91
92	yes_intr:
93	rdpr %pstate, %g7
94	or %g7, 0x2, %g7 ! Set interrupt enable
95	wrpr %g7, %pstate
96
97	! Enable IMU, MMU interrupts in the DMU Core and Block
98	! Interrupt Enable register.
99
100	dmu_core_block_enable:
101	setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
102	setx mpeval(PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK \|PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK \| PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK), %g1, %g3
103	stx %g3, [%g2]
104
105	peu_uncorrectable_err_enable:
106	setx PCI_E_PEU_UE_INT_ENB_ADDR, %g1, %g2
107	stx %g4, [%g2+0x10] ! clear interrupt status bits
108	stx %g4, [%g2] ! set interrupt enables
109
110	peu_correctable_err_enable:
111	setx PCI_E_PEU_CE_INT_ENB_ADDR, %g1, %g2
112	stx %g4, [%g2+0x10] ! clear interrupt status bits
113	stx %g4, [%g2] ! set interrupt enables
114
115	peu_dlpl_error_enable:
116	setx PCI_E_PEU_DLPL_INT_ENB_ADDR, %g1, %g2
117	best_set_reg(0x0003ffff, %g1, %g4)
118	stx %g4, [%g2+0x10] ! clear interrupt status bits
119	stx %g4, [%g2] ! set interrupt enables
120
121	peu_other_err_enable:
122	setx PCI_E_PEU_OTHER_INT_ENB_ADDR, %g1, %g2
123	stx %g4, [%g2+0x10] ! clear interrupt status bits
124	stx %g4, [%g2] ! set interrupt enables
125
126	peu_core_block_enable:
127	setx PCI_E_PEU_INT_ENB_ADDR, %g1, %g2
128	stx %g4, [%g2+0x10] ! clear interrupt status bits
129	stx %g4, [%g2] ! set interrupt enables
130
131	ilu_block_enable:
132	setx PCI_E_ILU_INT_ENB_ADDR, %g1, %g2
133	stx %g4, [%g2] ! set block enables
134
135	membar #Sync
136
137	b trap_end
138	nop
139
140	/**********************************************************************
141	Interrupt trap handler.
142	**********************************************************************/
143	.align 64
144	.global my_trap_code
145	my_trap_code:
146
147	! read DMU error status registers
148
149	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %g3 ! 631000
150	ldx [%g3+0x808], %l7 ! 631808 - DMU Core and Block Error Status Reg
151	cmp %l7, 0
152	bz read_peu_error_regs ! if 0, must be a PEU interrupt
153
154	and %l7, 0x2, %g4 ! test if the MMU has an interrupt
155	cmp %g4, 0
156	bnz read_mmu_error_regs
157	nop
158
159	read_imu_error_regs:
160	ldx [%g3+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
161	ldx [%g3+0x28], %l4 ! 631028 - IMU RDS Error Log Reg
162	ldx [%g3+0x30], %l5 ! 631030 - IMU SCS Error Log Reg
163	ldx [%g3+0x38], %l6 ! 631038 - IMU EQS Error Log Reg
164	b test_failed ! No errors expected - go to bad trap
165	nop
166
167	read_mmu_error_regs:
168	setx FIRE_DLC_MMU_CSR_A_LOG_ADDR, %g1, %g2 ! 641000
169	ldx [%g2+0x10], %l0 ! 641010 - MMU Interrupt Status Reg
170	ldx [%g2+0x28], %l1 ! 641028 - MMU Translation Fault Address Reg
171	ldx [%g2+0x30], %l2 ! 641030 - MMU Translation Fault Status Reg
172	b test_failed ! No errors expected - go to bad trap
173	nop
174
175	! read PEU error status registers
176
177	read_peu_error_regs:
178	setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR, %g1, %g3 ! 651000
179	ldx [%g3+0x808], %l7 ! 651808 - PEU Core and Block Interrupt Status Reg
180	cmp %l7, 0
181	bz test_failed ! one of the bits should have been set
182
183	and %l7, 0x8, %g4 ! test if the ILU has an interrupt
184	cmp %g4, 0
185	bnz read_ilu_error_regs
186
187	and %l7, 0x4, %g4 ! test if its an Uncorrectable error from PEU
188	cmp %g4, 0
189	bnz read_ue_error_regs
190
191	and %l7, 0x2, %g4 ! test if its a Correctable error from PEU
192	cmp %g4, 0
193	bnz read_ce_error_regs
194	nop
195
196	read_oe_error_regs:
197	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR, %g1, %g3 ! 681000
198	ldx [%g3+0x10], %l0 ! 681010 - PEU OE Status Reg
199	and %l0, 0x800, %l1 ! test if its a Correctable error from PEU
200	cmp %l1, 0
201	bnz read_dlpl_error_regs
202	nop
203	ldx [%g2+0x28], %l1 ! 681028 - PEU OE Rx Hdr1 Log Reg
204	ldx [%g2+0x30], %l2 ! 681030 - PEU OE Rx Hdr2 Log Reg
205	ldx [%g2+0x38], %l3 ! 681038 - PEU OE Tx Hdr1 Log Reg
206	ldx [%g2+0x40], %l4 ! 681040 - PEU OE Tx Hdr2 Log Reg
207	b test_failed ! No errors expected - go to bad trap
208	nop
209
210	read_ue_error_regs:
211	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR, %g1, %g3 ! 691000
212	ldx [%g3+0x10], %l0 ! 691010 - PEU UE Status Reg
213	ldx [%g2+0x28], %l1 ! 691028 - PEU UE Rx Hdr1 Log Reg
214	ldx [%g2+0x30], %l2 ! 691030 - PEU UE Rx Hdr2 Log Reg
215	ldx [%g2+0x38], %l3 ! 691038 - PEU UE Tx Hdr1 Log Reg
216	ldx [%g2+0x40], %l4 ! 691040 - PEU UE Tx Hdr2 Log Reg
217	b test_failed ! No errors expected - go to bad trap
218	nop
219
220	read_ce_error_regs:
221	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR, %g1, %g3 ! 6a1000
222	ldx [%g3+0x10], %l0 ! 6a1010 - PEU CE Status Reg
223	b test_failed ! No errors expected - go to bad trap
224	nop
225
226	read_dlpl_error_regs:
227	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g3 ! 6e2100
228	ldx [%g3+0x18], %l1 ! 6e2118 - PEU DLPL Status Reg
229	b test_failed ! No errors expected - go to bad trap
230	nop
231
232	read_ilu_error_regs:
233	ldx [%g3+0x10], %l0 ! 651010 - ILU Interrupt Status Reg
234	b test_failed ! No errors expected - go to bad trap
235	nop
236
237	.align 64
238	trap_end: