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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / si_include / si_defines.h
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: si_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38!
39! This file is used to compile the v9 Test Suite from Sparc International.
40!
41!
42#ifndef NWIN
43#define NWIN 8
44#endif
45
46#ifndef INIT_CWP
47#define INIT_CWP 0
48#define CWP_INIT INIT_CWP
49#endif
50
51#ifndef INIT_CANSAVE
52#define INIT_CANSAVE 6
53#define CANSAVE_INIT INIT_CANSAVE
54#endif
55
56#ifndef INIT_CANRESTORE
57#define INIT_CANRESTORE 0
58#define CANRESTORE_INIT INIT_CANRESTORE
59#endif
60
61#ifndef INIT_OTHERWIN
62#define INIT_OTHERWIN 0
63#define OTHERWIN_INIT INIT_OTHERWIN
64#endif
65
66#ifndef INIT_CLEANWIN
67#define INIT_CLEANWIN 4
68#define CLEANWIN_INIT INIT_CLEANWIN
69#endif
70
71#define EXIT_TRAP_NO 0x6f
72#define USR2SUP_TRAP_NO 0x6e
73
74#ifndef USER_TEXT_START
75#define USER_TEXT_START user_text_start
76#endif
77
78!#define ENTRY_POINT USER_TEXT_START
79#define ENTRY_POINT main
80
81#ifndef RESET_HANDLER
82#define RESET_HANDLER RESET_HANDLER_default
83#endif
84
85#ifndef WATCHDOG_RESET_HANDLER
86#define WATCHDOG_RESET_HANDLER WATCHDOG_RESET_HANDLER_default
87#endif
88
89#ifndef EXTERNAL_RESET_HANDLER
90#define EXTERNAL_RESET_HANDLER EXTERNAL_RESET_HANDLER_default
91#endif
92
93#ifndef SOFTWARE_RESET_HANDLER
94#define SOFTWARE_RESET_HANDLER SOFTWARE_RESET_HANDLER_default
95#endif
96
97#ifndef REDMODE_HANDLER
98#define REDMODE_HANDLER REDMODE_HANDLER_default
99#endif
100
101
102#define ultra 1
103#define not_run 1
104
105#define EXIT_TRAP_NO 0x6f
106#define USR2SUP_TRAP_NO 0x6e
107
108#ifdef SI_DIAG
109#define EXIT\
110exit_ldb:\
111 ta EXIT_TRAP_NO;\
112 nop
113
114#define EXIT1 call exit_ldb
115#else
116#define EXIT \
117 ta GOOD_TRAP
118
119#define EXIT1 \
120 ta BAD_TRAP
121#endif
122
123#define writemem(addr,r_val,r_tmp1) \
124 set addr,r_tmp1;\
125 st r_val,[r_tmp1]
126
127#define readmem(addr,r_tmp,r_dst) \
128 set addr,r_tmp;\
129 ld [r_tmp],r_dst
130
131#define cmpreg(reg1,reg2) \
132 cmp reg1,reg2;\
133 bne,a %xcc,1f;\
134 or %o0,%o1,%o0;\
1351:
136
137#define icmpreg(reg1,reg2) \
138 cmp reg1,reg2;\
139 bne,a %icc,1f;\
140 or %o0,%o1,%o0;\
1411:\
142
143#define chkreg(reg1,reg2) \
144 cmp reg1,reg2;\
145 be %xcc,1f;\
146 nop;\
147 rd %pc,%o0;\
148 EXIT1;\
1491:\
150
151#define fcmpreg(reg1,reg2) \
152 fcmps %fcc0,reg1,reg2;\
153 nop;\
154 fbne,a %fcc0,1f;\
155 or %o0,%o1,%o0;\
1561:\
157
158#define getcc(reg) \
159 rd %ccr,reg
160
161#define putcc(val) \
162 wr %g0,val,%ccr
163
164#define setd(val1,val2,reg1,reg2) \
165 set val1,reg1;\
166 set val2,reg2;
167
168#define settrp(tbladdr,tmpreg1,tmpreg2) \
169 set tbladdr,tmpreg1;\
170 mov 1,tmpreg2;\
171 st tmpreg2,[tmpreg1];
172
173#define dcmp(reg11,reg12,reg21,reg22) \
174 cmp reg11,reg12;\
175 bne,a %xcc,1f;\
176 or %o0,%o1,%o0;\
1771:\
178 cmp reg21,reg22;\
179 bne,a %xcc,1f;\
180 or %o0,%o1,%o0;\
1811:
182
183#define qcmp(reg11,reg12,reg13,reg14,reg21,reg22,reg23,reg24) \
184 cmp reg11,reg12;\
185 bne,a %xcc,1f;\
186 or %o0,%o1,%o0;\
1871:\
188 cmp reg13,reg14;\
189 bne,a %xcc,1f;\
190 or %o0,%o1,%o0;\
1911:\
192 cmp reg21,reg22;\
193 bne,a %xcc,1f;\
194 or %o0,%o1,%o0;\
1951:\
196 cmp reg23,reg24;\
197 bne,a %xcc,1f;\
198 or %o0,%o1,%o0;\
1991:
200
201#define fcmpdreg(reg1,reg2) \
202 fcmpd %fcc0,reg1,reg2;\
203 nop;\
204 fbne,a %fcc0,1f;\
205 or %o0,%o1,%o0;\
2061:\
207
208#define fcmpqreg(reg1,reg2) \
209 fcmpq %fcc0,reg1,reg2;\
210 nop;\
211 fbne,a %fcc0,1f;\
212 or %o0,%o1,%o0;\
2131:\
214
215#define disblfp(reg1) \
216 rd %fprs,reg1;\
217 and reg1,0x3,reg1;\
218 wr %g0,reg1,%fprs
219
220#define enablfp(reg1) \
221 rd %fprs,reg1;\
222 or reg1,0x4,reg1;\
223 wr %g0,reg1,%fprs;\
224 rdpr %pstate,reg1;\
225 or reg1,0x10,reg1;\
226 wrpr %g0,reg1,%pstate
227
228#define getcc(reg) \
229 rd %ccr,reg
230
231#define putcc(val) \
232 wr %g0,val,%ccr\
233
234#define setgreg(val) \
235 mov val,%g1;\
236 mov val,%g2;\
237 mov val,%g3;\
238 mov val,%g4;\
239 mov val,%g5;\
240 mov val,%g6;\
241 mov val,%g7\
242
243#define setireg(val) \
244 mov val,%i0;\
245 mov val,%i1;\
246 mov val,%i2;\
247 mov val,%i3;\
248 mov val,%i4;\
249 mov val,%i5;\
250 mov val,%i6;\
251 mov val,%i7\
252
253#define setlreg(val) \
254 mov val,%l0;\
255 mov val,%l1;\
256 mov val,%l2;\
257 mov val,%l3;\
258 mov val,%l4;\
259 mov val,%l5;\
260 mov val,%l6;\
261 mov val,%l7\
262
263#define setoreg(val) \
264 mov val,%o0;\
265 mov val,%o1;\
266 mov val,%o2;\
267 mov val,%o3;\
268 mov val,%o4;\
269 mov val,%o5;\
270 mov val,%o6;\
271 mov val,%o7\
272
273
274#define setfcc0(val,tmpreg1,tmpreg2)\
275 .seg "data";\
276 .align 8;\
2771: .word 0,0;\
278 .word 0xffffffff,0xfffff3ff;\
279 .seg "text";\
280 set 1b,tmpreg1;\
281 stx %fsr,[tmpreg1];\
282 ldx [tmpreg1],tmpreg2;\
283 ldx [tmpreg1+8],tmpreg1;\
284 and tmpreg2,tmpreg1,tmpreg2;\
285 set val,tmpreg1;\
286 sllx tmpreg1,10,tmpreg1;\
287 or tmpreg2,tmpreg1,tmpreg2;\
288 set 1b,tmpreg1;\
289 stx tmpreg2,[tmpreg1];\
290 ldx [tmpreg1],%fsr
291
292#define setfcc1(val,tmpreg1,tmpreg2)\
293 .seg "data";\
294 .align 8;\
2951: .word 0,0;\
296 .word 0xfffffffc,0xffffffff;\
297 .seg "text";\
298 set 1b,tmpreg1;\
299 stx %fsr,[tmpreg1];\
300 ldx [tmpreg1],tmpreg2;\
301 ldx [tmpreg1+8],tmpreg1;\
302 and tmpreg2,tmpreg1,tmpreg2;\
303 set val,tmpreg1;\
304 sllx tmpreg1,32,tmpreg1;\
305 or tmpreg2,tmpreg1,tmpreg2;\
306 set 1b,tmpreg1;\
307 stx tmpreg2,[tmpreg1];\
308 ldx [tmpreg1],%fsr
309
310#define setfcc2(val,tmpreg1,tmpreg2)\
311 .seg "data";\
312 .align 8;\
3131: .word 0,0;\
314 .word 0xfffffff3,0xffffffff;\
315 .seg "text";\
316 set 1b,tmpreg1;\
317 stx %fsr,[tmpreg1];\
318 ldx [tmpreg1],tmpreg2;\
319 ldx [tmpreg1+8],tmpreg1;\
320 and tmpreg2,tmpreg1,tmpreg2;\
321 set val,tmpreg1;\
322 sllx tmpreg1,34,tmpreg1;\
323 or tmpreg2,tmpreg1,tmpreg2;\
324 set 1b,tmpreg1;\
325 stx tmpreg2,[tmpreg1];\
326 ldx [tmpreg1],%fsr
327
328#define setfcc3(val,tmpreg1,tmpreg2)\
329 .seg "data";\
330 .align 8;\
3311: .word 0,0;\
332 .word 0xffffffcf,0xffffffff;\
333 .seg "text";\
334 set 1b,tmpreg1;\
335 stx %fsr,[tmpreg1];\
336 ldx [tmpreg1],tmpreg2;\
337 ldx [tmpreg1+8],tmpreg1;\
338 and tmpreg2,tmpreg1,tmpreg2;\
339 set val,tmpreg1;\
340 sllx tmpreg1,36,tmpreg1;\
341 or tmpreg2,tmpreg1,tmpreg2;\
342 set 1b,tmpreg1;\
343 stx tmpreg2,[tmpreg1];\
344 ldx [tmpreg1],%fsr
345
346#define getfcc0(reg)\
347 .seg "data";\
348 .align 8;\
3491: .word 0,0;\
350 .seg "text";\
351 set 1b,reg;\
352 stx %fsr,[reg];\
353 ldx [reg],reg;\
354 srlx reg,10,reg;\
355 and reg,0x3,reg
356
357#define getfcc1(reg)\
358 .seg "data";\
359 .align 8;\
3601: .word 0,0;\
361 .seg "text";\
362 set 1b,reg;\
363 stx %fsr,[reg];\
364 ldx [reg],reg;\
365 srlx reg,32,reg;\
366 and reg,0x3,reg
367
368#define getfcc2(reg)\
369 .seg "data";\
370 .align 8;\
3711: .word 0,0;\
372 .seg "text";\
373 set 1b,reg;\
374 stx %fsr,[reg];\
375 ldx [reg],reg;\
376 srlx reg,34,reg;\
377 and reg,0x3,reg
378
379#define getfcc3(reg)\
380 .seg "data";\
381 .align 8;\
3821: .word 0,0;\
383 .seg "text";\
384 set 1b,reg;\
385 stx %fsr,[reg];\
386 ldx [reg],reg;\
387 srlx reg,36,reg;\
388 and reg,0x3,reg
389
390
391#define getfcc2(reg)\
392 .seg "data";\
393 .align 8;\
3941: .word 0,0;\
395 .seg "text";\
396 set 1b,reg;\
397 stx %fsr,[reg];\
398 ldx [reg],reg;\
399 srlx reg,34,reg;\
400 and reg,0x3,reg
401
402#define getfcc3(reg)\
403 .seg "data";\
404 .align 8;\
4051: .word 0,0;\
406 .seg "text";\
407 set 1b,reg;\
408 stx %fsr,[reg];\
409 ldx [reg],reg;\
410 srlx reg,36,reg;\
411 and reg,0x3,reg
412
413
414
415#define NOP4 nop;nop;nop;nop
416
417#define CHECK_VALID(reg,val,err) cmp %reg,val;\
418 bne,a mexit;\
419 mov err,%o0
420
421#ifdef SI_DIAG
422#define WSTATE_NORMAL_MAX 0x7
423#endif
424
Full OpenSPARC design & verification tarball including full HDL.