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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: trap0x33_hred_reset_handler.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define TRAP_2E_START 0x0122000 | |
39 | #define MAIN_BASE_TEXT_VA_CONTEXT 0x20000044 | |
40 | ||
41 | ! HRED_SESET_HANDLER Code here | |
42 | ! | |
43 | !! N2 TBD Need to enable L1-caches | |
44 | !! N2 TBD Need to enable L2-cache | |
45 | ||
46 | ||
47 | #ifndef CUSTOM_THREAD_START | |
48 | ! N2 Thread start stuff here | |
49 | #ifdef SYNC_THREADS | |
50 | ! N2 Thread sync stuff here | |
51 | #endif | |
52 | #endif | |
53 | ||
54 | ! Reset hpstate.red = 0 | |
55 | ! N2 hpstate.enb = 1 | |
56 | ||
57 | rdhpr %hpstate, %l1 | |
58 | wrhpr %l1, 0x820, %hpstate | |
59 | ||
60 | wrpr 0, %tl | |
61 | wrpr 0, %g0, %gl | |
62 | ||
63 | #ifdef NO_SLAM_INIT | |
64 | #include "hboot_init.s" | |
65 | #endif | |
66 | ||
67 | ! load partition id to %l7 | |
68 | wr %g0, ASI_CORE_ID, %asi | |
69 | ldxa [ASI_CORE_ID_VA] %asi, %l7 | |
70 | ||
71 | #ifdef PORTABLE_CORE | |
72 | set 0x07, %g1 | |
73 | #else | |
74 | set 0x3f, %g1 | |
75 | #endif | |
76 | and %l7, %g1, %l7 ! %l7 has TID | |
77 | setx part_id_list, %g1, %g2 | |
78 | sllx %l7, 3, %l7 ! offset - partition list | |
79 | ldx [%g2 + %l7], %g2 ! %g2 contains partition ID | |
80 | ||
81 | mov ASI_PARTITION_ID_VAL, %g1 | |
82 | stxa %g2, [%g1] ASI_PARTITION_ID | |
83 | ||
84 | ! set hyper trap base addr | |
85 | setx HV_TRAP_BASE_PA, %l0, %l7 | |
86 | wrhpr %l7, %g0, %htba | |
87 | ||
88 | hred_tsb_config: | |
89 | ! Load tsb config/base from memory | |
90 | ! and write to corresponding ASI's | |
91 | ! set tsb-config-regs for one partition | |
92 | ||
93 | setx tsb_config_base_list, %l0, %g1 | |
94 | umul %g2, 80, %g2 ! %g2 contains offset to tsb_config_base_list | |
95 | add %g1, %g2, %g1 ! %g1 contains pointer to tsb_config_base_list | |
96 | ||
97 | mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 | |
98 | wr %g3, 0x0, %asi | |
99 | ||
100 | ||
101 | hred_tsb_z_config_0: | |
102 | !!! Write CONTEXT ZERO, TSB_CONFIG_0 !!! | |
103 | ||
104 | ldx [%g1], %g4 ! part_N_z_tsb_config_0 | |
105 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi | |
106 | ||
107 | ||
108 | hred_tsb_nz_config_0: | |
109 | !!! Write CONTEXT NON-ZERO, TSB_CONFIG_0 !!! | |
110 | ||
111 | ldx [%g1+8], %g4 ! part_N_nz_tsb_config_0 | |
112 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi | |
113 | ||
114 | hred_tsb_z_config_1: | |
115 | !!! Write CONTEXT ZERO, TSB_CONFIG_1 !!! | |
116 | ||
117 | ldx [%g1+16], %g4 ! part_N_z_tsb_config_1 | |
118 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi | |
119 | ||
120 | hred_tsb_nz_config_1: | |
121 | !!! Write CONTEXT NON-ZERO, TSB_CONFIG_1 !!! | |
122 | ||
123 | ldx [%g1+24], %g4 ! part_N_nz_tsb_config_1 | |
124 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi | |
125 | ||
126 | hred_tsb_z_config_2: | |
127 | !!! Write CONTEXT ZERO, TSB_CONFIG_2 !!! | |
128 | ||
129 | ldx [%g1+32], %g4 ! part_N_z_tsb_config_2 | |
130 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi | |
131 | ||
132 | hred_tsb_nz_config_2: | |
133 | !!! Write CONTEXT NON-ZERO, TSB_CONFIG_2 !!! | |
134 | ||
135 | ldx [%g1+40], %g4 ! part_N_nz_tsb_config_2 | |
136 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi | |
137 | ||
138 | ||
139 | hred_tsb_z_config_3: | |
140 | !!! Write CONTEXT ZERO, TSB_CONFIG_3 !!! | |
141 | ||
142 | ldx [%g1+48], %g4 ! part_N_z_tsb_config_2 | |
143 | stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi | |
144 | ||
145 | hred_tsb_nz_config_3: | |
146 | !!! Write CONTEXT NON-ZERO, TSB_CONFIG_3 !!! | |
147 | ||
148 | ldx [%g1+56], %g4 ! part_N_nz_tsb_config_3 | |
149 | stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi | |
150 | ||
151 | ! Init dtsb entry for i context zero ps0, ps1 | |
152 | ! Set lsu control reg. enable dcache, icache, immu, dmmu | |
153 | ||
154 | setx cregs_lsu_ctl_reg_r64, %g1, %l7 | |
155 | stxa %l7, [%g0] ASI_LSU_CTL_REG | |
156 | ||
157 | wrpr 1, %tl | |
158 | setx cregs_htstate_r64, %g1, %g4 | |
159 | wrhpr %g4, %g0, %htstate | |
160 | wrpr 0, %tl | |
161 | mov 0x0, %o0 /* please don't delete this , used in customized */ | |
162 | /* IMMU miss trap */ | |
163 | ||
164 | ! Van's code begin -> preloading iTLB | |
165 | ||
166 | ! IMMU_TAG_ACCESS | |
167 | set 0x0134000, %l2 | |
168 | mov 0x30, %l3 | |
169 | stxa %l2, [%l3] 0x50 | |
170 | ||
171 | mov 0x000, %l4 | |
172 | setx 0x8000001000134540, %l1, %l2 ! data, sun4v | |
173 | stxa %l2, [%l4] 0x54 | |
174 | ! Van's code end | |
175 | ||
176 | setx HPriv_Reset_Handler, %g1, %g2 | |
177 | jmp %g2 | |
178 | wrhpr %g0, 0x800, %hpstate | |
179 | nop | |
180 | nop | |
181 |