projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: xlate.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #ifndef __XLATE_H__ | |
| 39 | #define __XLATE_H__ | |
| 40 | ||
| 41 | #if 0 | |
| 42 | #define POWERON_RESET_ENABLE 0x1 | |
| 43 | #define WATCHDOG_RESET_ENABLE 0x1 | |
| 44 | #define EXTERNAL_RESET_ENABLE 0x1 | |
| 45 | #define SOFTWARE_RESET_ENABLE 0x1 | |
| 46 | #define REDMODE_ENABLE 0x1 | |
| 47 | #define RESERVED0_ENABLE 0x1 | |
| 48 | #define RESERVED1_ENABLE 0x1 | |
| 49 | #define INSTRUCTION_ACCESS_EXCEPTION_ENABLE 0x1 | |
| 50 | #define IA_MMU_MISS_ENABLE 0x1 | |
| 51 | #define INSTRUCTION_ACCESS_ERROR_ENABLE 0x1 | |
| 52 | #define RESERVED2_ENABLE 0x1 | |
| 53 | #define RESERVED3_ENABLE 0x1 | |
| 54 | #define RESERVED4_ENABLE 0x1 | |
| 55 | #define RESERVED5_ENABLE 0x1 | |
| 56 | #define RESERVED6_ENABLE 0x1 | |
| 57 | #endif | |
| 58 | ||
| 59 | #define GOOD_TRAP T_GOOD_TRAP | |
| 60 | #define BAD_TRAP T_BAD_TRAP | |
| 61 | #define ST_SUPER T_CHANGE_PRIV | |
| 62 | #define ST_USER T_CHANGE_NONPRIV | |
| 63 | ||
| 64 | #ifdef POWERON_RESET_ENABLE | |
| 65 | #define ENABLE_T0_Reserved_0x01 | |
| 66 | #define ENABLE_HT0_Reserved_0x01 | |
| 67 | #endif | |
| 68 | ||
| 69 | #ifdef WATCHDOG_RESET_ENABLE | |
| 70 | #define ENABLE_T0_Reserved_0x02 | |
| 71 | #define ENABLE_HT0_Reserved_0x02 | |
| 72 | #endif | |
| 73 | ||
| 74 | #ifdef EXTERNAL_RESET_ENABLE | |
| 75 | #define ENABLE_T0_Reserved_0x03 | |
| 76 | #define ENABLE_HT0_Reserved_0x03 | |
| 77 | #endif | |
| 78 | ||
| 79 | #ifdef SOFTWARE_RESET_ENABLE | |
| 80 | #define ENABLE_T0_Reserved_0x04 | |
| 81 | #define ENABLE_HT0_Reserved_0x04 | |
| 82 | #endif | |
| 83 | ||
| 84 | #ifdef REDMODE_ENABLE | |
| 85 | #define ENABLE_T0_Reserved_0x05 | |
| 86 | #define ENABLE_HT0_Reserved_0x05 | |
| 87 | #endif | |
| 88 | ||
| 89 | #ifdef RESERVED0_ENABLE | |
| 90 | #define ENABLE_T0_Reserved_0x06 | |
| 91 | #define ENABLE_HT0_Reserved_0x06 | |
| 92 | #endif | |
| 93 | ||
| 94 | #ifdef RESERVED1_ENABLE | |
| 95 | #define ENABLE_T0_Reserved_0x07 | |
| 96 | #define ENABLE_HT0_Reserved_0x07 | |
| 97 | #endif | |
| 98 | ||
| 99 | #ifdef INSTRUCTION_ACCESS_EXCEPTION_ENABLE | |
| 100 | #define ENABLE_T0_Instruction_access_exception_0x08 | |
| 101 | #define ENABLE_HT0_Instruction_access_exception_0x08 | |
| 102 | #endif | |
| 103 | ||
| 104 | #ifdef IA_MMU_MISS_ENABLE | |
| 105 | #define ENABLE_T0_Instruction_Access_MMU_Miss_0x09 | |
| 106 | #define ENABLE_HT0_Instruction_Access_MMU_Miss_0x09 | |
| 107 | #endif | |
| 108 | ||
| 109 | #ifdef INSTRUCTION_ACCESS_ERROR_ENABLE | |
| 110 | #define ENABLE_T0_Instruction_access_error_0x0a | |
| 111 | #define ENABLE_HT0_Instruction_access_error_0x0a | |
| 112 | #endif | |
| 113 | ||
| 114 | #ifdef RESERVED2_ENABLE | |
| 115 | #define ENABLE_T0_Reserved_0x0b | |
| 116 | #define ENABLE_HT0_Reserved_0x0b | |
| 117 | #endif | |
| 118 | ||
| 119 | #ifdef RESERVED3_ENABLE | |
| 120 | #define ENABLE_T0_Reserved_0x0c | |
| 121 | #define ENABLE_HT0_Reserved_0x0c | |
| 122 | #endif | |
| 123 | ||
| 124 | #ifdef RESERVED4_ENABLE | |
| 125 | #define ENABLE_T0_Reserved_0x0d | |
| 126 | #define ENABLE_HT0_Reserved_0x0d | |
| 127 | #endif | |
| 128 | ||
| 129 | #ifdef RESERVED5_ENABLE | |
| 130 | #define ENABLE_T0_Reserved_0x0e | |
| 131 | #define ENABLE_HT0_Reserved_0x0e | |
| 132 | #endif | |
| 133 | ||
| 134 | #ifdef RESERVED6_ENABLE | |
| 135 | #define ENABLE_T0_Reserved_0x0f | |
| 136 | #define ENABLE_HT0_Reserved_0x0f | |
| 137 | #endif | |
| 138 | ||
| 139 | #ifdef ILLEGAL_ENABLE | |
| 140 | #define ENABLE_T0_Illegal_instruction_0x10 | |
| 141 | #define ENABLE_HT0_Illegal_instruction_0x10 | |
| 142 | #endif | |
| 143 | ||
| 144 | #ifdef PRIVILEGED_OPCODE_ENABLE | |
| 145 | #define ENABLE_T0_Privileged_opcode_0x11 | |
| 146 | #define ENABLE_HT0_Privileged_opcode_0x11 | |
| 147 | #endif | |
| 148 | ||
| 149 | #ifdef UNIMPLEMENTED_LDD_ENABLE | |
| 150 | #define ENABLE_T0_Unimplemented_LDD_0x12 | |
| 151 | #define ENABLE_HT0_Unimplemented_LDD_0x12 | |
| 152 | #endif | |
| 153 | ||
| 154 | #ifdef UNIMPLEMENTED_STD_ENABLE | |
| 155 | #define ENABLE_T0_Unimplemented_STD_0x13 | |
| 156 | #define ENABLE_HT0_Unimplemented_STD_0x13 | |
| 157 | #endif | |
| 158 | ||
| 159 | #ifdef RESERVED7_ENABLE | |
| 160 | #define ENABLE_T0_Reserved_0x14 | |
| 161 | #define ENABLE_HT0_Reserved_0x14 | |
| 162 | #endif | |
| 163 | ||
| 164 | #ifdef RESERVED8_ENABLE | |
| 165 | #define ENABLE_T0_Reserved_0x15 | |
| 166 | #define ENABLE_HT0_Reserved_0x15 | |
| 167 | #endif | |
| 168 | ||
| 169 | #ifdef RESERVED9_ENABLE | |
| 170 | #define ENABLE_T0_Reserved_0x16 | |
| 171 | #define ENABLE_HT0_Reserved_0x16 | |
| 172 | #endif | |
| 173 | ||
| 174 | #ifdef RESERVED10_ENABLE | |
| 175 | #define ENABLE_T0_Reserved_0x17 | |
| 176 | #define ENABLE_HT0_Reserved_0x17 | |
| 177 | #endif | |
| 178 | ||
| 179 | #ifdef RESERVED11_ENABLE | |
| 180 | #define ENABLE_T0_Reserved_0x18 | |
| 181 | #define ENABLE_HT0_Reserved_0x18 | |
| 182 | #endif | |
| 183 | ||
| 184 | #ifdef RESERVED12_ENABLE | |
| 185 | #define ENABLE_T0_Reserved_0x19 | |
| 186 | #define ENABLE_HT0_Reserved_0x19 | |
| 187 | #endif | |
| 188 | ||
| 189 | #ifdef RESERVED13_ENABLE | |
| 190 | #define ENABLE_T0_Reserved_0x1a | |
| 191 | #define ENABLE_HT0_Reserved_0x1a | |
| 192 | #endif | |
| 193 | ||
| 194 | #ifdef RESERVED14_ENABLE | |
| 195 | #define ENABLE_T0_Reserved_0x1b | |
| 196 | #define ENABLE_HT0_Reserved_0x1b | |
| 197 | #endif | |
| 198 | ||
| 199 | #ifdef RESERVED15_ENABLE | |
| 200 | #define ENABLE_T0_Reserved_0x1c | |
| 201 | #define ENABLE_HT0_Reserved_0x1c | |
| 202 | #endif | |
| 203 | ||
| 204 | #ifdef RESERVED16_ENABLE | |
| 205 | #define ENABLE_T0_Reserved_0x1d | |
| 206 | #define ENABLE_HT0_Reserved_0x1d | |
| 207 | #endif | |
| 208 | ||
| 209 | #ifdef RESERVED17_ENABLE | |
| 210 | #define ENABLE_T0_Reserved_0x1e | |
| 211 | #define ENABLE_HT0_Reserved_0x1e | |
| 212 | #endif | |
| 213 | ||
| 214 | #ifdef RESERVED18_ENABLE | |
| 215 | #define ENABLE_T0_Reserved_0x1f | |
| 216 | #define ENABLE_HT0_Reserved_0x1f | |
| 217 | #endif | |
| 218 | ||
| 219 | #ifdef FP_DISABLED_ENABLE | |
| 220 | #define ENABLE_T0_Fp_disabled_0x20 | |
| 221 | #define ENABLE_HT0_Fp_disabled_0x20 | |
| 222 | #endif | |
| 223 | ||
| 224 | #ifdef FP_IEEE_754_ENABLE | |
| 225 | #define ENABLE_T0_Fp_exception_ieee_754_0x21 | |
| 226 | #define ENABLE_HT0_Fp_exception_ieee_754_0x21 | |
| 227 | #endif | |
| 228 | ||
| 229 | #ifdef FP_EXCP_OTHER_ENABLE | |
| 230 | #define ENABLE_T0_Fp_exception_other_0x22 | |
| 231 | #define ENABLE_HT0_Fp_exception_other_0x22 | |
| 232 | #endif | |
| 233 | ||
| 234 | #ifdef TAG_OVERFLOW_ENABLE | |
| 235 | #define ENABLE_T0_Tag_Overflow_0x23 | |
| 236 | #define ENABLE_HT0_Tag_Overflow_0x23 | |
| 237 | #endif | |
| 238 | ||
| 239 | #ifdef CLEAN_WIN_ENABLE | |
| 240 | #define ENABLE_T0_Clean_Window_0x24 | |
| 241 | #define ENABLE_HT0_Clean_Window_0x24 | |
| 242 | #endif | |
| 243 | ||
| 244 | #ifdef DIV_ZERO_ENABLE | |
| 245 | #define ENABLE_T0_Division_By_Zero_0x28 | |
| 246 | #define ENABLE_HT0_Division_By_Zero_0x28 | |
| 247 | #endif | |
| 248 | ||
| 249 | #ifdef INT_PROC_ERROR_ENABLE | |
| 250 | #define ENABLE_T0_Reserved_0x29 | |
| 251 | #define ENABLE_HT0_Reserved_0x29 | |
| 252 | #endif | |
| 253 | ||
| 254 | #ifdef RESERVED19_ENABLE | |
| 255 | #define ENABLE_T0_Reserved_0x2a | |
| 256 | #define ENABLE_HT0_Reserved_0x2a | |
| 257 | #endif | |
| 258 | ||
| 259 | #ifdef RESERVED20_ENABLE | |
| 260 | #define ENABLE_T0_Reserved_0x2b | |
| 261 | #define ENABLE_HT0_Reserved_0x2b | |
| 262 | #endif | |
| 263 | ||
| 264 | #ifdef RESERVED21_ENABLE | |
| 265 | #define ENABLE_T0_Reserved_0x2c | |
| 266 | #define ENABLE_HT0_Reserved_0x2c | |
| 267 | #endif | |
| 268 | ||
| 269 | #ifdef RESERVED22_ENABLE | |
| 270 | #define ENABLE_T0_Reserved_0x2d | |
| 271 | #define ENABLE_HT0_Reserved_0x2d | |
| 272 | #endif | |
| 273 | ||
| 274 | #ifdef RESERVED23_ENABLE | |
| 275 | #define ENABLE_T0_Reserved_0x2e | |
| 276 | #define ENABLE_HT0_Reserved_0x2e | |
| 277 | #endif | |
| 278 | ||
| 279 | #ifdef RESERVED24_ENABLE | |
| 280 | #define ENABLE_T0_Reserved_0x2f | |
| 281 | #define ENABLE_HT0_Reserved_0x2f | |
| 282 | #endif | |
| 283 | ||
| 284 | #ifdef DATA_ACCESS_EXCEPTION_ENABLE | |
| 285 | #define ENABLE_T0_Data_Access_Exception_0x30 | |
| 286 | #define ENABLE_HT0_Data_Access_Exception_0x30 | |
| 287 | #endif | |
| 288 | ||
| 289 | #ifdef DA_MMU_MISS_ENABLE | |
| 290 | #define ENABLE_T0_Reserved_0x31 | |
| 291 | #define ENABLE_HT0_Reserved_0x31 | |
| 292 | #endif | |
| 293 | ||
| 294 | #ifdef DATA_ACCESS_ERROR_ENABLE | |
| 295 | #define ENABLE_T0_Data_access_error_0x32 | |
| 296 | #define ENABLE_HT0_Data_access_error_0x32 | |
| 297 | #endif | |
| 298 | ||
| 299 | #ifdef DATA_PROT_ENABLE | |
| 300 | #define ENABLE_T0_Reserved_0x33 | |
| 301 | #define ENABLE_HT0_Reserved_0x33 | |
| 302 | #endif | |
| 303 | ||
| 304 | #ifdef MEM_NONALIGNED_ENABLE | |
| 305 | #define ENABLE_T0_Mem_Address_Not_Aligned_0x34 | |
| 306 | #define ENABLE_HT0_Mem_Address_Not_Aligned_0x34 | |
| 307 | #endif | |
| 308 | ||
| 309 | #ifdef LDDF_MEM_NONALIGNED_ENABLE | |
| 310 | #define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35 | |
| 311 | #define ENABLE_HT0_Lddf_Mem_Address_Not_Aligned_0x35 | |
| 312 | #endif | |
| 313 | ||
| 314 | #ifdef STDF_MEM_NONALIGNED_ENABLE | |
| 315 | #define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36 | |
| 316 | #define ENABLE_HT0_Stdf_Mem_Address_Not_Aligned_0x36 | |
| 317 | #endif | |
| 318 | ||
| 319 | #ifdef PRIVILEGED_ACTION_ENABLE | |
| 320 | #define ENABLE_T0_Privileged_Action_0x37 | |
| 321 | #define ENABLE_HT0_Privileged_Action_0x37 | |
| 322 | #endif | |
| 323 | ||
| 324 | #ifdef LDQF_MEM_NONALIGNED_ENABLE | |
| 325 | #define ENABLE_T0_Reserved_0x38 | |
| 326 | #define ENABLE_HT0_Reserved_0x38 | |
| 327 | #endif | |
| 328 | ||
| 329 | #ifdef STQF_MEM_NONALIGNED_ENABLE | |
| 330 | #define ENABLE_T0_Reserved_0x39 | |
| 331 | #define ENABLE_HT0_Reserved_0x39 | |
| 332 | #endif | |
| 333 | ||
| 334 | #ifdef RESERVED25_ENABLE | |
| 335 | #define ENABLE_T0_Reserved_0x3a | |
| 336 | #define ENABLE_HT0_Reserved_0x3a | |
| 337 | #endif | |
| 338 | ||
| 339 | #ifdef RESERVED26_ENABLE | |
| 340 | #define ENABLE_T0_Reserved_0x3b | |
| 341 | #define ENABLE_HT0_Reserved_0x3b | |
| 342 | #endif | |
| 343 | ||
| 344 | #ifdef RESERVED27_ENABLE | |
| 345 | #define ENABLE_T0_Reserved_0x3c | |
| 346 | #define ENABLE_HT0_Reserved_0x3c | |
| 347 | #endif | |
| 348 | ||
| 349 | #ifdef RESERVED28_ENABLE | |
| 350 | #define ENABLE_T0_Reserved_0x3d | |
| 351 | #define ENABLE_HT0_Reserved_0x3d | |
| 352 | #endif | |
| 353 | ||
| 354 | #ifdef RESERVED29_ENABLE | |
| 355 | #define ENABLE_T0_Reserved_0x3e | |
| 356 | #define ENABLE_HT0_Reserved_0x3e | |
| 357 | #endif | |
| 358 | ||
| 359 | #ifdef RESERVED30_ENABLE | |
| 360 | #define ENABLE_T0_Reserved_0x3f | |
| 361 | #define ENABLE_HT0_Reserved_0x3f | |
| 362 | #endif | |
| 363 | ||
| 364 | #ifdef ASYNC_DATA_ERROR_ENABLE | |
| 365 | #define ENABLE_T0_Reserved_0x40 | |
| 366 | #define ENABLE_HT0_Reserved_0x40 | |
| 367 | #endif | |
| 368 | ||
| 369 | #ifdef INTERRUPT_LEVEL_1_ENABLE | |
| 370 | #define ENABLE_T0_Interrupt_Level_1_0x41 | |
| 371 | #define ENABLE_HT0_Interrupt_Level_1_0x41 | |
| 372 | #endif | |
| 373 | ||
| 374 | #ifdef INTERRUPT_LEVEL_2_ENABLE | |
| 375 | #define ENABLE_T0_Interrupt_Level_2_0x42 | |
| 376 | #define ENABLE_HT0_Interrupt_Level_2_0x42 | |
| 377 | #endif | |
| 378 | ||
| 379 | #ifdef INTERRUPT_LEVEL_3_ENABLE | |
| 380 | #define ENABLE_T0_Interrupt_Level_3_0x43 | |
| 381 | #define ENABLE_HT0_Interrupt_Level_3_0x43 | |
| 382 | #endif | |
| 383 | ||
| 384 | #ifdef INTERRUPT_LEVEL_4_ENABLE | |
| 385 | #define ENABLE_T0_Interrupt_Level_4_0x44 | |
| 386 | #define ENABLE_HT0_Interrupt_Level_4_0x44 | |
| 387 | #endif | |
| 388 | ||
| 389 | #ifdef INTERRUPT_LEVEL_5_ENABLE | |
| 390 | #define ENABLE_T0_Interrupt_Level_5_0x45 | |
| 391 | #define ENABLE_HT0_Interrupt_Level_5_0x45 | |
| 392 | #endif | |
| 393 | ||
| 394 | #ifdef INTERRUPT_LEVEL_6_ENABLE | |
| 395 | #define ENABLE_T0_Interrupt_Level_6_0x46 | |
| 396 | #define ENABLE_HT0_Interrupt_Level_6_0x46 | |
| 397 | #endif | |
| 398 | ||
| 399 | #ifdef INTERRUPT_LEVEL_7_ENABLE | |
| 400 | #define ENABLE_T0_Interrupt_Level_7_0x47 | |
| 401 | #define ENABLE_HT0_Interrupt_Level_7_0x47 | |
| 402 | #endif | |
| 403 | ||
| 404 | #ifdef INTERRUPT_LEVEL_8_ENABLE | |
| 405 | #define ENABLE_T0_Interrupt_Level_8_0x48 | |
| 406 | #define ENABLE_HT0_Interrupt_Level_8_0x48 | |
| 407 | #endif | |
| 408 | ||
| 409 | #ifdef INTERRUPT_LEVEL_9_ENABLE | |
| 410 | #define ENABLE_T0_Interrupt_Level_9_0x49 | |
| 411 | #define ENABLE_HT0_Interrupt_Level_9_0x49 | |
| 412 | #endif | |
| 413 | ||
| 414 | #ifdef INTERRUPT_LEVEL_10_ENABLE | |
| 415 | #define ENABLE_T0_Interrupt_Level_10_0x4a | |
| 416 | #define ENABLE_HT0_Interrupt_Level_10_0x4a | |
| 417 | #endif | |
| 418 | ||
| 419 | #ifdef INTERRUPT_LEVEL_11_ENABLE | |
| 420 | #define ENABLE_T0_Interrupt_Level_11_0x4b | |
| 421 | #define ENABLE_HT0_Interrupt_Level_11_0x4b | |
| 422 | #endif | |
| 423 | ||
| 424 | #ifdef INTERRUPT_LEVEL_12_ENABLE | |
| 425 | #define ENABLE_T0_Interrupt_Level_12_0x4c | |
| 426 | #define ENABLE_HT0_Interrupt_Level_12_0x4c | |
| 427 | #endif | |
| 428 | ||
| 429 | #ifdef INTERRUPT_LEVEL_13_ENABLE | |
| 430 | #define ENABLE_T0_Interrupt_Level_13_0x4d | |
| 431 | #define ENABLE_HT0_Interrupt_Level_13_0x4d | |
| 432 | #endif | |
| 433 | ||
| 434 | #ifdef INTERRUPT_LEVEL_14_ENABLE | |
| 435 | #define ENABLE_T0_Interrupt_Level_14_0x4e | |
| 436 | #define ENABLE_HT0_Interrupt_Level_14_0x4e | |
| 437 | #endif | |
| 438 | ||
| 439 | #ifdef INTERRUPT_LEVEL_15_ENABLE | |
| 440 | #define ENABLE_T0_Interrupt_Level_15_0x4f | |
| 441 | #define ENABLE_HT0_Interrupt_Level_15_0x4f | |
| 442 | #endif | |
| 443 | ||
| 444 | #ifdef RESERVED31_ENABLE | |
| 445 | #define ENABLE_T0_Reserved_0x50 | |
| 446 | #define ENABLE_HT0_Reserved_0x50 | |
| 447 | #endif | |
| 448 | ||
| 449 | #ifdef RESERVED32_ENABLE | |
| 450 | #define ENABLE_T0_Reserved_0x51 | |
| 451 | #define ENABLE_HT0_Reserved_0x51 | |
| 452 | #endif | |
| 453 | ||
| 454 | #ifdef RESERVED33_ENABLE | |
| 455 | #define ENABLE_T0_Reserved_0x52 | |
| 456 | #define ENABLE_HT0_Reserved_0x52 | |
| 457 | #endif | |
| 458 | ||
| 459 | #ifdef RESERVED34_ENABLE | |
| 460 | #define ENABLE_T0_Reserved_0x53 | |
| 461 | #define ENABLE_HT0_Reserved_0x53 | |
| 462 | #endif | |
| 463 | ||
| 464 | #ifdef RESERVED35_ENABLE | |
| 465 | #define ENABLE_T0_Reserved_0x54 | |
| 466 | #define ENABLE_HT0_Reserved_0x54 | |
| 467 | #endif | |
| 468 | ||
| 469 | #ifdef RESERVED36_ENABLE | |
| 470 | #define ENABLE_T0_Reserved_0x55 | |
| 471 | #define ENABLE_HT0_Reserved_0x55 | |
| 472 | #endif | |
| 473 | ||
| 474 | #ifdef RESERVED37_ENABLE | |
| 475 | #define ENABLE_T0_Reserved_0x56 | |
| 476 | #define ENABLE_HT0_Reserved_0x56 | |
| 477 | #endif | |
| 478 | ||
| 479 | #ifdef RESERVED38_ENABLE | |
| 480 | #define ENABLE_T0_Reserved_0x57 | |
| 481 | #define ENABLE_HT0_Reserved_0x57 | |
| 482 | #endif | |
| 483 | ||
| 484 | #ifdef RESERVED39_ENABLE | |
| 485 | #define ENABLE_T0_Reserved_0x58 | |
| 486 | #define ENABLE_HT0_Reserved_0x58 | |
| 487 | #endif | |
| 488 | ||
| 489 | #ifdef RESERVED40_ENABLE | |
| 490 | #define ENABLE_T0_Reserved_0x59 | |
| 491 | #define ENABLE_HT0_Reserved_0x59 | |
| 492 | #endif | |
| 493 | ||
| 494 | #ifdef RESERVED41_ENABLE | |
| 495 | #define ENABLE_T0_Reserved_0x5a | |
| 496 | #define ENABLE_HT0_Reserved_0x5a | |
| 497 | #endif | |
| 498 | ||
| 499 | #ifdef RESERVED42_ENABLE | |
| 500 | #define ENABLE_T0_Reserved_0x5b | |
| 501 | #define ENABLE_HT0_Reserved_0x5b | |
| 502 | #endif | |
| 503 | ||
| 504 | #ifdef RESERVED43_ENABLE | |
| 505 | #define ENABLE_T0_Reserved_0x5c | |
| 506 | #define ENABLE_HT0_Reserved_0x5c | |
| 507 | #endif | |
| 508 | ||
| 509 | #ifdef RESERVED44_ENABLE | |
| 510 | #define ENABLE_T0_Reserved_0x5d | |
| 511 | #define ENABLE_HT0_Reserved_0x5d | |
| 512 | #endif | |
| 513 | ||
| 514 | #ifdef RESERVED45_ENABLE | |
| 515 | #define ENABLE_T0_Reserved_0x5e | |
| 516 | #define ENABLE_HT0_Reserved_0x5e | |
| 517 | #endif | |
| 518 | ||
| 519 | #ifdef RESERVED46_ENABLE | |
| 520 | #define ENABLE_T0_Reserved_0x5f | |
| 521 | #define ENABLE_HT0_Reserved_0x5f | |
| 522 | #endif | |
| 523 | ||
| 524 | #ifdef IMPL_DEP_XCPN_0_ENABLE | |
| 525 | #define ENABLE_T0_Interrupt_0x60 | |
| 526 | #define ENABLE_HT0_Interrupt_0x60 | |
| 527 | #endif | |
| 528 | ||
| 529 | #ifdef PA_WATCHPOINT_ENABLE | |
| 530 | #define ENABLE_T0_Reserved_0x61 | |
| 531 | #define ENABLE_HT0_Reserved_0x61 | |
| 532 | #endif | |
| 533 | ||
| 534 | #ifdef VA_WATCHPOINT_ENABLE | |
| 535 | #define ENABLE_T0_Reserved_0x62 | |
| 536 | #define ENABLE_HT0_Reserved_0x62 | |
| 537 | #endif | |
| 538 | ||
| 539 | #ifdef IA_FAST_MMU_MISS_ENABLE | |
| 540 | #define ENABLE_T0_fast_instr_access_MMU_miss_0x64 | |
| 541 | #define ENABLE_HT0_fast_instr_access_MMU_miss_0x64 | |
| 542 | #endif | |
| 543 | ||
| 544 | #ifdef DA_FAST_MMU_MISS_ENABLE | |
| 545 | #define ENABLE_T0_fast_data_access_MMU_miss_0x68 | |
| 546 | #define ENABLE_HT0_fast_data_access_MMU_miss_0x68 | |
| 547 | #endif | |
| 548 | ||
| 549 | #ifdef FAST_DATA_PROT_ENABLE | |
| 550 | #define ENABLE_T0_data_access_protection_0x6c | |
| 551 | #define ENABLE_HT0_data_access_protection_0x6c | |
| 552 | #endif | |
| 553 | ||
| 554 | #ifdef SPILL_0_NORMAL_ENABLE | |
| 555 | #define ENABLE_T0_Window_Spill_0_Normal_0x80 | |
| 556 | #define ENABLE_HT0_Window_Spill_0_Normal_0x80 | |
| 557 | #endif | |
| 558 | ||
| 559 | #ifdef SPILL_1_NORMAL_ENABLE | |
| 560 | #define ENABLE_T0_Window_Spill_1_Normal_0x84 | |
| 561 | #define ENABLE_HT0_Window_Spill_1_Normal_0x84 | |
| 562 | #endif | |
| 563 | ||
| 564 | #ifdef SPILL_2_NORMAL_ENABLE | |
| 565 | #define ENABLE_T0_Window_Spill_2_Normal_0x88 | |
| 566 | #define ENABLE_HT0_Window_Spill_2_Normal_0x88 | |
| 567 | #endif | |
| 568 | ||
| 569 | #ifdef SPILL_3_NORMAL_ENABLE | |
| 570 | #define ENABLE_T0_Window_Spill_3_Normal_0x8c | |
| 571 | #define ENABLE_HT0_Window_Spill_3_Normal_0x8c | |
| 572 | #endif | |
| 573 | ||
| 574 | #ifdef SPILL_4_NORMAL_ENABLE | |
| 575 | #define ENABLE_T0_Window_Spill_4_Normal_0x90 | |
| 576 | #define ENABLE_HT0_Window_Spill_4_Normal_0x90 | |
| 577 | #endif | |
| 578 | ||
| 579 | #ifdef SPILL_5_NORMAL_ENABLE | |
| 580 | #define ENABLE_T0_Window_Spill_5_Normal_0x94 | |
| 581 | #define ENABLE_HT0_Window_Spill_5_Normal_0x94 | |
| 582 | #endif | |
| 583 | ||
| 584 | #ifdef SPILL_6_NORMAL_ENABLE | |
| 585 | #define ENABLE_T0_Window_Spill_6_Normal_0x98 | |
| 586 | #define ENABLE_HT0_Window_Spill_6_Normal_0x98 | |
| 587 | #endif | |
| 588 | ||
| 589 | #ifdef SPILL_7_NORMAL_ENABLE | |
| 590 | #define ENABLE_T0_Window_Spill_7_Normal_0x9c | |
| 591 | #define ENABLE_HT0_Window_Spill_7_Normal_0x9c | |
| 592 | #endif | |
| 593 | ||
| 594 | #ifdef SPILL_0_OTHER_ENABLE | |
| 595 | #define ENABLE_T0_Window_Spill_0_Other_0xa0 | |
| 596 | #define ENABLE_HT0_Window_Spill_0_Other_0xa0 | |
| 597 | #endif | |
| 598 | ||
| 599 | #ifdef SPILL_1_OTHER_ENABLE | |
| 600 | #define ENABLE_T0_Window_Spill_1_Other_0xa4 | |
| 601 | #define ENABLE_HT0_Window_Spill_1_Other_0xa4 | |
| 602 | #endif | |
| 603 | ||
| 604 | #ifdef SPILL_2_OTHER_ENABLE | |
| 605 | #define ENABLE_T0_Window_Spill_2_Other_0xa8 | |
| 606 | #define ENABLE_HT0_Window_Spill_2_Other_0xa8 | |
| 607 | #endif | |
| 608 | ||
| 609 | #ifdef SPILL_3_OTHER_ENABLE | |
| 610 | #define ENABLE_T0_Window_Spill_3_Other_0xac | |
| 611 | #define ENABLE_HT0_Window_Spill_3_Other_0xac | |
| 612 | #endif | |
| 613 | ||
| 614 | #ifdef SPILL_4_OTHER_ENABLE | |
| 615 | #define ENABLE_T0_Window_Spill_4_Other_0xb0 | |
| 616 | #define ENABLE_HT0_Window_Spill_4_Other_0xb0 | |
| 617 | #endif | |
| 618 | ||
| 619 | #ifdef SPILL_5_OTHER_ENABLE | |
| 620 | #define ENABLE_T0_Window_Spill_5_Other_0xb4 | |
| 621 | #define ENABLE_HT0_Window_Spill_5_Other_0xb4 | |
| 622 | #endif | |
| 623 | ||
| 624 | #ifdef SPILL_6_OTHER_ENABLE | |
| 625 | #define ENABLE_T0_Window_Spill_6_Other_0xb8 | |
| 626 | #define ENABLE_HT0_Window_Spill_6_Other_0xb8 | |
| 627 | #endif | |
| 628 | ||
| 629 | #ifdef SPILL_7_OTHER_ENABLE | |
| 630 | #define ENABLE_T0_Window_Spill_7_Other_0xbc | |
| 631 | #define ENABLE_HT0_Window_Spill_7_Other_0xbc | |
| 632 | #endif | |
| 633 | ||
| 634 | #ifdef FILL_0_NORMAL_ENABLE | |
| 635 | #define ENABLE_T0_Window_Fill_0_Normal_0xc0 | |
| 636 | #define ENABLE_HT0_Window_Fill_0_Normal_0xc0 | |
| 637 | #endif | |
| 638 | ||
| 639 | #ifdef FILL_1_NORMAL_ENABLE | |
| 640 | #define ENABLE_T0_Window_Fill_1_Normal_0xc4 | |
| 641 | #define ENABLE_HT0_Window_Fill_1_Normal_0xc4 | |
| 642 | #endif | |
| 643 | ||
| 644 | #ifdef FILL_2_NORMAL_ENABLE | |
| 645 | #define ENABLE_T0_Window_Fill_2_Normal_0xc8 | |
| 646 | #define ENABLE_HT0_Window_Fill_2_Normal_0xc8 | |
| 647 | #endif | |
| 648 | ||
| 649 | #ifdef FILL_3_NORMAL_ENABLE | |
| 650 | #define ENABLE_T0_Window_Fill_3_Normal_0xcc | |
| 651 | #define ENABLE_HT0_Window_Fill_3_Normal_0xcc | |
| 652 | #endif | |
| 653 | ||
| 654 | #ifdef FILL_4_NORMAL_ENABLE | |
| 655 | #define ENABLE_T0_Window_Fill_4_Normal_0xd0 | |
| 656 | #define ENABLE_HT0_Window_Fill_4_Normal_0xd0 | |
| 657 | #endif | |
| 658 | ||
| 659 | #ifdef FILL_5_NORMAL_ENABLE | |
| 660 | #define ENABLE_T0_Window_Fill_5_Normal_0xd4 | |
| 661 | #define ENABLE_HT0_Window_Fill_5_Normal_0xd4 | |
| 662 | #endif | |
| 663 | ||
| 664 | #ifdef FILL_6_NORMAL_ENABLE | |
| 665 | #define ENABLE_T0_Window_Fill_6_Normal_0xd8 | |
| 666 | #define ENABLE_HT0_Window_Fill_6_Normal_0xd8 | |
| 667 | #endif | |
| 668 | ||
| 669 | #ifdef FILL_7_NORMAL_ENABLE | |
| 670 | #define ENABLE_T0_Window_Fill_7_Normal_0xdc | |
| 671 | #define ENABLE_HT0_Window_Fill_7_Normal_0xdc | |
| 672 | #endif | |
| 673 | ||
| 674 | #ifdef FILL_0_OTHER_ENABLE | |
| 675 | #define ENABLE_T0_Window_Fill_0_Other_0xe0 | |
| 676 | #define ENABLE_HT0_Window_Fill_0_Other_0xe0 | |
| 677 | #endif | |
| 678 | ||
| 679 | #ifdef FILL_1_OTHER_ENABLE | |
| 680 | #define ENABLE_T0_Window_Fill_1_Other_0xe4 | |
| 681 | #define ENABLE_HT0_Window_Fill_1_Other_0xe4 | |
| 682 | #endif | |
| 683 | ||
| 684 | #ifdef FILL_2_OTHER_ENABLE | |
| 685 | #define ENABLE_T0_Window_Fill_2_Other_0xe8 | |
| 686 | #define ENABLE_HT0_Window_Fill_2_Other_0xe8 | |
| 687 | #endif | |
| 688 | ||
| 689 | #ifdef FILL_3_OTHER_ENABLE | |
| 690 | #define ENABLE_T0_Window_Fill_3_Other_0xec | |
| 691 | #define ENABLE_HT0_Window_Fill_3_Other_0xec | |
| 692 | #endif | |
| 693 | ||
| 694 | #ifdef FILL_4_OTHER_ENABLE | |
| 695 | #define ENABLE_T0_Window_Fill_4_Other_0xf0 | |
| 696 | #define ENABLE_HT0_Window_Fill_4_Other_0xf0 | |
| 697 | #endif | |
| 698 | ||
| 699 | #ifdef FILL_5_OTHER_ENABLE | |
| 700 | #define ENABLE_T0_Window_Fill_5_Other_0xf4 | |
| 701 | #define ENABLE_HT0_Window_Fill_5_Other_0xf4 | |
| 702 | #endif | |
| 703 | ||
| 704 | #ifdef FILL_6_OTHER_ENABLE | |
| 705 | #define ENABLE_T0_Window_Fill_6_Other_0xf8 | |
| 706 | #define ENABLE_HT0_Window_Fill_6_Other_0xf8 | |
| 707 | #endif | |
| 708 | ||
| 709 | #ifdef FILL_7_OTHER_ENABLE | |
| 710 | #define ENABLE_T0_Window_Fill_7_Other_0xfc | |
| 711 | #define ENABLE_HT0_Window_Fill_7_Other_0xfc | |
| 712 | #endif | |
| 713 | ||
| 714 | #if 0 | |
| 715 | #define PRIVILEGED_OPCODE_ENABLE 0x1 | |
| 716 | #define UNIMPLEMENTED_LDD_ENABLE 0x1 | |
| 717 | #define UNIMPLEMENTED_STD_ENABLE 0x1 | |
| 718 | #define RESERVED7_ENABLE 0x1 | |
| 719 | #define RESERVED8_ENABLE 0x1 | |
| 720 | #define RESERVED9_ENABLE 0x1 | |
| 721 | #define RESERVED10_ENABLE 0x1 | |
| 722 | #define RESERVED11_ENABLE 0x1 | |
| 723 | #define RESERVED12_ENABLE 0x1 | |
| 724 | #define RESERVED13_ENABLE 0x1 | |
| 725 | #define RESERVED14_ENABLE 0x1 | |
| 726 | #define RESERVED15_ENABLE 0x1 | |
| 727 | #define RESERVED16_ENABLE 0x1 | |
| 728 | #define RESERVED17_ENABLE 0x1 | |
| 729 | #define RESERVED18_ENABLE 0x1 | |
| 730 | #define FP_DISABLED_ENABLE 0x1 | |
| 731 | #define FP_IEEE_754_ENABLE 0x1 | |
| 732 | #define FP_EXCP_OTHER_ENABLE 0x1 | |
| 733 | #define TAG_OVERFLOW_ENABLE 0x1 | |
| 734 | #endif | |
| 735 | ||
| 736 | #if 0 | |
| 737 | #define CLEAN_WIN_ENABLE 0x1 | |
| 738 | #define DIV_ZERO_ENABLE 0x1 | |
| 739 | #define INT_PROC_ERROR_ENABLE 0x1 | |
| 740 | #define RESERVED19_ENABLE 0x1 | |
| 741 | #define RESERVED20_ENABLE 0x1 | |
| 742 | #define RESERVED21_ENABLE 0x1 | |
| 743 | #define RESERVED22_ENABLE 0x1 | |
| 744 | #define RESERVED23_ENABLE 0x1 | |
| 745 | #define RESERVED24_ENABLE 0x1 | |
| 746 | #define DATA_ACCESS_EXCEPTION_ENABLE 0x1 | |
| 747 | #define DA_MMU_MISS_ENABLE 0x1 | |
| 748 | #define DATA_ACCESS_ERROR_ENABLE 0x1 | |
| 749 | #define DATA_PROT_ENABLE 0x1 | |
| 750 | #define MEM_NONALIGNED_ENABLE 0x1 | |
| 751 | #define LDDF_MEM_NONALIGNED_ENABLE 0x1 | |
| 752 | #define STDF_MEM_NONALIGNED_ENABLE 0x1 | |
| 753 | #define PRIVILEGED_ACTION_ENABLE 0x1 | |
| 754 | #define LDQF_MEM_NONALIGNED_ENABLE 0x1 | |
| 755 | #define STQF_MEM_NONALIGNED_ENABLE 0x1 | |
| 756 | #define RESERVED25_ENABLE 0x1 | |
| 757 | #define RESERVED26_ENABLE 0x1 | |
| 758 | #define RESERVED27_ENABLE 0x1 | |
| 759 | #define RESERVED28_ENABLE 0x1 | |
| 760 | #define RESERVED29_ENABLE 0x1 | |
| 761 | #define RESERVED30_ENABLE 0x1 | |
| 762 | #define ASYNC_DATA_ERROR_ENABLE 0x1 | |
| 763 | #define INTERRUPT_LEVEL_1_ENABLE 0x1 | |
| 764 | #define INTERRUPT_LEVEL_2_ENABLE 0x1 | |
| 765 | #define INTERRUPT_LEVEL_3_ENABLE 0x1 | |
| 766 | #define INTERRUPT_LEVEL_4_ENABLE 0x1 | |
| 767 | #define INTERRUPT_LEVEL_5_ENABLE 0x1 | |
| 768 | #define INTERRUPT_LEVEL_6_ENABLE 0x1 | |
| 769 | #define INTERRUPT_LEVEL_7_ENABLE 0x1 | |
| 770 | #define INTERRUPT_LEVEL_8_ENABLE 0x1 | |
| 771 | #define INTERRUPT_LEVEL_9_ENABLE 0x1 | |
| 772 | #define INTERRUPT_LEVEL_10_ENABLE 0x1 | |
| 773 | #define INTERRUPT_LEVEL_11_ENABLE 0x1 | |
| 774 | #define INTERRUPT_LEVEL_12_ENABLE 0x1 | |
| 775 | #define INTERRUPT_LEVEL_13_ENABLE 0x1 | |
| 776 | #define INTERRUPT_LEVEL_14_ENABLE 0x1 | |
| 777 | #define INTERRUPT_LEVEL_15_ENABLE 0x1 | |
| 778 | #define RESERVED31_ENABLE 0x1 | |
| 779 | #define RESERVED32_ENABLE 0x1 | |
| 780 | #define RESERVED33_ENABLE 0x1 | |
| 781 | #define RESERVED34_ENABLE 0x1 | |
| 782 | #define RESERVED35_ENABLE 0x1 | |
| 783 | #define RESERVED36_ENABLE 0x1 | |
| 784 | #define RESERVED37_ENABLE 0x1 | |
| 785 | #define RESERVED38_ENABLE 0x1 | |
| 786 | #define RESERVED39_ENABLE 0x1 | |
| 787 | #define RESERVED40_ENABLE 0x1 | |
| 788 | #define RESERVED41_ENABLE 0x1 | |
| 789 | #define RESERVED42_ENABLE 0x1 | |
| 790 | #define RESERVED43_ENABLE 0x1 | |
| 791 | #define RESERVED44_ENABLE 0x1 | |
| 792 | #define RESERVED45_ENABLE 0x1 | |
| 793 | #define RESERVED46_ENABLE 0x1 | |
| 794 | #define IMPL_DEP_XCPN_0_ENABLE 0x1 | |
| 795 | #define PA_WATCHPOINT_ENABLE 0x1 | |
| 796 | #define VA_WATCHPOINT_ENABLE 0x1 | |
| 797 | #define IA_FAST_MMU_MISS_ENABLE 0x1 | |
| 798 | #define DA_FAST_MMU_MISS_ENABLE 0x1 | |
| 799 | #define FAST_DATA_PROT_ENABLE 0x1 | |
| 800 | #define SPILL_0_NORMAL_ENABLE 0x1 | |
| 801 | #define SPILL_1_NORMAL_ENABLE 0x1 | |
| 802 | #define SPILL_2_NORMAL_ENABLE 0x1 | |
| 803 | #define SPILL_3_NORMAL_ENABLE 0x1 | |
| 804 | #define SPILL_4_NORMAL_ENABLE 0x1 | |
| 805 | #define SPILL_5_NORMAL_ENABLE 0x1 | |
| 806 | #define SPILL_6_NORMAL_ENABLE 0x1 | |
| 807 | #define SPILL_7_NORMAL_ENABLE 0x1 | |
| 808 | #define SPILL_0_OTHER_ENABLE 0x1 | |
| 809 | #define SPILL_1_OTHER_ENABLE 0x1 | |
| 810 | #define SPILL_2_OTHER_ENABLE 0x1 | |
| 811 | #define SPILL_3_OTHER_ENABLE 0x1 | |
| 812 | #define SPILL_4_OTHER_ENABLE 0x1 | |
| 813 | #define SPILL_5_OTHER_ENABLE 0x1 | |
| 814 | #define SPILL_6_OTHER_ENABLE 0x1 | |
| 815 | #define SPILL_7_OTHER_ENABLE 0x1 | |
| 816 | #define FILL_0_NORMAL_ENABLE 0x1 | |
| 817 | #define FILL_1_NORMAL_ENABLE 0x1 | |
| 818 | #define FILL_2_NORMAL_ENABLE 0x1 | |
| 819 | #define FILL_3_NORMAL_ENABLE 0x1 | |
| 820 | #define FILL_4_NORMAL_ENABLE 0x1 | |
| 821 | #define FILL_5_NORMAL_ENABLE 0x1 | |
| 822 | #define FILL_6_NORMAL_ENABLE 0x1 | |
| 823 | #define FILL_7_NORMAL_ENABLE 0x1 | |
| 824 | #define FILL_0_OTHER_ENABLE 0x1 | |
| 825 | #define FILL_1_OTHER_ENABLE 0x1 | |
| 826 | #define FILL_2_OTHER_ENABLE 0x1 | |
| 827 | #define FILL_3_OTHER_ENABLE 0x1 | |
| 828 | #define FILL_4_OTHER_ENABLE 0x1 | |
| 829 | #define FILL_5_OTHER_ENABLE 0x1 | |
| 830 | #define FILL_6_OTHER_ENABLE 0x1 | |
| 831 | #define FILL_7_OTHER_ENABLE 0x1 | |
| 832 | #define TICC_256_ENABLE 0x1 | |
| 833 | #define TICC_257_ENABLE 0x1 | |
| 834 | #define TICC_258_ENABLE 0x1 | |
| 835 | #define TICC_259_ENABLE 0x1 | |
| 836 | #define TICC_260_ENABLE 0x1 | |
| 837 | #define TICC_261_ENABLE 0x1 | |
| 838 | #define TICC_262_ENABLE 0x1 | |
| 839 | #define TICC_263_ENABLE 0x1 | |
| 840 | #define TICC_264_ENABLE 0x1 | |
| 841 | #define TICC_265_ENABLE 0x1 | |
| 842 | #define TICC_266_ENABLE 0x1 | |
| 843 | #define TICC_267_ENABLE 0x1 | |
| 844 | #define TICC_268_ENABLE 0x1 | |
| 845 | #define TICC_269_ENABLE 0x1 | |
| 846 | #define TICC_270_ENABLE 0x1 | |
| 847 | #define TICC_271_ENABLE 0x1 | |
| 848 | #define TICC_272_ENABLE 0x1 | |
| 849 | #define TICC_273_ENABLE 0x1 | |
| 850 | #define TICC_274_ENABLE 0x1 | |
| 851 | #define TICC_275_ENABLE 0x1 | |
| 852 | #define TICC_276_ENABLE 0x1 | |
| 853 | #define TICC_277_ENABLE 0x1 | |
| 854 | #define TICC_278_ENABLE 0x1 | |
| 855 | #define TICC_279_ENABLE 0x1 | |
| 856 | #define TICC_280_ENABLE 0x1 | |
| 857 | #define TICC_281_ENABLE 0x1 | |
| 858 | #define TICC_282_ENABLE 0x1 | |
| 859 | #define TICC_283_ENABLE 0x1 | |
| 860 | #define TICC_284_ENABLE 0x1 | |
| 861 | #define TICC_285_ENABLE 0x1 | |
| 862 | #define TICC_286_ENABLE 0x1 | |
| 863 | #define TICC_287_ENABLE 0x1 | |
| 864 | #define TICC_288_ENABLE 0x1 | |
| 865 | #define TICC_289_ENABLE 0x1 | |
| 866 | #define TICC_290_ENABLE 0x1 | |
| 867 | #define TICC_291_ENABLE 0x1 | |
| 868 | #define TICC_292_ENABLE 0x1 | |
| 869 | #define TICC_293_ENABLE 0x1 | |
| 870 | #define TICC_294_ENABLE 0x1 | |
| 871 | #define TICC_295_ENABLE 0x1 | |
| 872 | #define TICC_296_ENABLE 0x1 | |
| 873 | #define TICC_297_ENABLE 0x1 | |
| 874 | #define TICC_298_ENABLE 0x1 | |
| 875 | #define TICC_299_ENABLE 0x1 | |
| 876 | #define TICC_300_ENABLE 0x1 | |
| 877 | #define TICC_301_ENABLE 0x1 | |
| 878 | #define TICC_302_ENABLE 0x1 | |
| 879 | #define TICC_303_ENABLE 0x1 | |
| 880 | #define TICC_304_ENABLE 0x1 | |
| 881 | #define TICC_305_ENABLE 0x1 | |
| 882 | #define TICC_306_ENABLE 0x1 | |
| 883 | #define TICC_307_ENABLE 0x1 | |
| 884 | #define TICC_308_ENABLE 0x1 | |
| 885 | #define TICC_309_ENABLE 0x1 | |
| 886 | #define TICC_310_ENABLE 0x1 | |
| 887 | #define TICC_311_ENABLE 0x1 | |
| 888 | #define TICC_312_ENABLE 0x1 | |
| 889 | #define TICC_313_ENABLE 0x1 | |
| 890 | #define TICC_314_ENABLE 0x1 | |
| 891 | #define TICC_315_ENABLE 0x1 | |
| 892 | #define TICC_316_ENABLE 0x1 | |
| 893 | #define TICC_317_ENABLE 0x1 | |
| 894 | #define TICC_318_ENABLE 0x1 | |
| 895 | #define TICC_319_ENABLE 0x1 | |
| 896 | #define TICC_320_ENABLE 0x1 | |
| 897 | #define TICC_321_ENABLE 0x1 | |
| 898 | #define TICC_322_ENABLE 0x1 | |
| 899 | #define TICC_323_ENABLE 0x1 | |
| 900 | #define TICC_324_ENABLE 0x1 | |
| 901 | #define TICC_325_ENABLE 0x1 | |
| 902 | #define TICC_326_ENABLE 0x1 | |
| 903 | #define TICC_327_ENABLE 0x1 | |
| 904 | #define TICC_328_ENABLE 0x1 | |
| 905 | #define TICC_329_ENABLE 0x1 | |
| 906 | #define TICC_330_ENABLE 0x1 | |
| 907 | #define TICC_331_ENABLE 0x1 | |
| 908 | #define TICC_332_ENABLE 0x1 | |
| 909 | #define TICC_333_ENABLE 0x1 | |
| 910 | #define TICC_334_ENABLE 0x1 | |
| 911 | #define TICC_335_ENABLE 0x1 | |
| 912 | #define TICC_336_ENABLE 0x1 | |
| 913 | #define TICC_337_ENABLE 0x1 | |
| 914 | #define TICC_338_ENABLE 0x1 | |
| 915 | #define TICC_339_ENABLE 0x1 | |
| 916 | #define TICC_340_ENABLE 0x1 | |
| 917 | #define TICC_341_ENABLE 0x1 | |
| 918 | #define TICC_342_ENABLE 0x1 | |
| 919 | #define TICC_343_ENABLE 0x1 | |
| 920 | #define TICC_344_ENABLE 0x1 | |
| 921 | #define TICC_345_ENABLE 0x1 | |
| 922 | #define TICC_346_ENABLE 0x1 | |
| 923 | #define TICC_347_ENABLE 0x1 | |
| 924 | #define TICC_348_ENABLE 0x1 | |
| 925 | #define TICC_349_ENABLE 0x1 | |
| 926 | #define TICC_350_ENABLE 0x1 | |
| 927 | #define TICC_351_ENABLE 0x1 | |
| 928 | #define TICC_352_ENABLE 0x1 | |
| 929 | #define TICC_353_ENABLE 0x1 | |
| 930 | #define TICC_354_ENABLE 0x1 | |
| 931 | #define TICC_355_ENABLE 0x1 | |
| 932 | #define TICC_356_ENABLE 0x1 | |
| 933 | #define TICC_357_ENABLE 0x1 | |
| 934 | #define TICC_358_ENABLE 0x1 | |
| 935 | #define TICC_359_ENABLE 0x1 | |
| 936 | #define TICC_360_ENABLE 0x1 | |
| 937 | #define TICC_361_ENABLE 0x1 | |
| 938 | #define TICC_362_ENABLE 0x1 | |
| 939 | #define TICC_363_ENABLE 0x1 | |
| 940 | #define TICC_364_ENABLE 0x1 | |
| 941 | #define TICC_365_ENABLE 0x1 | |
| 942 | #define TICC_366_ENABLE 0x1 | |
| 943 | #define TICC_367_ENABLE 0x1 | |
| 944 | #define TICC_368_ENABLE 0x1 | |
| 945 | #define TICC_369_ENABLE 0x1 | |
| 946 | #define TICC_370_ENABLE 0x1 | |
| 947 | #define TICC_371_ENABLE 0x1 | |
| 948 | #define TICC_372_ENABLE 0x1 | |
| 949 | #define TICC_373_ENABLE 0x1 | |
| 950 | #define TICC_374_ENABLE 0x1 | |
| 951 | #define TICC_375_ENABLE 0x1 | |
| 952 | #define TICC_376_ENABLE 0x1 | |
| 953 | #define TICC_377_ENABLE 0x1 | |
| 954 | #define TICC_378_ENABLE 0x1 | |
| 955 | #define TICC_379_ENABLE 0x1 | |
| 956 | #define TICC_380_ENABLE 0x1 | |
| 957 | #define TICC_381_ENABLE 0x1 | |
| 958 | #define TICC_382_ENABLE 0x1 | |
| 959 | #define TICC_383_ENABLE 0x1 | |
| 960 | #endif | |
| 961 | ||
| 962 | #endif | |
| 963 | ||
| 964 | /* __XLATE_H__ */ |