[OpenSPARC-T2-DV] / verif / diag / assembly / isa3 / aes_kat_ctr.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: aes_kat_ctr.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO
#include "hboot.s"
#define NUM_MODE_PATTERNS 5
#define NUM_PATTERNS 3*NUM_MODE_PATTERNS
	
/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:		/* test begin */
        !# Switch to hpriv mode
	ta T_CHANGE_HPRIV

	
	!# Execute Main Diag ..
	!# setup ASI register to point to SPU
        wr %g0, 0x40, %asi
	
	!# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
	and %l1, 0xf, %l2
	cmp %g0, %l2
	bne,pn %xcc, fail
	nop 

	!# allocate control word queue (e.g., setup head/tail/first/last registers)
	!# %l6  CWQ_BASE
	setx CWQ_BASE, %g1, %l6
		
	!# write base addr to first, head, and tail ptr
	!# first store to first
	stxa	%l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
	!# Mask off upper 16 bits
	setx 0x0000ffffffffffff, %l5, %l0
	and %l0, %l6, %l2
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop

	!# then to head
	stxa	%l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop
	
	!# then to tail
	stxa	%l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop
	
	!# then end of CWQ region to LAST
	setx CWQ_LAST, %g1, %l5
	stxa	%l5, [%g0 + ASI_SPU_CWQ_LAST] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_LAST] %asi, %l1

	!# Mask off upper 16 bits
	and	%l0, %l5, %l2
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop

	setx	0x0080000000000000, %l1, %g4  !# Encrypt/Decrypt flag (bit in CWQ)
	setx plaintext_128, %g1, %l2
	setx plaintext_addr, %g1, %l1
	stx  %l2, [%l1]
	setx ciphertext_128, %g1, %l2
	setx ciphertext_addr, %g1, %l1
	stx  %l2, [%l1]

	mov  0, %g5 !# Encrypt/Decrypt counter
encrypt_decrypt_loop:			
	mov 0, %i4 !# Loop counter
	mov 0, %i5 !# For plaintext/cipher/iv offset
	mov 0, %i7 !# For key offset
	mov 0, %g3 !# index
	
kat_loop:			
	!# Build the first control word, for the first AES vector.
	!# First build up word 0
	!# For AES, set op = 64, Enc=1, SOB=EOB=1, SFAS=0, Int=CoreID=0, AuthType=0, EncType=13, status=0, Len=15
	setx	0x406000001300000f, %l1, %l2
	addcc   %i4, 0-NUM_MODE_PATTERNS, %g0
	addC	0, %g0, %g1	!# Add 1 on 192 bit keys => EncType=17
	addcc	%i4, 0-NUM_MODE_PATTERNS*2, %g0
	addC	0, %g1, %g1	!# Add 2 on 256 bit keys => EncType=1b
	sllx	%g1, 26, %g1
	or	%l2, %g1, %l2
	or	%l2, %g4, %l2

	!# %l6 points to CWQ_BASE
	!# Note:	All CWQ entry addresses must be physical!
	stx	%l2, [%l6 + 0x0]

		
	!# Write source address to next CW field
	setx plaintext_addr, %g1, %l2
	ldx	[%l2], %l2
	add     %i5, %l2, %l2
	stx	%l2, [%l6+0x8]

	!# Write 0's to the next 3 CW fields as they are not used
	stx	%g0, [%l6+0x10]
	stx	%g0, [%l6+0x18]
	stx	%g0, [%l6+0x20]

	!# Write address of Encryption key 
	setx aes_key_128, %g1, %o2
	add     %i7, %o2, %o2
	stx	%o2, [%l6 + 0x28] 

	!# Encryption IV
	setx	ctr_iv_128, %g1, %l2
	add	%i5, %l2, %l2
	stx	%l2, [%l6+0x30]

	!# Finally write destination address to last CW field
	setx result, %g1, %o3
	stx	%o3, [%l6 + 0x38] 

	!# Make sure all these stores get to memory before we start
	membar #Sync

	!# Now add 1 (actually 8*8B) to tail pointer 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
	add	%l2, 0x40, %l2
	stxa	%l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop
	
	!# Kick off the CWQ operation by writing to the CWQ_CSR
	!# Set the enabled bit and reset the other bits 
	or	%g0, 0x1, %g1
	stxa	%g1,	[%g0 + ASI_SPU_CWQ_CSR] %asi

	!# Try CWQ_SYNC operation...
	ldxa    [%g0 + 0x30] %asi, %l1

	!# Check for protocol error - Riesling should only have busy bit set
	ldxa	[%g0 + ASI_SPU_CWQ_CSR] %asi,	%l1
	
	
	!# check the results...first check the data
       	!# Each AES block is only 16B long (divide by 8 anyway)	
	or %g0, 0x2, %i0
	!# set %l3 to be base address of result area, and
	!# %l4 to be base address of known ciphertext area
	setx	result, %g1, %l3
	setx	ciphertext_addr, %g1, %l4
	ldx	[%l4], %l4
	add	%l4, %i5, %l4
	or	%g0, %g0, %g3
		
more1:
	ldx	[%l3 + %g3], %l1
	ldx	[%l4 + %g3], %l2
	cmp	%l1, %l2
	bne,pn	%xcc, fail
	add	%g3, 0x8, %g3	!# i++
	addcc	%i0, -1, %i0
	bgt	more1
	nop

	add	%l6, 0x40, %l6   !# next CWQ
	add     %i5, 0x10, %i5   !# next pattern
	add	%i4, 1, %i4	 !# loop counter
	
	cmp	%i4, NUM_MODE_PATTERNS
	ble     kat_loop
	add	%i7, 0x10, %i7   !# add offset for 128bit keys in branch delay
	
	add	%i7, 0x10, %i7   !# add offset for 192/256 bit keys (keep them aligned!)
	
	cmp	%i4, NUM_PATTERNS
	bl      kat_loop
	nop

	!# Swap plain/cipher address
	setx plaintext_addr, %g1, %l1
	setx ciphertext_addr, %g1, %l2
	ldx	[%l1], %g1
	ldx	[%l2], %g2
	stx	%g2, [%l1]
	stx	%g1, [%l2]

	setx	0x0080000000000000, %l1, %g1  !# Encrypt/Decrypt flag (bit in CWQ)
	xor	%g1, %g4, %g4
	inc	%g5
	cmp	%g5, 2
	bl	encrypt_decrypt_loop 
	nop	
		
	EXIT_GOOD

fail:
	EXIT_BAD

	
/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
scratch_area:

!# temporary area for storing expected result
.align 16
result:	
.xword 0xDEADBEEFDEADBEEF, 0xDEADBEEFDEADBEEF			


!# CWQ data area, set aside 512 CW's worth
!# 512*8*8 = 32KB
.align 32*1024
CWQ_BASE:		
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.align 32*1024
CWQ_LAST:	

.align 16
ciphertext_addr:
.xword 0,0
	
plaintext_addr:	
.xword 0,0		
		
.align 16
plaintext_128:
.xword 0x53696E676C652062, 0x6C6F636B206D7367
.xword 0x0001020304050607, 0x08090A0B0C0D0E0F	
.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
		
plaintext_192:
.xword 0x53696E676C652062, 0x6C6F636B206D7367
.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
.xword 0x1011121314151617, 0x18191A1B1C1D1E1F

plaintext_256:	
.xword 0x53696E676C652062, 0x6C6F636B206D7367
.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
	
.align 16
aes_key_128:
.xword 0xAE6852F8121067CC, 0x4BF7A5765577F39E
.xword 0x7E24067817FAE0D7, 0x43D6CE1F32539163
.xword 0x7E24067817FAE0D7, 0x43D6CE1F32539163
.xword 0x7691BE035E5020A8, 0xAC6E618529F9A0DC
.xword 0x7691BE035E5020A8, 0xAC6E618529F9A0DC
	
aes_key_192:
.xword 0x16AF5B145FC9F579, 0xC175F93E3BFB0EED, 0x863D06CCFDB78515, 0x0
.xword 0x7C5CB2401B3DC33C, 0x19E7340819E0F69C, 0x678C3DB8E6F6A91A, 0x0
.xword 0x7C5CB2401B3DC33C, 0x19E7340819E0F69C, 0x678C3DB8E6F6A91A, 0x0
.xword 0x02BF391EE8ECB159, 0xB959617B0965279B, 0xF59B60A786D3E0FE, 0x0
.xword 0x02BF391EE8ECB159, 0xB959617B0965279B, 0xF59B60A786D3E0FE, 0x0

aes_key_256:
.xword 0x776BEFF2851DB06F, 0x4C8A0542C8696F6C, 0x6A81AF1EEC96B4D3, 0x7FC1D689E6C1C104
.xword 0xF6D66D6BD52D59BB, 0x0796365879EFF886, 0xC66DD51A5B6A9974, 0x4B50590C87A23884
.xword 0xF6D66D6BD52D59BB, 0x0796365879EFF886, 0xC66DD51A5B6A9974, 0x4B50590C87A23884
.xword 0xFF7A617CE69148E4, 0xF1726E2F43581DE2, 0xAA62D9F805532EDF, 0xF1EED687FB54153D
.xword 0xFF7A617CE69148E4, 0xF1726E2F43581DE2, 0xAA62D9F805532EDF, 0xF1EED687FB54153D

.align 16
ciphertext_128:
.xword 0xE4095D4FB7A7B379, 0x2D6175A3261311B8
.xword 0x5104A106168A72D9, 0x790D41EE8EDAD388
.xword 0xEB2E1EFC46DA57C8, 0xFCE630DF9141BE28
.xword 0xC1CF48A89F2FFDD9, 0xCF4652E9EFDB72D7
.xword 0x4540A42BDE6D7836, 0xD59A5CEAAEF31053
	
ciphertext_192:
.xword 0x4B55384FE259C9C8, 0x4E7935A003CBE928
.xword 0x453243FC609B2332, 0x7EDFAAFA7131CD9F
.xword 0x8490701C5AD4A79C, 0xFC1FE0FF42F4FB00
.xword 0x96893FC55E5C722F, 0x540B7DD1DDF7E758
.xword 0xD288BC95C6916588, 0x4536C811662F2188

ciphertext_256:
.xword 0x145AD01DBF824EC7, 0x560863DC71E3E0C0
.xword 0xF05E231B3894612C, 0x49EE000B804EB2A9
.xword 0xB8306B508F839D6A, 0x5530831D9344AF1C
.xword 0xEB6C52821D0BBBF7, 0xCE7594462ACA4FAA
.xword 0xB407DF866569FD07, 0xF48CC0B583D6071F
	
.align 16
ctr_iv_128:
.xword 0x0000003000000000, 0x0000000000000001
.xword 0x006CB6DBC0543B59, 0xDA48D90B00000001
.xword 0x006CB6DBC0543B59, 0xDA48D90B00000002
.xword 0x00E0017B27777F3F, 0x4A1786F000000001
.xword 0x00E0017B27777F3F, 0x4A1786F000000002
		
ctr_iv_192:	
.xword 0x0000004836733C14, 0x7D6D93CB00000001
.xword 0x0096B03B020C6EAD, 0xC2CB500D00000001
.xword 0x0096B03B020C6EAD, 0xC2CB500D00000002
.xword 0x0007BDFD5CBD6027, 0x8DCC091200000001
.xword 0x0007BDFD5CBD6027, 0x8DCC091200000002
	
ctr_iv_256:	
.xword 0x00000060DB5672C9, 0x7AA8F0B200000001
.xword 0x00FAAC24C1585EF1, 0x5A43D87500000001
.xword 0x00FAAC24C1585EF1, 0x5A43D87500000002
.xword 0x001CC5B751A51D70, 0xA1C1114800000001
.xword 0x001CC5B751A51D70, 0xA1C1114800000002	
	
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: aes_kat_ctr.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39	#include "hboot.s"
	40	#define NUM_MODE_PATTERNS 5
	41	#define NUM_PATTERNS 3*NUM_MODE_PATTERNS
	42
	43	/************************************************************************
	44	Test case code start
	45	************************************************************************/
	46
	47	.text
	48	.global main
	49
	50	main: /* test begin */
	51	!# Switch to hpriv mode
	52	ta T_CHANGE_HPRIV
	53
	54
	55	!# Execute Main Diag ..
	56	!# setup ASI register to point to SPU
	57	wr %g0, 0x40, %asi
	58
	59	!# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
	60	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
	61	and %l1, 0xf, %l2
	62	cmp %g0, %l2
	63	bne,pn %xcc, fail
	64	nop
65
66	!# allocate control word queue (e.g., setup head/tail/first/last registers)
67	!# %l6 CWQ_BASE
68	setx CWQ_BASE, %g1, %l6
69
70	!# write base addr to first, head, and tail ptr
71	!# first store to first
72	stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
73	ldxa [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
74	!# Mask off upper 16 bits
75	setx 0x0000ffffffffffff, %l5, %l0
76	and %l0, %l6, %l2
77	cmp %l1, %l2
78	bne,pn %xcc, fail
79	nop
80
81	!# then to head
82	stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
83	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
84	cmp %l1, %l2
85	bne,pn %xcc, fail
86	nop
87
88	!# then to tail
89	stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
90	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
91	cmp %l1, %l2
92	bne,pn %xcc, fail
93	nop
94
95	!# then end of CWQ region to LAST
96	setx CWQ_LAST, %g1, %l5
97	stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
98	ldxa [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
99
100	!# Mask off upper 16 bits
101	and %l0, %l5, %l2
102	cmp %l1, %l2
103	bne,pn %xcc, fail
104	nop
105
106	setx 0x0080000000000000, %l1, %g4 !# Encrypt/Decrypt flag (bit in CWQ)
107	setx plaintext_128, %g1, %l2
108	setx plaintext_addr, %g1, %l1
109	stx %l2, [%l1]
110	setx ciphertext_128, %g1, %l2
111	setx ciphertext_addr, %g1, %l1
112	stx %l2, [%l1]
113
114	mov 0, %g5 !# Encrypt/Decrypt counter
115	encrypt_decrypt_loop:
116	mov 0, %i4 !# Loop counter
117	mov 0, %i5 !# For plaintext/cipher/iv offset
118	mov 0, %i7 !# For key offset
119	mov 0, %g3 !# index
120
121	kat_loop:
122	!# Build the first control word, for the first AES vector.
123	!# First build up word 0
124	!# For AES, set op = 64, Enc=1, SOB=EOB=1, SFAS=0, Int=CoreID=0, AuthType=0, EncType=13, status=0, Len=15
125	setx 0x406000001300000f, %l1, %l2
126	addcc %i4, 0-NUM_MODE_PATTERNS, %g0
127	addC 0, %g0, %g1 !# Add 1 on 192 bit keys => EncType=17
128	addcc %i4, 0-NUM_MODE_PATTERNS*2, %g0
129	addC 0, %g1, %g1 !# Add 2 on 256 bit keys => EncType=1b
130	sllx %g1, 26, %g1
131	or %l2, %g1, %l2
132	or %l2, %g4, %l2
133
134	!# %l6 points to CWQ_BASE
135	!# Note: All CWQ entry addresses must be physical!
136	stx %l2, [%l6 + 0x0]
137
138
139	!# Write source address to next CW field
140	setx plaintext_addr, %g1, %l2
141	ldx [%l2], %l2
142	add %i5, %l2, %l2
143	stx %l2, [%l6+0x8]
144
145	!# Write 0's to the next 3 CW fields as they are not used
146	stx %g0, [%l6+0x10]
147	stx %g0, [%l6+0x18]
148	stx %g0, [%l6+0x20]
149
150	!# Write address of Encryption key
151	setx aes_key_128, %g1, %o2
152	add %i7, %o2, %o2
153	stx %o2, [%l6 + 0x28]
154
155	!# Encryption IV
156	setx ctr_iv_128, %g1, %l2
157	add %i5, %l2, %l2
158	stx %l2, [%l6+0x30]
159
160	!# Finally write destination address to last CW field
161	setx result, %g1, %o3
162	stx %o3, [%l6 + 0x38]
163
164	!# Make sure all these stores get to memory before we start
165	membar #Sync
166
167	!# Now add 1 (actually 8*8B) to tail pointer
168	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
169	add %l2, 0x40, %l2
170	stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
171	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
172	cmp %l1, %l2
173	bne,pn %xcc, fail
174	nop
175
176	!# Kick off the CWQ operation by writing to the CWQ_CSR
177	!# Set the enabled bit and reset the other bits
178	or %g0, 0x1, %g1
179	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
180
181	!# Try CWQ_SYNC operation...
182	ldxa [%g0 + 0x30] %asi, %l1
183
184	!# Check for protocol error - Riesling should only have busy bit set
185	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
186
187
188	!# check the results...first check the data
189	!# Each AES block is only 16B long (divide by 8 anyway)
190	or %g0, 0x2, %i0
191	!# set %l3 to be base address of result area, and
192	!# %l4 to be base address of known ciphertext area
193	setx result, %g1, %l3
194	setx ciphertext_addr, %g1, %l4
195	ldx [%l4], %l4
196	add %l4, %i5, %l4
197	or %g0, %g0, %g3
198
199	more1:
200	ldx [%l3 + %g3], %l1
201	ldx [%l4 + %g3], %l2
202	cmp %l1, %l2
203	bne,pn %xcc, fail
204	add %g3, 0x8, %g3 !# i++
205	addcc %i0, -1, %i0
206	bgt more1
207	nop
208
209	add %l6, 0x40, %l6 !# next CWQ
210	add %i5, 0x10, %i5 !# next pattern
211	add %i4, 1, %i4 !# loop counter
212
213	cmp %i4, NUM_MODE_PATTERNS
214	ble kat_loop
215	add %i7, 0x10, %i7 !# add offset for 128bit keys in branch delay
216
217	add %i7, 0x10, %i7 !# add offset for 192/256 bit keys (keep them aligned!)
218
219	cmp %i4, NUM_PATTERNS
220	bl kat_loop
221	nop
222
223	!# Swap plain/cipher address
224	setx plaintext_addr, %g1, %l1
225	setx ciphertext_addr, %g1, %l2
226	ldx [%l1], %g1
227	ldx [%l2], %g2
228	stx %g2, [%l1]
229	stx %g1, [%l2]
230
231	setx 0x0080000000000000, %l1, %g1 !# Encrypt/Decrypt flag (bit in CWQ)
232	xor %g1, %g4, %g4
233	inc %g5
234	cmp %g5, 2
235	bl encrypt_decrypt_loop
236	nop
237
238	EXIT_GOOD
239
240	fail:
241	EXIT_BAD
242
243
244	/************************************************************************
245	Test case data start
246	************************************************************************/
247	.data
248	user_data_start:
249	scratch_area:
250
251	!# temporary area for storing expected result
252	.align 16
253	result:
254	.xword 0xDEADBEEFDEADBEEF, 0xDEADBEEFDEADBEEF
255
256
257
258	!# CWQ data area, set aside 512 CW's worth
259	!# 51288 = 32KB
260	.align 32*1024
261	CWQ_BASE:
262	.xword 0xAAAAAAAAAAAAAAA
263	.xword 0xAAAAAAAAAAAAAAA
264	.xword 0xAAAAAAAAAAAAAAA
265	.xword 0xAAAAAAAAAAAAAAA
266	.xword 0xAAAAAAAAAAAAAAA
267	.xword 0xAAAAAAAAAAAAAAA
268	.xword 0xAAAAAAAAAAAAAAA
269	.xword 0xAAAAAAAAAAAAAAA
270	.align 32*1024
271	CWQ_LAST:
272
273	.align 16
274	ciphertext_addr:
275	.xword 0,0
276
277	plaintext_addr:
278	.xword 0,0
279
280	.align 16
281	plaintext_128:
282	.xword 0x53696E676C652062, 0x6C6F636B206D7367
283	.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
284	.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
285	.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
286	.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
287
288	plaintext_192:
289	.xword 0x53696E676C652062, 0x6C6F636B206D7367
290	.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
291	.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
292	.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
293	.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
294
295	plaintext_256:
296	.xword 0x53696E676C652062, 0x6C6F636B206D7367
297	.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
298	.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
299	.xword 0x0001020304050607, 0x08090A0B0C0D0E0F
300	.xword 0x1011121314151617, 0x18191A1B1C1D1E1F
301
302	.align 16
303	aes_key_128:
304	.xword 0xAE6852F8121067CC, 0x4BF7A5765577F39E
305	.xword 0x7E24067817FAE0D7, 0x43D6CE1F32539163
306	.xword 0x7E24067817FAE0D7, 0x43D6CE1F32539163
307	.xword 0x7691BE035E5020A8, 0xAC6E618529F9A0DC
308	.xword 0x7691BE035E5020A8, 0xAC6E618529F9A0DC
309
310	aes_key_192:
311	.xword 0x16AF5B145FC9F579, 0xC175F93E3BFB0EED, 0x863D06CCFDB78515, 0x0
312	.xword 0x7C5CB2401B3DC33C, 0x19E7340819E0F69C, 0x678C3DB8E6F6A91A, 0x0
313	.xword 0x7C5CB2401B3DC33C, 0x19E7340819E0F69C, 0x678C3DB8E6F6A91A, 0x0
314	.xword 0x02BF391EE8ECB159, 0xB959617B0965279B, 0xF59B60A786D3E0FE, 0x0
315	.xword 0x02BF391EE8ECB159, 0xB959617B0965279B, 0xF59B60A786D3E0FE, 0x0
316
317	aes_key_256:
318	.xword 0x776BEFF2851DB06F, 0x4C8A0542C8696F6C, 0x6A81AF1EEC96B4D3, 0x7FC1D689E6C1C104
319	.xword 0xF6D66D6BD52D59BB, 0x0796365879EFF886, 0xC66DD51A5B6A9974, 0x4B50590C87A23884
320	.xword 0xF6D66D6BD52D59BB, 0x0796365879EFF886, 0xC66DD51A5B6A9974, 0x4B50590C87A23884
321	.xword 0xFF7A617CE69148E4, 0xF1726E2F43581DE2, 0xAA62D9F805532EDF, 0xF1EED687FB54153D
322	.xword 0xFF7A617CE69148E4, 0xF1726E2F43581DE2, 0xAA62D9F805532EDF, 0xF1EED687FB54153D
323
324	.align 16
325	ciphertext_128:
326	.xword 0xE4095D4FB7A7B379, 0x2D6175A3261311B8
327	.xword 0x5104A106168A72D9, 0x790D41EE8EDAD388
328	.xword 0xEB2E1EFC46DA57C8, 0xFCE630DF9141BE28
329	.xword 0xC1CF48A89F2FFDD9, 0xCF4652E9EFDB72D7
330	.xword 0x4540A42BDE6D7836, 0xD59A5CEAAEF31053
331
332	ciphertext_192:
333	.xword 0x4B55384FE259C9C8, 0x4E7935A003CBE928
334	.xword 0x453243FC609B2332, 0x7EDFAAFA7131CD9F
335	.xword 0x8490701C5AD4A79C, 0xFC1FE0FF42F4FB00
336	.xword 0x96893FC55E5C722F, 0x540B7DD1DDF7E758
337	.xword 0xD288BC95C6916588, 0x4536C811662F2188
338
339	ciphertext_256:
340	.xword 0x145AD01DBF824EC7, 0x560863DC71E3E0C0
341	.xword 0xF05E231B3894612C, 0x49EE000B804EB2A9
342	.xword 0xB8306B508F839D6A, 0x5530831D9344AF1C
343	.xword 0xEB6C52821D0BBBF7, 0xCE7594462ACA4FAA
344	.xword 0xB407DF866569FD07, 0xF48CC0B583D6071F
345
346	.align 16
347	ctr_iv_128:
348	.xword 0x0000003000000000, 0x0000000000000001
349	.xword 0x006CB6DBC0543B59, 0xDA48D90B00000001
350	.xword 0x006CB6DBC0543B59, 0xDA48D90B00000002
351	.xword 0x00E0017B27777F3F, 0x4A1786F000000001
352	.xword 0x00E0017B27777F3F, 0x4A1786F000000002
353
354	ctr_iv_192:
355	.xword 0x0000004836733C14, 0x7D6D93CB00000001
356	.xword 0x0096B03B020C6EAD, 0xC2CB500D00000001
357	.xword 0x0096B03B020C6EAD, 0xC2CB500D00000002
358	.xword 0x0007BDFD5CBD6027, 0x8DCC091200000001
359	.xword 0x0007BDFD5CBD6027, 0x8DCC091200000002
360
361	ctr_iv_256:
362	.xword 0x00000060DB5672C9, 0x7AA8F0B200000001
363	.xword 0x00FAAC24C1585EF1, 0x5A43D87500000001
364	.xword 0x00FAAC24C1585EF1, 0x5A43D87500000002
365	.xword 0x001CC5B751A51D70, 0xA1C1114800000001
366	.xword 0x001CC5B751A51D70, 0xA1C1114800000002
367
368	.end