[OpenSPARC-T2-DV] / verif / diag / assembly / isa3 / isa3_asi_cmp_core_1.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: isa3_asi_cmp_core_1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
!#include "nmacros.h"
    
#include "hboot.s"


!!!!!!!!!!!!!!!!!! assumes only 1 thread of core 0 running  !!!
#define CMP_CORE_RUNNING_STATUS_EXP %o1
#define CMP_CORE_AVAIL_EXP    0xff
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    
#define ALL1S  0xffffffffffffffff

    
/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:

    
 	ta	T_CHANGE_HPRIV  ! run in Hpriv mode
 	nop
 	rdth_id ! get thread ID in %o1
!     cmp %o1, 0
!     bne wrong_thread ! only thread zero allowed!!!
    nop
        
!
! Thread Start
!
thread_0:

    !rdth_id ! get thread ID in %o1
    mov     1,  %o2
    sllx    %o2,    %o1,   %o1

    wr      %g0,    ASI_CMP_CORE,   %asi
    
    ! ASI_CMP_CORE_AVAIL:   set at foundry  
    ! RO
    ldxa    [%g0 + ASI_CMP_CORE_AVAIL] %asi,    %i0
    cmp     %i0,    CMP_CORE_AVAIL_EXP
!%i0 will hold expected value for many reads below    
    bne     test_failed
    mov      %g0,  %l0

enabled:        
    ! ASI_CMP_CORE_ENABLE_STATUS = core enabled
    ! RO
    ldxa    [%g0 + ASI_CMP_CORE_ENABLED] %asi,    %l0
    cmp     %l0,   %i0 !CMP_CORE_ENABLED_EXP
    bne     test_failed
    mov      %g0,  %l0
    
    ! ASI_CMP_CORE_ENABLE:    write to disable thread later after a reset.
    ! the reg value is moved to ASI_CMP_CORE_ENABLE_STATUS on next reset
    ! R/W
    ! must keep threads 0 & 4 enabled.
    ! non available threads will return 0.
    setx    0x5555555555555555,  %g1,    %l1
    stxa    %l1,    [%g0 + ASI_CMP_CORE_ENABLE] %asi
	ldxa    [%g0 + ASI_CMP_CORE_ENABLE] %asi,   %l0
    cmp     %l0,   %i0 ! non available threads will return 0, else ff
    bne     test_failed
    mov     %g0,  %l0
    mov     %g0,  %l1
    stxa    %l1,    [%g0 + ASI_CMP_CORE_ENABLE] %asi ! write 0
	ldxa    [%g0 + ASI_CMP_CORE_ENABLE] %asi,   %l0
    cmp     %l0,   %i0 ! cant self disable so will get ff 
    bne     test_failed
    mov      %g0,  %l0
    
running:        
    ! Bit mask of virtual cores that are 
    ! currently active. 1 = active
    ! avail & enable & running & !parked ???
    ! RO
    ldxa    [%g0 + ASI_CMP_CORE_RUNNING_STATUS] %asi,    %l0
    cmp     %l0,    CMP_CORE_RUNNING_STATUS_EXP
    bne     test_failed
    mov      %g0,  %l0

        
    ! Bit mask to control which virtual
    ! cores are running and which are 
    ! parked (r/w). 1= active
    ! R/W
    setx    ALL1S,  %g1,    %l1
    stxa    %l1,    [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi
	ldxa    [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi,   %l0
    cmp     %l0,   %i0
    bne     test_failed
    mov     %g0,  %l0
    mov     CMP_CORE_RUNNING_STATUS_EXP,  %l1
    stxa    %l1,    [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi
	ldxa    [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi,   %l0
    cmp     %l1,    %l0
    bne     test_failed
    mov     %g0,  %l0
	
parking:    
    ! Bit mask to control which virtual
    ! cores are running and which are 
    ! parked (r/w). 1= active
    ! W
    setx    ALL1S,  %g1,    %l1
    stxa    %l1,    [%g0 + ASI_CMP_CORE_RUNNING_W1S] %asi
    ldxa    [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi,   %l0
    cmp     %l0,    %i0
    bne     test_failed
    mov     %g0,  %l0

    ! cant park all from >1 threads at once, results may not be predictable
    setx    ALL1S,  %g1,    %l1
    xor     %l1,    CMP_CORE_RUNNING_STATUS_EXP, %l1
    stxa    %l1,    [%g0 + ASI_CMP_CORE_RUNNING_W1C] %asi
	ldxa    [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi,   %l0
    cmp     %l0,    CMP_CORE_RUNNING_STATUS_EXP
    bne     test_failed
    mov     %g0,  %l0
    
xir:    
    ! ASI_CMP_XIR_STEERING
    ! R/W
    setx    ALL1S,  %g1,    %l1
    stxa    %l1,    [%g0 + ASI_CMP_XIR_STEERING] %asi
	ldxa    [%g0 + ASI_CMP_XIR_STEERING] %asi,   %l0
    and     %l1, %i0, %l1
    cmp     %l0,    %i0 !CMP_CORE_ENABLED_EXP
    bne     test_failed
    mov     %g0,  %l0
    mov     %g0,  %l1
    stxa    %l1,    [%g0 + ASI_CMP_XIR_STEERING] %asi
	ldxa    [%g0 + ASI_CMP_XIR_STEERING] %asi,   %l0
    cmp     %l1,    %l0
    bne     test_failed
    mov     %g0,  %l0
    
	
test_passed:
	EXIT_GOOD

wrong_thread:
    nop
! $!E!V trig_pc_d(1, @VA(.MAIN.wrong_thread)) -> printf("This diag only runs on thread ZERO!")
    
test_failed:
    EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
.xword 0x0
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: isa3_asi_cmp_core_1.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40	!#include "nmacros.h"
	41
	42	#include "hboot.s"
	43
	44
	45	!!!!!!!!!!!!!!!!!! assumes only 1 thread of core 0 running !!!
	46	#define CMP_CORE_RUNNING_STATUS_EXP %o1
	47	#define CMP_CORE_AVAIL_EXP 0xff
	48	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	49
	50	#define ALL1S 0xffffffffffffffff
	51
	52
	53	/************************************************************************
	54	Test case code start
	55	************************************************************************/
	56
	57	.text
	58	.global main
	59
	60	main:
	61
	62
	63	ta T_CHANGE_HPRIV ! run in Hpriv mode
	64	nop
65	rdth_id ! get thread ID in %o1
66	! cmp %o1, 0
67	! bne wrong_thread ! only thread zero allowed!!!
68	nop
69
70	!
71	! Thread Start
72	!
73	thread_0:
74
75	!rdth_id ! get thread ID in %o1
76	mov 1, %o2
77	sllx %o2, %o1, %o1
78
79	wr %g0, ASI_CMP_CORE, %asi
80
81	! ASI_CMP_CORE_AVAIL: set at foundry
82	! RO
83	ldxa [%g0 + ASI_CMP_CORE_AVAIL] %asi, %i0
84	cmp %i0, CMP_CORE_AVAIL_EXP
85	!%i0 will hold expected value for many reads below
86	bne test_failed
87	mov %g0, %l0
88
89	enabled:
90	! ASI_CMP_CORE_ENABLE_STATUS = core enabled
91	! RO
92	ldxa [%g0 + ASI_CMP_CORE_ENABLED] %asi, %l0
93	cmp %l0, %i0 !CMP_CORE_ENABLED_EXP
94	bne test_failed
95	mov %g0, %l0
96
97	! ASI_CMP_CORE_ENABLE: write to disable thread later after a reset.
98	! the reg value is moved to ASI_CMP_CORE_ENABLE_STATUS on next reset
99	! R/W
100	! must keep threads 0 & 4 enabled.
101	! non available threads will return 0.
102	setx 0x5555555555555555, %g1, %l1
103	stxa %l1, [%g0 + ASI_CMP_CORE_ENABLE] %asi
104	ldxa [%g0 + ASI_CMP_CORE_ENABLE] %asi, %l0
105	cmp %l0, %i0 ! non available threads will return 0, else ff
106	bne test_failed
107	mov %g0, %l0
108	mov %g0, %l1
109	stxa %l1, [%g0 + ASI_CMP_CORE_ENABLE] %asi ! write 0
110	ldxa [%g0 + ASI_CMP_CORE_ENABLE] %asi, %l0
111	cmp %l0, %i0 ! cant self disable so will get ff
112	bne test_failed
113	mov %g0, %l0
114
115	running:
116	! Bit mask of virtual cores that are
117	! currently active. 1 = active
118	! avail & enable & running & !parked ???
119	! RO
120	ldxa [%g0 + ASI_CMP_CORE_RUNNING_STATUS] %asi, %l0
121	cmp %l0, CMP_CORE_RUNNING_STATUS_EXP
122	bne test_failed
123	mov %g0, %l0
124
125
126	! Bit mask to control which virtual
127	! cores are running and which are
128	! parked (r/w). 1= active
129	! R/W
130	setx ALL1S, %g1, %l1
131	stxa %l1, [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi
132	ldxa [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi, %l0
133	cmp %l0, %i0
134	bne test_failed
135	mov %g0, %l0
136	mov CMP_CORE_RUNNING_STATUS_EXP, %l1
137	stxa %l1, [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi
138	ldxa [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi, %l0
139	cmp %l1, %l0
140	bne test_failed
141	mov %g0, %l0
142
143	parking:
144	! Bit mask to control which virtual
145	! cores are running and which are
146	! parked (r/w). 1= active
147	! W
148	setx ALL1S, %g1, %l1
149	stxa %l1, [%g0 + ASI_CMP_CORE_RUNNING_W1S] %asi
150	ldxa [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi, %l0
151	cmp %l0, %i0
152	bne test_failed
153	mov %g0, %l0
154
155	! cant park all from >1 threads at once, results may not be predictable
156	setx ALL1S, %g1, %l1
157	xor %l1, CMP_CORE_RUNNING_STATUS_EXP, %l1
158	stxa %l1, [%g0 + ASI_CMP_CORE_RUNNING_W1C] %asi
159	ldxa [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi, %l0
160	cmp %l0, CMP_CORE_RUNNING_STATUS_EXP
161	bne test_failed
162	mov %g0, %l0
163
164	xir:
165	! ASI_CMP_XIR_STEERING
166	! R/W
167	setx ALL1S, %g1, %l1
168	stxa %l1, [%g0 + ASI_CMP_XIR_STEERING] %asi
169	ldxa [%g0 + ASI_CMP_XIR_STEERING] %asi, %l0
170	and %l1, %i0, %l1
171	cmp %l0, %i0 !CMP_CORE_ENABLED_EXP
172	bne test_failed
173	mov %g0, %l0
174	mov %g0, %l1
175	stxa %l1, [%g0 + ASI_CMP_XIR_STEERING] %asi
176	ldxa [%g0 + ASI_CMP_XIR_STEERING] %asi, %l0
177	cmp %l1, %l0
178	bne test_failed
179	mov %g0, %l0
180
181
182
183	test_passed:
184	EXIT_GOOD
185
186	wrong_thread:
187	nop
188	! $!E!V trig_pc_d(1, @VA(.MAIN.wrong_thread)) -> printf("This diag only runs on thread ZERO!")
189
190	test_failed:
191	EXIT_BAD
192
193
194
195
196	/************************************************************************
197	Test case data start
198	************************************************************************/
199	.data
200	user_data_start:
201	.xword 0x0
202	.end
203
204