[OpenSPARC-T2-DV] / verif / diag / assembly / isa3 / isa3_asi_cmp_core_2.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: isa3_asi_cmp_core_2.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
!#include "nmacros.h"
    
#include "hboot.s"

! can set this to 1 to stop test after thread 0 & 1 have 
! parked/unparked all threads.
! #define STOP_AFTER

#define THREAD_COUNT %l1
! a threads unique addr for incrementing a counter.
#define MY_ADDR %l7
! addr that stores which thread is the master thread.    
#define COMN_ADDR %l6
#define COMN_ADDR2 %l5
#define MY_ID %o1
#define MASK_OUT_SELF %l4
! holds user_data_start addr    
#define USER_DATA %o3
! what threads are expected to be active    
#define EXPECT_ACTIVE %o4
#define LAST_THREAD %o5

#define ALL1S  0xffffffffffffffff
        
/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:

 	!# Input registers
    set	0,	%i0
  	set	0,	%i1
  	set	0,	%i2
  	set	0,	%i3
  	set	0,	%i4
  	set	0,	%i5
  	set	0,	%i6
  	set	0,	%i7
	!# Local registers
  	set	0,	%l0
  	set	0,	%l1
  	set	0,	%l2
  	set	0,	%l3
 	set	0,	%l4
 	set	0,	%l5
 	set	0,	%l6
    set	0,	%l7
 	!# Output registers
  	set	0,	%o0
  	set	0,  %o1
  	set	0,	%o2
  	set	0,	%o3
  	set	0,	%o4
  	set	0,  %o5
  	set	0,	%o6
  	set	0,  %o7
    
 	ta	T_CHANGE_HPRIV  ! run in Hpriv mode
 	nop

 	rdth_id ! get thread ID in %o1
	
    ! 9 64 bit memory locations. last is shared, init all to 0.
    ! offset 0 = thread 0 counter area
    ! ...
    ! offset 8 = common area that stores which thread is the master thread.
    
 	!umul	MY_ID,  8, MY_ADDR       ! per thread offset
    sllx    MY_ID, 6, MY_ADDR       ! per thread offset, ID selects bank
 	setx	user_data_start, %g1, USER_DATA ! data area base
 	add 	MY_ADDR,  USER_DATA ,  MY_ADDR   ! per thread address ('my' address)

    add     %g2,    0x40,   COMN_ADDR ! common address
    add     COMN_ADDR, 0x8, COMN_ADDR2  ! common address 2

    ! what threads are expected to be active
    wr      %g0,    0x41,   %asi
    ldxa    [%g0 + ASI_CMP_CORE_ENABLED] %asi,    EXPECT_ACTIVE

    ! what thread will be the last thread
    mov     0,  LAST_THREAD  ! init
    mov     EXPECT_ACTIVE,  %g1 ! thread enabled mask
calc_last_thread:   
    srlx    %g1,    1,  %g1
    cmp     %g1,    %g0
    bne,a   calc_last_thread
    inc     LAST_THREAD

    mov     LAST_THREAD,    THREAD_COUNT
    inc     THREAD_COUNT
    
    ba      thread_x ! all threads do the same
    nop
    
        
	EXIT_BAD

	
!
! Thread Start
!
thread_x:
	
    wr      %g0,    ASI_CMP_CORE,   %asi

    
    ! signal that thread has gotten here (started).
    mov     0xff,   %g2
    stb     %g2,    [COMN_ADDR2 + MY_ID]    

    ! am I the master thread?
    ldx     [COMN_ADDR],  %g2
    cmp     %g2,    MY_ID
    bne     not_master
    nop

    ! master waits for other threads to have started.
master_waiting: 
    ldx     [COMN_ADDR2], %g2
    cmp     %g2,    ALL1S
    bne     master_waiting
    nop
    
    ! yes, skip first loop and control the parking instead
    call    park_control
    nop
    nop
    ! If we were just master, goto pass_control
    ba      pass_control   !call will ret here
    nop

not_master:    
    ! not master, then loop doing visible busy work, 
    ! waiting to become master on return
    call    counter1  ! %o7
    nop
	nop
    
    ! now we are master. next, pass control
    call    park_control
    nop
	nop

pass_control:   
    ! pass control to next thread
    add     MY_ID,  1,  %g2
    stx     %g2,    [COMN_ADDR]
	
    ! now we do second loop,
    ! waiting to exit
    call    counter2  ! %o7
    nop
    nop
    
test_passed:
	EXIT_GOOD

thread_not_parked:
    nop
thread_not_running:
    nop
bad_reg_value:
    nop
test_failed:
    nop
    
    EXIT_BAD


!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!  subroutines
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    
    
! make sure all other threads are spinning counters.
! park all other threads.
! make sure all other threads are NOT spinning counters.
! UN park all other threads.
! make sure all other threads are spinning counters.
! return.
! CHECK FOR ERRORS!
park_control:
    ! save return address, nested calls
    mov     %o7,    %i0

    ! make a mask, the only 0 is for self
    sub     %g0,    1,      %g1
    mov     1,      MASK_OUT_SELF 
    sllx    MASK_OUT_SELF,    MY_ID,  MASK_OUT_SELF
    xor     MASK_OUT_SELF,    %g1,    MASK_OUT_SELF ! the only 0 is for me

    ! make sure all other threads are spinning counters
    call    run_check ! changes %o7
    nop
    nop
        	
return_from_run_check:         
    ! park all other threads except self
    stxa    MASK_OUT_SELF,    [%g0 + ASI_CMP_CORE_RUNNING_W1C] %asi
    ! check reg
    ldxa    [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi,    %l0
    xor     %l0,    ALL1S,    %l0
    cmp     %l0,    MASK_OUT_SELF
    bne     bad_reg_value
    mov     %g0,  %l0
    
  
    ! make sure all other threads are NOT spinning counters
    call    park_check ! changes %o7
    nop
    nop
	
return_from_park_check:     
    ! UN park all other threads
    stxa    MASK_OUT_SELF,    [%g0 + ASI_CMP_CORE_RUNNING_W1S] %asi
    ! checks reg
    ldxa    [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi,    %l0
    cmp     %l0,    EXPECT_ACTIVE
    bne     bad_reg_value
    mov     %g0,  %l0
    
    ! make sure all other threads are spinning counters
    call    run_check ! changes %o7
    nop
    
    ! restore original return address
    mov     %i0,    %o7    
    retl ! to %o7
    nop
! ---

    
! confirm all threads are running/counting. (except for myself)
! loop for each thread.
run_check:
    ! save return address, nested calls
    mov     %o7,    %i1
    mov     LAST_THREAD,      %g4

loop_rc: 
	! skip self
    cmp     MY_ID,  %g4
    beq     next_rc
    nop    

    !umul	%g4,    0x8,  %g5               ! g4=tid, offset
    sllx    %g4, 6, %g5           ! move tid up to bank select position
    
    !read counter location
    ldx     [USER_DATA + %g5],   %g6

    call    delay
    nop
delay_rtn1: 
    !read counter location
    ldx     [USER_DATA + %g5],   %g7
    
    !has it incremented?
    cmp     %g6,    %g7
    beq     thread_not_running
    nop
    
next_rc:   
    deccc   %g4
    bpos    loop_rc
    nop

    ! check ASI_CORE_RUNNING_STATUS, all active
    ldxa    [%g0 + ASI_CMP_CORE_RUNNING_STATUS] %asi,    %g6
    cmp     %g6,    EXPECT_ACTIVE ! what threads are expected to be active
    bne     bad_reg_value
    nop

    ! restore original return address
    mov     %i1,    %o7    
    retl ! to %o7
    nop
! ---

    
! confirm, all threads are parked, except self.
! loop for each thread and insure counter does not inc
park_check:
    ! save return address, nested calls
    mov     %o7,    %i2

    mov     LAST_THREAD,      %g4

loop_pc: 
	! skip self
    cmp     MY_ID,  %g4
    beq     next_pc
    nop    

    !umul	%g4,    0x8,  %g5               ! g4=tid, offset
    sllx    %g4, 6, %g5           ! move tid up to bank select position
    !read counter location
    ldx     [USER_DATA + %g5],   %g6

    call    delay
    nop
delay_rtn2:     
    !read counter location
    ldx     [USER_DATA + %g5],   %g7
    
    !has it incremented?
    cmp     %g6,    %g7
    bne     thread_not_parked
    nop
    
next_pc:   
    deccc   %g4
    bpos    loop_pc
    nop
	
    ! check ASI_CORE_RUNNING_STATUS, all active
    ldxa    [%g0 + ASI_CMP_CORE_RUNNING_STATUS] %asi,    %g6
    xor     MASK_OUT_SELF,    ALL1S,    %g7 ! only self is set
    cmp     %g6,    %g7
    bne     bad_reg_value
    nop

    ! restore original return address
    mov     %i2,    %o7    
    retl ! %o7
    nop
! ---

    
! spin incrementing a mem location.
! look at the master address to see when I become master.
counter1:
    mov     1,      %g1
loop_1: 
    stx     %g1,    [MY_ADDR]
    ldx     [COMN_ADDR],  %g2
    cmp     %g2,    MY_ID ! thread id
    bne,a   loop_1
    inc     %g1
    retl    ! %o7
    nop
! ---


! spin incrementing a mem location.
! look at the master address to see when I need to exit
counter2:
    mov     1,      %g3
loop_2: 
    stx     %g3,    [MY_ADDR]
    ldx     [COMN_ADDR],  %g2
    cmp     %g2,    THREAD_COUNT ! final thread is done
    bne,a   loop_2
    inc     %g3
    retl    ! %o7
    nop
! ---

    
! kill time, do a few divides
delay:
    !do a divide a few times
    ldd     [COMN_ADDR + 0x10],  %f0
    ldd     [COMN_ADDR + 0x18],  %f2
    fdivd   %f0,    %f2,    %f4
    fdivd   %f4,    %f6,    %f0
!     fdivd   %f0,    %f2,    %f4
!     fdivd   %f4,    %f6,    %f0
!     fmuld   %f0,    %f2,    %f4
!     fmuld   %f4,    %f6,    %f0    
!     fdivd   %f0,    %f2,    %f4
!     fdivd   %f4,    %f6,    %f0
!     fdivd   %f0,    %f2,    %f4
!     fdivd   %f4,    %f6,    %f0
!     fmuld   %f0,    %f2,    %f4
!     fmuld   %f4,    %f6,    %f0
!     fmuld   %f0,    %f2,    %f4
!     fmuld   %f4,    %f6,    %f0    
    fdivd   %f0,    %f2,    %f4
    fdivd   %f4,    %f6,    %f0
    fdivd   %f0,    %f2,    %f4
    fdivd   %f4,    %f6,    %f0
    fmuld   %f0,    %f2,    %f4
    fmuld   %f4,    %f6,    %f0    
    fdivd   %f0,    %f2,    %f4
    fdivd   %f4,    %f6,    %f0
    fdivd   %f0,    %f2,    %f4
    fdivd   %f4,    %f6,    %f0
    fmuld   %f0,    %f2,    %f4
!     fmuld   %f4,    %f6,    %f0
!     fmuld   %f0,    %f2,    %f4
!     fmuld   %f4,    %f6,    %f0    
!     fdivd   %f0,    %f2,    %f4
!     fdivd   %f4,    %f6,    %f0
    fdivd   %f0,    %f2,    %f4
      
    retl ! %o7
    nop
! ---


/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
.xword 0x0
.xword 0x0
.xword 0x0	
.xword 0x0
.xword 0x0	
.xword 0x0
.xword 0x0
.xword 0x0
.xword 0x0
.xword 0x5555555555555555
.xword 0xaaaaaaaaaaaaaaaa
.xword 0x5555555555555555
.xword 0xaaaaaaaaaaaaaaaa
.xword 0x5555555555555555
.xword 0xaaaaaaaaaaaaaaaa
.xword 0x5555555555555555
.xword 0xaaaaaaaaaaaaaaaa
.xword 0x5555555555555555
.xword 0xaaaaaaaaaaaaaaaa
.xword 0x5555555555555555
.xword 0xaaaaaaaaaaaaaaaa
.xword 0x5555555555555555
.xword 0xaaaaaaaaaaaaaaaa
.xword 0x5555555555555555
.xword 0xaaaaaaaaaaaaaaaa
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: isa3_asi_cmp_core_2.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40	!#include "nmacros.h"
	41
	42	#include "hboot.s"
	43
	44	! can set this to 1 to stop test after thread 0 & 1 have
	45	! parked/unparked all threads.
	46	! #define STOP_AFTER
	47
	48	#define THREAD_COUNT %l1
	49	! a threads unique addr for incrementing a counter.
	50	#define MY_ADDR %l7
	51	! addr that stores which thread is the master thread.
	52	#define COMN_ADDR %l6
	53	#define COMN_ADDR2 %l5
	54	#define MY_ID %o1
	55	#define MASK_OUT_SELF %l4
	56	! holds user_data_start addr
	57	#define USER_DATA %o3
	58	! what threads are expected to be active
	59	#define EXPECT_ACTIVE %o4
	60	#define LAST_THREAD %o5
	61
	62	#define ALL1S 0xffffffffffffffff
	63
	64	/************************************************************************
65	Test case code start
66	************************************************************************/
67
68	.text
69	.global main
70
71	main:
72
73	!# Input registers
74	set 0, %i0
75	set 0, %i1
76	set 0, %i2
77	set 0, %i3
78	set 0, %i4
79	set 0, %i5
80	set 0, %i6
81	set 0, %i7
82	!# Local registers
83	set 0, %l0
84	set 0, %l1
85	set 0, %l2
86	set 0, %l3
87	set 0, %l4
88	set 0, %l5
89	set 0, %l6
90	set 0, %l7
91	!# Output registers
92	set 0, %o0
93	set 0, %o1
94	set 0, %o2
95	set 0, %o3
96	set 0, %o4
97	set 0, %o5
98	set 0, %o6
99	set 0, %o7
100
101	ta T_CHANGE_HPRIV ! run in Hpriv mode
102	nop
103
104	rdth_id ! get thread ID in %o1
105
106	! 9 64 bit memory locations. last is shared, init all to 0.
107	! offset 0 = thread 0 counter area
108	! ...
109	! offset 8 = common area that stores which thread is the master thread.
110
111	!umul MY_ID, 8, MY_ADDR ! per thread offset
112	sllx MY_ID, 6, MY_ADDR ! per thread offset, ID selects bank
113	setx user_data_start, %g1, USER_DATA ! data area base
114	add MY_ADDR, USER_DATA , MY_ADDR ! per thread address ('my' address)
115
116	add %g2, 0x40, COMN_ADDR ! common address
117	add COMN_ADDR, 0x8, COMN_ADDR2 ! common address 2
118
119	! what threads are expected to be active
120	wr %g0, 0x41, %asi
121	ldxa [%g0 + ASI_CMP_CORE_ENABLED] %asi, EXPECT_ACTIVE
122
123	! what thread will be the last thread
124	mov 0, LAST_THREAD ! init
125	mov EXPECT_ACTIVE, %g1 ! thread enabled mask
126	calc_last_thread:
127	srlx %g1, 1, %g1
128	cmp %g1, %g0
129	bne,a calc_last_thread
130	inc LAST_THREAD
131
132	mov LAST_THREAD, THREAD_COUNT
133	inc THREAD_COUNT
134
135	ba thread_x ! all threads do the same
136	nop
137
138
139	EXIT_BAD
140
141
142
143	!
144	! Thread Start
145	!
146	thread_x:
147
148	wr %g0, ASI_CMP_CORE, %asi
149
150
151	! signal that thread has gotten here (started).
152	mov 0xff, %g2
153	stb %g2, [COMN_ADDR2 + MY_ID]
154
155	! am I the master thread?
156	ldx [COMN_ADDR], %g2
157	cmp %g2, MY_ID
158	bne not_master
159	nop
160
161	! master waits for other threads to have started.
162	master_waiting:
163	ldx [COMN_ADDR2], %g2
164	cmp %g2, ALL1S
165	bne master_waiting
166	nop
167
168	! yes, skip first loop and control the parking instead
169	call park_control
170	nop
171	nop
172	! If we were just master, goto pass_control
173	ba pass_control !call will ret here
174	nop
175
176	not_master:
177	! not master, then loop doing visible busy work,
178	! waiting to become master on return
179	call counter1 ! %o7
180	nop
181	nop
182
183	! now we are master. next, pass control
184	call park_control
185	nop
186	nop
187
188	pass_control:
189	! pass control to next thread
190	add MY_ID, 1, %g2
191	stx %g2, [COMN_ADDR]
192
193	! now we do second loop,
194	! waiting to exit
195	call counter2 ! %o7
196	nop
197	nop
198
199	test_passed:
200	EXIT_GOOD
201
202	thread_not_parked:
203	nop
204	thread_not_running:
205	nop
206	bad_reg_value:
207	nop
208	test_failed:
209	nop
210
211	EXIT_BAD
212
213
214
215
216	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
217	! subroutines
218	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
219
220
221	! make sure all other threads are spinning counters.
222	! park all other threads.
223	! make sure all other threads are NOT spinning counters.
224	! UN park all other threads.
225	! make sure all other threads are spinning counters.
226	! return.
227	! CHECK FOR ERRORS!
228	park_control:
229	! save return address, nested calls
230	mov %o7, %i0
231
232	! make a mask, the only 0 is for self
233	sub %g0, 1, %g1
234	mov 1, MASK_OUT_SELF
235	sllx MASK_OUT_SELF, MY_ID, MASK_OUT_SELF
236	xor MASK_OUT_SELF, %g1, MASK_OUT_SELF ! the only 0 is for me
237
238	! make sure all other threads are spinning counters
239	call run_check ! changes %o7
240	nop
241	nop
242
243	return_from_run_check:
244	! park all other threads except self
245	stxa MASK_OUT_SELF, [%g0 + ASI_CMP_CORE_RUNNING_W1C] %asi
246	! check reg
247	ldxa [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi, %l0
248	xor %l0, ALL1S, %l0
249	cmp %l0, MASK_OUT_SELF
250	bne bad_reg_value
251	mov %g0, %l0
252
253
254	! make sure all other threads are NOT spinning counters
255	call park_check ! changes %o7
256	nop
257	nop
258
259	return_from_park_check:
260	! UN park all other threads
261	stxa MASK_OUT_SELF, [%g0 + ASI_CMP_CORE_RUNNING_W1S] %asi
262	! checks reg
263	ldxa [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi, %l0
264	cmp %l0, EXPECT_ACTIVE
265	bne bad_reg_value
266	mov %g0, %l0
267
268	! make sure all other threads are spinning counters
269	call run_check ! changes %o7
270	nop
271
272	! restore original return address
273	mov %i0, %o7
274	retl ! to %o7
275	nop
276	! ---
277
278
279	! confirm all threads are running/counting. (except for myself)
280	! loop for each thread.
281	run_check:
282	! save return address, nested calls
283	mov %o7, %i1
284	mov LAST_THREAD, %g4
285
286	loop_rc:
287	! skip self
288	cmp MY_ID, %g4
289	beq next_rc
290	nop
291
292	!umul %g4, 0x8, %g5 ! g4=tid, offset
293	sllx %g4, 6, %g5 ! move tid up to bank select position
294
295	!read counter location
296	ldx [USER_DATA + %g5], %g6
297
298	call delay
299	nop
300	delay_rtn1:
301	!read counter location
302	ldx [USER_DATA + %g5], %g7
303
304	!has it incremented?
305	cmp %g6, %g7
306	beq thread_not_running
307	nop
308
309	next_rc:
310	deccc %g4
311	bpos loop_rc
312	nop
313
314	! check ASI_CORE_RUNNING_STATUS, all active
315	ldxa [%g0 + ASI_CMP_CORE_RUNNING_STATUS] %asi, %g6
316	cmp %g6, EXPECT_ACTIVE ! what threads are expected to be active
317	bne bad_reg_value
318	nop
319
320	! restore original return address
321	mov %i1, %o7
322	retl ! to %o7
323	nop
324	! ---
325
326
327	! confirm, all threads are parked, except self.
328	! loop for each thread and insure counter does not inc
329	park_check:
330	! save return address, nested calls
331	mov %o7, %i2
332
333	mov LAST_THREAD, %g4
334
335	loop_pc:
336	! skip self
337	cmp MY_ID, %g4
338	beq next_pc
339	nop
340
341	!umul %g4, 0x8, %g5 ! g4=tid, offset
342	sllx %g4, 6, %g5 ! move tid up to bank select position
343	!read counter location
344	ldx [USER_DATA + %g5], %g6
345
346	call delay
347	nop
348	delay_rtn2:
349	!read counter location
350	ldx [USER_DATA + %g5], %g7
351
352	!has it incremented?
353	cmp %g6, %g7
354	bne thread_not_parked
355	nop
356
357	next_pc:
358	deccc %g4
359	bpos loop_pc
360	nop
361
362	! check ASI_CORE_RUNNING_STATUS, all active
363	ldxa [%g0 + ASI_CMP_CORE_RUNNING_STATUS] %asi, %g6
364	xor MASK_OUT_SELF, ALL1S, %g7 ! only self is set
365	cmp %g6, %g7
366	bne bad_reg_value
367	nop
368
369	! restore original return address
370	mov %i2, %o7
371	retl ! %o7
372	nop
373	! ---
374
375
376
377	! spin incrementing a mem location.
378	! look at the master address to see when I become master.
379	counter1:
380	mov 1, %g1
381	loop_1:
382	stx %g1, [MY_ADDR]
383	ldx [COMN_ADDR], %g2
384	cmp %g2, MY_ID ! thread id
385	bne,a loop_1
386	inc %g1
387	retl ! %o7
388	nop
389	! ---
390
391
392
393	! spin incrementing a mem location.
394	! look at the master address to see when I need to exit
395	counter2:
396	mov 1, %g3
397	loop_2:
398	stx %g3, [MY_ADDR]
399	ldx [COMN_ADDR], %g2
400	cmp %g2, THREAD_COUNT ! final thread is done
401	bne,a loop_2
402	inc %g3
403	retl ! %o7
404	nop
405	! ---
406
407
408
409	! kill time, do a few divides
410	delay:
411	!do a divide a few times
412	ldd [COMN_ADDR + 0x10], %f0
413	ldd [COMN_ADDR + 0x18], %f2
414	fdivd %f0, %f2, %f4
415	fdivd %f4, %f6, %f0
416	! fdivd %f0, %f2, %f4
417	! fdivd %f4, %f6, %f0
418	! fmuld %f0, %f2, %f4
419	! fmuld %f4, %f6, %f0
420	! fdivd %f0, %f2, %f4
421	! fdivd %f4, %f6, %f0
422	! fdivd %f0, %f2, %f4
423	! fdivd %f4, %f6, %f0
424	! fmuld %f0, %f2, %f4
425	! fmuld %f4, %f6, %f0
426	! fmuld %f0, %f2, %f4
427	! fmuld %f4, %f6, %f0
428	fdivd %f0, %f2, %f4
429	fdivd %f4, %f6, %f0
430	fdivd %f0, %f2, %f4
431	fdivd %f4, %f6, %f0
432	fmuld %f0, %f2, %f4
433	fmuld %f4, %f6, %f0
434	fdivd %f0, %f2, %f4
435	fdivd %f4, %f6, %f0
436	fdivd %f0, %f2, %f4
437	fdivd %f4, %f6, %f0
438	fmuld %f0, %f2, %f4
439	! fmuld %f4, %f6, %f0
440	! fmuld %f0, %f2, %f4
441	! fmuld %f4, %f6, %f0
442	! fdivd %f0, %f2, %f4
443	! fdivd %f4, %f6, %f0
444	fdivd %f0, %f2, %f4
445
446	retl ! %o7
447	nop
448	! ---
449
450
451
452
453	/************************************************************************
454	Test case data start
455	************************************************************************/
456	.data
457	user_data_start:
458	.xword 0x0
459	.xword 0x0
460	.xword 0x0
461	.xword 0x0
462	.xword 0x0
463	.xword 0x0
464	.xword 0x0
465	.xword 0x0
466	.xword 0x0
467	.xword 0x5555555555555555
468	.xword 0xaaaaaaaaaaaaaaaa
469	.xword 0x5555555555555555
470	.xword 0xaaaaaaaaaaaaaaaa
471	.xword 0x5555555555555555
472	.xword 0xaaaaaaaaaaaaaaaa
473	.xword 0x5555555555555555
474	.xword 0xaaaaaaaaaaaaaaaa
475	.xword 0x5555555555555555
476	.xword 0xaaaaaaaaaaaaaaaa
477	.xword 0x5555555555555555
478	.xword 0xaaaaaaaaaaaaaaaa
479	.xword 0x5555555555555555
480	.xword 0xaaaaaaaaaaaaaaaa
481	.xword 0x5555555555555555
482	.xword 0xaaaaaaaaaaaaaaaa
483	.end
484