Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / isa3 / isa3_mod_arith_int_1215_0x3d.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: isa3_mod_arith_int_1215_0x3d.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
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31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define MAIN_PAGE_NUCLEUS_ALSO
40
41#define H_HT0_Modular_Arithmetic_Interrupt_0x3d
42#define My_H_HT0_Modular_Arithmetic_Interrupt_0x3d andcc %l1, %l2, %l1 ; \
43 bne,pn %xcc, test_fail1 ; \
44 nop ; \
45 EXIT_GOOD ; \
46test_fail1: EXIT_BAD
47
48#include "hboot.s"
49
50.text
51.global main
52
53main:
54
55 ta T_CHANGE_HPRIV
56
57 !# Write bit 9 of MACTL (causes interrupt upon completion)
58 !# 21:0 == 00 0010 0000 0000 0011 1111
59 !# 20:18 TID == 0
60 !# 17 cause interrupt
61 !# 12:08 modular addition (1001)
62 !# 12:08 load MA mem (0000)
63 !# 07:00 length = 63
64
65 wr %g0, 0x40, %asi
66 setx 0x2003f, %g1, %g3
67 stxa %g3, [%g0 + 0x80] %asi
68
69 !# setup mask to check busy bit
70 or %g0, 0x1, %l2
71 sllx %l2, 16, %l2
72
73 #! Try MA_SYNC operation...
74wait1:
75 ldxa [%g0 + 0xA0] %asi, %l1
76 !# since disrupting interrupting on complete, TPC should point to
77 !# instruction below or a later one. Copy this to the trap handler.
78 andcc %l1, %l2, %l1
79 bne,pn %xcc, test_fail
80 nop
81
82
83 nop
84
85 EXIT_BAD
86
87/*******************************************************
88 * Exit code
89 *******************************************************/
90
91test_fail:
92 ta T_BAD_TRAP
93
94/*******************************************************
95 * Data section
96 *******************************************************/
97
98.data