[OpenSPARC-T2-DV] / verif / diag / assembly / isa3 / isa3_mondo_121503.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: isa3_mondo_121503.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO
! Enable main section to run in PRIV mode
#define MAIN_PAGE_NUCLEUS_ALSO

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!Override trap handler definitions
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

! Trap should set %l6=TT which is verified in main program

#define H_T0_Cpu_Mondo_Trap_0x7c
#define My_T0_Cpu_Mondo_Trap_0x7c \
	rdpr    %tt, %l6; \
    ldxa    [ASI_CPU_MONDO_QUEUE_TAIL] %asi, %g1 ;\
	stxa	%g1, [ASI_CPU_MONDO_QUEUE_HEAD] %asi; \
	nop; \
	retry; \
	nop;

#define H_T0_Dev_Mondo_Trap_0x7d
#define My_T0_Dev_Mondo_Trap_0x7d \
	rdpr    %tt, %l6; \
    ldxa    [ASI_DEVICE_QUEUE_TAIL] %asi, %g1 ;\
	stxa	%g1, [ASI_DEVICE_QUEUE_HEAD] %asi; \
	nop; \
	retry; \
	nop;
	
#define H_T0_Resumable_Error_0x7e
#define My_T0_Resumable_Error_0x7e \
	rdpr    %tt, %l6; \
    ldxa    [ASI_RES_ERROR_QUEUE_TAIL] %asi, %g1 ;\
	stxa	%g1, [ASI_RES_ERROR_QUEUE_HEAD] %asi; \
	nop; \
	retry; \
	nop;
	
! Set PSTATE.IE=1
#define CREGS_PSTATE_IE 1  

#include "hboot.s"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:		/* test begin */

	! local reg usage for this diag
	! %l0 = 0x0 always
	! %l1 = expected trap
	! %l2 = tmp register
	! %l3 = tmp register
	! %l4 = tmp register
	! %l5 = tmp register
	! %l6 = TT value
	! %l7 = tmp register

	ta T_CHANGE_HPRIV    ! Change to HPRIV mode
	
init:	
	! Clear local regs for scratch registers
	nop
	mov    0x0,	%l0
	mov    0x0,	%l1
	mov    0x0,	%l2
	mov    0x0,	%l3
	mov    0x0,	%l4
	mov    0x0,	%l5
	mov    0x0,	%l6
	nop

clr_ie:
	! Disable interrupts
	rdpr	%pstate, %l1 
	wrpr	%l1, 0x2, %pstate  ! Set PSTATE.IE=0

rdwr_asi:
	! Rd/Wr head/tail ASIs
	wr	%g0,	ASI_QUEUE,	%asi
	
	ldxa    [ASI_CPU_MONDO_QUEUE_HEAD]  %asi,  %i0
	ldxa    [ASI_CPU_MONDO_QUEUE_TAIL]  %asi,  %i1
	ldxa    [ASI_DEVICE_QUEUE_HEAD]  %asi,  %i2
	ldxa    [ASI_DEVICE_QUEUE_TAIL]  %asi,  %i3
	ldxa    [ASI_RES_ERROR_QUEUE_HEAD]  %asi,  %i4
	ldxa    [ASI_RES_ERROR_QUEUE_TAIL]  %asi,  %i5
	ldxa    [ASI_NONRES_ERROR_QUEUE_HEAD]  %asi,  %i6
	ldxa    [ASI_NONRES_ERROR_QUEUE_TAIL]  %asi,  %i7

	! Set all bits to 1
	setx	0xffff,	%l7,	%g7
	
	stxa    %g7,  [ASI_CPU_MONDO_QUEUE_HEAD]  %asi
	stxa    %g7,  [ASI_CPU_MONDO_QUEUE_TAIL]  %asi
	stxa    %g7,  [ASI_DEVICE_QUEUE_HEAD]  %asi
	stxa    %g7,  [ASI_DEVICE_QUEUE_TAIL]  %asi
	stxa    %g7,  [ASI_RES_ERROR_QUEUE_HEAD]  %asi
	stxa    %g7,  [ASI_RES_ERROR_QUEUE_TAIL]  %asi
	stxa    %g7,  [ASI_NONRES_ERROR_QUEUE_HEAD]  %asi
	stxa    %g7,  [ASI_NONRES_ERROR_QUEUE_TAIL]  %asi

	ldxa    [ASI_CPU_MONDO_QUEUE_HEAD]  %asi,  %i0
	ldxa    [ASI_CPU_MONDO_QUEUE_TAIL]  %asi,  %i1
	ldxa    [ASI_DEVICE_QUEUE_HEAD]  %asi,  %i2
	ldxa    [ASI_DEVICE_QUEUE_TAIL]  %asi,  %i3
	ldxa    [ASI_RES_ERROR_QUEUE_HEAD]  %asi,  %i4
	ldxa    [ASI_RES_ERROR_QUEUE_TAIL]  %asi,  %i5
	ldxa    [ASI_NONRES_ERROR_QUEUE_HEAD]  %asi,  %i6
	ldxa    [ASI_NONRES_ERROR_QUEUE_TAIL]  %asi,  %i7

	! Clear all bits - before beginning trap testing
	clr	%g7

	stxa    %g7,  [ASI_CPU_MONDO_QUEUE_HEAD]  %asi
	stxa    %g7,  [ASI_CPU_MONDO_QUEUE_TAIL]  %asi
	stxa    %g7,  [ASI_DEVICE_QUEUE_HEAD]  %asi
	stxa    %g7,  [ASI_DEVICE_QUEUE_TAIL]  %asi
	stxa    %g7,  [ASI_RES_ERROR_QUEUE_HEAD]  %asi
	stxa    %g7,  [ASI_RES_ERROR_QUEUE_TAIL]  %asi
	stxa    %g7,  [ASI_NONRES_ERROR_QUEUE_HEAD]  %asi
	stxa    %g7,  [ASI_NONRES_ERROR_QUEUE_TAIL]  %asi

	ldxa    [ASI_CPU_MONDO_QUEUE_HEAD]  %asi,  %i0
	ldxa    [ASI_CPU_MONDO_QUEUE_TAIL]  %asi,  %i1
	ldxa    [ASI_DEVICE_QUEUE_HEAD]  %asi,  %i2
	ldxa    [ASI_DEVICE_QUEUE_TAIL]  %asi,  %i3
	ldxa    [ASI_RES_ERROR_QUEUE_HEAD]  %asi,  %i4
	ldxa    [ASI_RES_ERROR_QUEUE_TAIL]  %asi,  %i5
	ldxa    [ASI_NONRES_ERROR_QUEUE_HEAD]  %asi,  %i6
	ldxa    [ASI_NONRES_ERROR_QUEUE_TAIL]  %asi,  %i7

set_ie:
	! Enable interrupts
	rdpr	%pstate, %l1 
	wrpr	%l1, 0x2, %pstate  ! Set PSTATE.IE=1

!! Test CPU MONDO Trap
	
cpu_mondo:
	ta T_CHANGE_HPRIV    ! Change to HPRIV mode

cpu_mondo_setup:	
	wr	%g0,	ASI_QUEUE,	%asi
	clr	%l6
	! %l1 = expected trap
	mov	0x7c,	%l1

	! Write values to setup trap condition
	ldxa    [ASI_CPU_MONDO_QUEUE_HEAD]  %asi,  %l2
	ldxa    [ASI_CPU_MONDO_QUEUE_TAIL]  %asi,  %l3
	! Trap if HEAD!=TAIL and HPRIV mode
	setx	0xffff,	%l7,	%l4
	stxa	%l4,	[ASI_CPU_MONDO_QUEUE_TAIL]  %asi
	ldxa    [ASI_CPU_MONDO_QUEUE_HEAD]  %asi,  %l4
	ldxa    [ASI_CPU_MONDO_QUEUE_TAIL]  %asi,  %l5

cpu_mondo_gotrap:	
	! Change to Priv and trap should happen immediately
	ta T_CHANGE_NONHPRIV
	ta T_CHANGE_PRIV     ! Change to PRIV mode

cpu_mondo_chk_trap:	
	! Verify that trap was taken, %l6=TT=%l1
	cmp	%l6,	%l1
	bne	failed
	nop

!! Test DEVICE MONDO Trap
	
dev_mondo:
	ta T_CHANGE_HPRIV    ! Change to HPRIV mode

dev_mondo_setup:	
	wr	%g0,	ASI_QUEUE,	%asi
	clr	%l6
	! %l1 = expected trap
	mov	0x7d,	%l1

	! Write values to setup trap condition
	ldxa    [ASI_DEVICE_QUEUE_HEAD]  %asi,  %l2
	ldxa    [ASI_DEVICE_QUEUE_TAIL]  %asi,  %l3
	! Trap if HEAD!=TAIL and HPRIV mode
	setx	0xffff,	%l7,	%l4
	stxa	%l4,	[ASI_DEVICE_QUEUE_TAIL]  %asi
	ldxa    [ASI_DEVICE_QUEUE_HEAD]  %asi,  %l4
	ldxa    [ASI_DEVICE_QUEUE_TAIL]  %asi,  %l5

dev_mondo_gotrap:	
	! Change to Priv and trap should happen immediately
	ta T_CHANGE_NONHPRIV
	ta T_CHANGE_PRIV     ! Change to PRIV mode

dev_mondo_chk_trap:	
	! Verify that trap was taken, %l6=TT=%l1
	cmp	%l6,	%l1
	bne	failed
	nop

!! Test RES ERROR Trap
	
res_err:
	ta T_CHANGE_HPRIV    ! Change to HPRIV mode

res_err_setup:	
	wr	%g0,	ASI_QUEUE,	%asi
	clr	%l6
	! %l1 = expected trap
	mov	0x7e,	%l1

	! Write values to setup trap condition
	ldxa    [ASI_RES_ERROR_QUEUE_HEAD]  %asi,  %l2
	ldxa    [ASI_RES_ERROR_QUEUE_TAIL]  %asi,  %l3
	! Trap if HEAD!=TAIL and HPRIV mode
	setx	0xffff,	%l7,	%l4
	stxa	%l4,	[ASI_RES_ERROR_QUEUE_TAIL]  %asi
	ldxa    [ASI_RES_ERROR_QUEUE_HEAD]  %asi,  %l4
	ldxa    [ASI_RES_ERROR_QUEUE_TAIL]  %asi,  %l5

res_err_gotrap:	
	! Change to Priv and trap should happen immediately
	ta T_CHANGE_NONHPRIV
	ta T_CHANGE_PRIV     ! Change to PRIV mode

res_err_chk_trap:	
	! Verify that trap was taken, %l6=TT=%l1
	cmp	%l6,	%l1
	bne	failed
	nop

passed:
	EXIT_GOOD	/* test finish  */

	
failed:
	EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
.word 0xB52E8698
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: isa3_mondo_121503.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39	! Enable main section to run in PRIV mode
	40	#define MAIN_PAGE_NUCLEUS_ALSO
	41
	42	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	43	!Override trap handler definitions
	44	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	45
	46	! Trap should set %l6=TT which is verified in main program
	47
	48	#define H_T0_Cpu_Mondo_Trap_0x7c
	49	#define My_T0_Cpu_Mondo_Trap_0x7c \
	50	rdpr %tt, %l6; \
	51	ldxa [ASI_CPU_MONDO_QUEUE_TAIL] %asi, %g1 ;\
	52	stxa %g1, [ASI_CPU_MONDO_QUEUE_HEAD] %asi; \
	53	nop; \
	54	retry; \
	55	nop;
	56
	57	#define H_T0_Dev_Mondo_Trap_0x7d
	58	#define My_T0_Dev_Mondo_Trap_0x7d \
	59	rdpr %tt, %l6; \
	60	ldxa [ASI_DEVICE_QUEUE_TAIL] %asi, %g1 ;\
	61	stxa %g1, [ASI_DEVICE_QUEUE_HEAD] %asi; \
	62	nop; \
	63	retry; \
	64	nop;
65
66	#define H_T0_Resumable_Error_0x7e
67	#define My_T0_Resumable_Error_0x7e \
68	rdpr %tt, %l6; \
69	ldxa [ASI_RES_ERROR_QUEUE_TAIL] %asi, %g1 ;\
70	stxa %g1, [ASI_RES_ERROR_QUEUE_HEAD] %asi; \
71	nop; \
72	retry; \
73	nop;
74
75	! Set PSTATE.IE=1
76	#define CREGS_PSTATE_IE 1
77
78	#include "hboot.s"
79
80	/************************************************************************
81	Test case code start
82	************************************************************************/
83
84	.text
85	.global main
86
87	main: /* test begin */
88
89	! local reg usage for this diag
90	! %l0 = 0x0 always
91	! %l1 = expected trap
92	! %l2 = tmp register
93	! %l3 = tmp register
94	! %l4 = tmp register
95	! %l5 = tmp register
96	! %l6 = TT value
97	! %l7 = tmp register
98
99	ta T_CHANGE_HPRIV ! Change to HPRIV mode
100
101	init:
102	! Clear local regs for scratch registers
103	nop
104	mov 0x0, %l0
105	mov 0x0, %l1
106	mov 0x0, %l2
107	mov 0x0, %l3
108	mov 0x0, %l4
109	mov 0x0, %l5
110	mov 0x0, %l6
111	nop
112
113	clr_ie:
114	! Disable interrupts
115	rdpr %pstate, %l1
116	wrpr %l1, 0x2, %pstate ! Set PSTATE.IE=0
117
118	rdwr_asi:
119	! Rd/Wr head/tail ASIs
120	wr %g0, ASI_QUEUE, %asi
121
122	ldxa [ASI_CPU_MONDO_QUEUE_HEAD] %asi, %i0
123	ldxa [ASI_CPU_MONDO_QUEUE_TAIL] %asi, %i1
124	ldxa [ASI_DEVICE_QUEUE_HEAD] %asi, %i2
125	ldxa [ASI_DEVICE_QUEUE_TAIL] %asi, %i3
126	ldxa [ASI_RES_ERROR_QUEUE_HEAD] %asi, %i4
127	ldxa [ASI_RES_ERROR_QUEUE_TAIL] %asi, %i5
128	ldxa [ASI_NONRES_ERROR_QUEUE_HEAD] %asi, %i6
129	ldxa [ASI_NONRES_ERROR_QUEUE_TAIL] %asi, %i7
130
131	! Set all bits to 1
132	setx 0xffff, %l7, %g7
133
134	stxa %g7, [ASI_CPU_MONDO_QUEUE_HEAD] %asi
135	stxa %g7, [ASI_CPU_MONDO_QUEUE_TAIL] %asi
136	stxa %g7, [ASI_DEVICE_QUEUE_HEAD] %asi
137	stxa %g7, [ASI_DEVICE_QUEUE_TAIL] %asi
138	stxa %g7, [ASI_RES_ERROR_QUEUE_HEAD] %asi
139	stxa %g7, [ASI_RES_ERROR_QUEUE_TAIL] %asi
140	stxa %g7, [ASI_NONRES_ERROR_QUEUE_HEAD] %asi
141	stxa %g7, [ASI_NONRES_ERROR_QUEUE_TAIL] %asi
142
143	ldxa [ASI_CPU_MONDO_QUEUE_HEAD] %asi, %i0
144	ldxa [ASI_CPU_MONDO_QUEUE_TAIL] %asi, %i1
145	ldxa [ASI_DEVICE_QUEUE_HEAD] %asi, %i2
146	ldxa [ASI_DEVICE_QUEUE_TAIL] %asi, %i3
147	ldxa [ASI_RES_ERROR_QUEUE_HEAD] %asi, %i4
148	ldxa [ASI_RES_ERROR_QUEUE_TAIL] %asi, %i5
149	ldxa [ASI_NONRES_ERROR_QUEUE_HEAD] %asi, %i6
150	ldxa [ASI_NONRES_ERROR_QUEUE_TAIL] %asi, %i7
151
152	! Clear all bits - before beginning trap testing
153	clr %g7
154
155	stxa %g7, [ASI_CPU_MONDO_QUEUE_HEAD] %asi
156	stxa %g7, [ASI_CPU_MONDO_QUEUE_TAIL] %asi
157	stxa %g7, [ASI_DEVICE_QUEUE_HEAD] %asi
158	stxa %g7, [ASI_DEVICE_QUEUE_TAIL] %asi
159	stxa %g7, [ASI_RES_ERROR_QUEUE_HEAD] %asi
160	stxa %g7, [ASI_RES_ERROR_QUEUE_TAIL] %asi
161	stxa %g7, [ASI_NONRES_ERROR_QUEUE_HEAD] %asi
162	stxa %g7, [ASI_NONRES_ERROR_QUEUE_TAIL] %asi
163
164	ldxa [ASI_CPU_MONDO_QUEUE_HEAD] %asi, %i0
165	ldxa [ASI_CPU_MONDO_QUEUE_TAIL] %asi, %i1
166	ldxa [ASI_DEVICE_QUEUE_HEAD] %asi, %i2
167	ldxa [ASI_DEVICE_QUEUE_TAIL] %asi, %i3
168	ldxa [ASI_RES_ERROR_QUEUE_HEAD] %asi, %i4
169	ldxa [ASI_RES_ERROR_QUEUE_TAIL] %asi, %i5
170	ldxa [ASI_NONRES_ERROR_QUEUE_HEAD] %asi, %i6
171	ldxa [ASI_NONRES_ERROR_QUEUE_TAIL] %asi, %i7
172
173	set_ie:
174	! Enable interrupts
175	rdpr %pstate, %l1
176	wrpr %l1, 0x2, %pstate ! Set PSTATE.IE=1
177
178	!! Test CPU MONDO Trap
179
180	cpu_mondo:
181	ta T_CHANGE_HPRIV ! Change to HPRIV mode
182
183	cpu_mondo_setup:
184	wr %g0, ASI_QUEUE, %asi
185	clr %l6
186	! %l1 = expected trap
187	mov 0x7c, %l1
188
189	! Write values to setup trap condition
190	ldxa [ASI_CPU_MONDO_QUEUE_HEAD] %asi, %l2
191	ldxa [ASI_CPU_MONDO_QUEUE_TAIL] %asi, %l3
192	! Trap if HEAD!=TAIL and HPRIV mode
193	setx 0xffff, %l7, %l4
194	stxa %l4, [ASI_CPU_MONDO_QUEUE_TAIL] %asi
195	ldxa [ASI_CPU_MONDO_QUEUE_HEAD] %asi, %l4
196	ldxa [ASI_CPU_MONDO_QUEUE_TAIL] %asi, %l5
197
198	cpu_mondo_gotrap:
199	! Change to Priv and trap should happen immediately
200	ta T_CHANGE_NONHPRIV
201	ta T_CHANGE_PRIV ! Change to PRIV mode
202
203	cpu_mondo_chk_trap:
204	! Verify that trap was taken, %l6=TT=%l1
205	cmp %l6, %l1
206	bne failed
207	nop
208
209	!! Test DEVICE MONDO Trap
210
211	dev_mondo:
212	ta T_CHANGE_HPRIV ! Change to HPRIV mode
213
214	dev_mondo_setup:
215	wr %g0, ASI_QUEUE, %asi
216	clr %l6
217	! %l1 = expected trap
218	mov 0x7d, %l1
219
220	! Write values to setup trap condition
221	ldxa [ASI_DEVICE_QUEUE_HEAD] %asi, %l2
222	ldxa [ASI_DEVICE_QUEUE_TAIL] %asi, %l3
223	! Trap if HEAD!=TAIL and HPRIV mode
224	setx 0xffff, %l7, %l4
225	stxa %l4, [ASI_DEVICE_QUEUE_TAIL] %asi
226	ldxa [ASI_DEVICE_QUEUE_HEAD] %asi, %l4
227	ldxa [ASI_DEVICE_QUEUE_TAIL] %asi, %l5
228
229	dev_mondo_gotrap:
230	! Change to Priv and trap should happen immediately
231	ta T_CHANGE_NONHPRIV
232	ta T_CHANGE_PRIV ! Change to PRIV mode
233
234	dev_mondo_chk_trap:
235	! Verify that trap was taken, %l6=TT=%l1
236	cmp %l6, %l1
237	bne failed
238	nop
239
240	!! Test RES ERROR Trap
241
242	res_err:
243	ta T_CHANGE_HPRIV ! Change to HPRIV mode
244
245	res_err_setup:
246	wr %g0, ASI_QUEUE, %asi
247	clr %l6
248	! %l1 = expected trap
249	mov 0x7e, %l1
250
251	! Write values to setup trap condition
252	ldxa [ASI_RES_ERROR_QUEUE_HEAD] %asi, %l2
253	ldxa [ASI_RES_ERROR_QUEUE_TAIL] %asi, %l3
254	! Trap if HEAD!=TAIL and HPRIV mode
255	setx 0xffff, %l7, %l4
256	stxa %l4, [ASI_RES_ERROR_QUEUE_TAIL] %asi
257	ldxa [ASI_RES_ERROR_QUEUE_HEAD] %asi, %l4
258	ldxa [ASI_RES_ERROR_QUEUE_TAIL] %asi, %l5
259
260	res_err_gotrap:
261	! Change to Priv and trap should happen immediately
262	ta T_CHANGE_NONHPRIV
263	ta T_CHANGE_PRIV ! Change to PRIV mode
264
265	res_err_chk_trap:
266	! Verify that trap was taken, %l6=TT=%l1
267	cmp %l6, %l1
268	bne failed
269	nop
270
271	passed:
272	EXIT_GOOD /* test finish */
273
274
275	failed:
276	EXIT_BAD
277
278
279
280
281	/************************************************************************
282	Test case data start
283	************************************************************************/
284	.data
285	user_data_start:
286	.word 0xB52E8698
287	.end
288