Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / diag / assembly / isa3 / isa3_pmu_imiss_idle.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: isa3_pmu_imiss_idle.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
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* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
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* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#include "hboot.s"
/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:		/* test begin */

!
! Thread 0 Start
!
!main_t0:
	!# Initialize registers ..

	!# Global registers
	!# Input registers
	!# Local registers
	set	0x1808C042,	%l0 ! count I-Cache Misses
	set	0x1810C082,	%l1 ! count D-Cache Misses
	set	0x1820C102,	%l2 ! count ITLB Misses
	set     0x1840C202,	%l3 ! count DTLB Misses
	set     0x1880C402,	%l4 ! count L2 cache instruction misses
	set     0x1900C802,	%l5 ! count L2 cache load misses
	set     0x00000002,	%l6 ! count idle
	!# Output registers
	!# Float registers
	!# Other state

	!# Execute Main Diag ..
	ta T_CHANGE_PRIV            ! Should cause Watchdog_reset trap
	
	rd 	%pic, %g2	! load the current pic value into %g2
	wr 	%g0, %g0, %pic 	! zero out the counter	


        ! before sending branches, update the PCR to be in UT.?
	rd 	%pcr, %g3 	! load the current pcr value into %g3

cnt_ICmiss:
	wr	%l2, %g0, %pcr 	! count icache misses

        addcc	%g0, 0x0000, %g2
	setx	load_1, %g2, %g3
	ld	[%g3 + 0x0], %g2
	ld	[%g3 + 0x10], %g6
	ld	[%g3 + 0x0], %g1	!should not be counted as a imiss
	inc	%g5
	inc	%g5
	rd	%pic, %g2	!check pic value

cnt_idle:
	wr	%l6, %g0, %pcr 	! count idle cycles
	ld	[%g3 + 0x10], %g2 ! 32 cycles waiting on this one... look for >1	
		
cnt_DTmiss:
	wr	%l2, %g0, %pcr 	! count dtlb misses ... not included yet
	setx	load_2, %i0, %g4
	ldx	[%g4], %g3
	!inc	%g5	!not counting this yet ...

stop_cnt:
	wr	%g0, %g0, %pcr	!stop counting

	inc	%g5		!look for at least one idle cycle
	!add	%g5, 0x20, %g5
	rd	%pic, %g2	!check pic value
	cmp	%g2, %g5
	ble,pn	%icc, fail

	nop

done:
	EXIT_GOOD	/* test finish  */
fail:
	EXIT_BAD	/* bad count */

/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
scratch_area:
.align 16	
load_1:	
.word 0xFFFF2e2d       
.word 0x2e2dFFFF
.align 16

load_2:
.xword 0xABCDEF0123456789
store_1:
.align 16
.word 0xDEADBEEF			
.word 0xAAAAAAAA		
.align 16	

.end