[OpenSPARC-T2-DV] / verif / diag / assembly / isa3 / isa3_pmu_sl6.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: isa3_pmu_sl6.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO
#include "hboot.s"

#define MA_TIMEOUT 0x100

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:		/* test begin */

        !# Switch to hpriv mode
	ta T_CHANGE_HPRIV

	!# Check to make sure pic is zero
        rd	%pic,	%g4
        cmp	%g0,	%g4
        bne,pn	%icc,	fail

	!# Clear event counter
        clr	%g6

	!# Setup PCR Register to monitor DES operations
        set	0x00018048, %g2
        wr	%g2, %g0, %pcr

	!# Execute Main Diag ..
	!# setup ASI register to point to SPU
        wr %g0, 0x40, %asi
	
	!# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
	and %l1, 0xf, %l2
	cmp %g0, %l2
	bne,pn %xcc, fail
	nop 
	
	!# allocate control word queue (e.g., setup head/tail/first/last registers)
	setx CWQ_BASE, %g1, %l6
		
	!# write base addr to first, head, and tail ptr
	!# first store to first
	stxa	%l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
	!# Mask off upper 16 bits
	setx 0x0000ffffffffffff, %l5, %l0
	and %l0, %l6, %l2
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop

	!# then to head
	stxa	%l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop
	
	!# then to tail
	stxa	%l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop
	
	!# then end of CWQ region to LAST
	setx CWQ_LAST, %g1, %l5
	stxa	%l5, [%g0 + ASI_SPU_CWQ_LAST] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_LAST] %asi, %l1

	!# Mask off upper 16 bits
	and	%l0, %l5, %l2
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop
	
	!# Build the first control word, for the first DES vector.
	!# First build up word 0
	!# For DES, set op = 64, Enc=1, SOB=EOB=1, SFAS=0, Int=CoreID=0, AuthType=0, EncType=09, status=0, Len=24
	setx 0x40E0000009000017, %l1, %l2
	!# %l6 points to CWQ_BASE
	!# Note:	All CWQ entry addresses must be physical!
	stx	%l2, [%l6 + 0x0]
	
	!# Write source address to next CW field
	setx cleartext_1, %g1, %l2
	stx	%l2, [%l6+0x8]

	!# Write 0's to the next 3 CW fields as they are not used
	stx	%g0, [%l6+0x10]
	stx	%g0, [%l6+0x18]
	stx	%g0, [%l6+0x20]

	!# Write address of Encryption key (e.g., initial RC4 state) to next CW field
	setx des_key, %g1, %o2
	stx	%o2, [%l6 + 0x28] 

	!# Encryption IV is not used for RC4
	setx des_iv, %g1, %o2
	stx	%o2, [%l6+0x30]

	!# Finally write destination address to last CW field
	setx result_1, %g1, %o3
	stx	%o3, [%l6 + 0x38] 

	!# Make sure all these stores get to memory before we start
	membar #Sync

	!# Now add 1 (actually 8*8B) to tail pointer 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
	add	%l2, 0x40, %l2
	stxa	%l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
	cmp	%l1, %l2
	bne,pn %xcc,	fail
	nop
	
	!# Kick off the CWQ operation by writing to the CWQ_CSR
	!# Set the enabled bit and reset the other bits 
	or	%g0, 0x1, %g1
	stxa	%g1,	[%g0 + ASI_SPU_CWQ_CSR] %asi

        !# increment event counter
        inc	%g6

	!# set maximum wait loop count, setup mask for busy bit
	!# This timeout may need adjustment
	setx MA_TIMEOUT, %o3, %l3
	!# mask out the busy bit
	or	%g0, 0x4, %l2


    ! give SPU time to start before reading ASI_SPU_CWQ_CSR
    setx user_data_start, %g1, %g2
    mov 10, %g1
loop_for_awhile:
    ldx [%g2], %g3
    bnz loop_for_awhile
    dec %g1

    
wait1:	!# loop on busy to fall through when done or loop count exceeded
	ldxa	[%g0 + ASI_SPU_CWQ_CSR] %asi,	%l1
	andcc	%l1, %l2, %l1
	be	idle1
	addcc	%l3, -1, %l3
	bgt	wait1
	nop
	ba	fail
	nop

idle1:
	!# check the results...first check the data
       	!# The first RC4 is only 8B long (divide by 8 anyway)	
	or %g0, 0x1, %i0
	!# set %l5 to be base address of result area, and
	!# %l6 to be base address of known ciphertext area
	setx	result_1, %g1, %l5
	setx	ciphertext_1, %g1, %l6
	or	%g0, %g0, %g3
		
more1:
	ldx	[%l5 + %g3], %l1
	ldx	[%l6 + %g3], %l2
	cmp	%l1, %l2
	bne,pn	%xcc, fail
	add	%l3, 0x8, %l3	!# i++
	addcc	%i0, -1, %i0
	bgt	more1
	nop

        
	!# Check the PIC
        rd	%pic,	%g4
	cmp     %g4,	%g6
        bne,pn	%icc, fail
	nop

	!# Temporarily ignore the RC4 final state until we get the stream-out working
	EXIT_GOOD
			
	!# Now check the RC4 final state
	!# check 32+1 doublewords
			
	setx	des_key, %g1, %l5
	setx	aes_expected_1, %g1, %l6
	or	%g0, %g0, %g3
	or	%g0, 0x21, %i0
		
more2:
	ldx	[%l5 + %g3], %l1
	ldx	[%l6 + %g3], %l2
	cmp	%l1, %l2
	bne,pn	%icc, fail
	add	%l3, 0x8, %l3	!# i++
	addcc	%i0, -1, %i0
	bgt	more2
	nop
		
	EXIT_GOOD


fail:
	EXIT_BAD

	
/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
scratch_area:

!# Subtest 1 start
!# input data
cleartext_1:		
.xword 0x4e6f772069732074
.xword 0x68652074696d6520
.xword 0x666f7220616c6c20
	
!# DES key (also where final state will be written)
.align 16
des_key:		
.xword 0x0123456789abcdef
.xword 0x08090a0b0c0d0e0f

des_iv:
.xword 0x1234567890abcdef

!# expected ciphertext
ciphertext_1:	
.xword 0xe5c7cdde872bf27c
.xword 0x43e934008c389c0f
.xword 0x683788499a7c05f6

!# should also check final rc4 state, skip for now

!# temporary area for storing expected result
result_1:	

.xword 0xDEADBEEFDEADBEEF			

!# Final RC4 state matrix:
aes_expected_1:	
.xword 0x0109ae9663c2d647 
.xword 0x4510e8d16626f9e7 
.xword 0xc9357b0e554a2a4f 
.xword 0xe1944822d2214360 
.xword 0x231514eb686d3382 
.xword 0xf1770cf8ad9380cf 
.xword 0xc5568c92e39f40ce 
.xword 0x38b899c85a5c507d 
.xword 0x13744ca673dd590b 
.xword 0x1c5241c79c19afed 
.xword 0xef8127d5e054d3e4 
.xword 0x079dfcfe91208bf7 
.xword 0x6e0308db6162fbb2 
.xword 0xba9b72391e4670be 
.xword 0xca2517cc1f2d31b6 
.xword 0x28b31d7f3ff5448a 
.xword 0x0d84bdfdb4008f58 
.xword 0x025fcdbfac2e6f36 
.xword 0xa8346c8553c4713a 
.xword 0x05954ea57e30b19e 
.xword 0x865ea46b2cd0cbb5 
.xword 0x5d1ae95b8d659a11 
.xword 0x78c07ad40683b0e2 
.xword 0xe575374b49dcdf8e 
.xword 0x1669291876aa67ea 
.xword 0xa924a3d9982f3bd8 
.xword 0x7912ee1bb9f4e6f6 
.xword 0x3ebcbb3ca088de57 
.xword 0x3d87c104dac6970a 
.xword 0x2b514dd7b77cf3ff 
.xword 0xf0f2abfa6490ecc3 
.xword 0x89a232a142a70f6a 

!# Final expected X, Y values
.xword 0x000000000000085e
	
!# CWQ data area, set aside 512 CW's worth
!# 512*8*8 = 32KB
.align 32*1024
CWQ_BASE:		
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.align 32*1024
CWQ_LAST:	
					
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: isa3_pmu_sl6.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39	#include "hboot.s"
	40
	41	#define MA_TIMEOUT 0x100
	42
	43	/************************************************************************
	44	Test case code start
	45	************************************************************************/
	46
	47	.text
	48	.global main
	49
	50	main: /* test begin */
	51
	52	!# Switch to hpriv mode
	53	ta T_CHANGE_HPRIV
	54
	55	!# Check to make sure pic is zero
	56	rd %pic, %g4
	57	cmp %g0, %g4
	58	bne,pn %icc, fail
	59
	60	!# Clear event counter
	61	clr %g6
	62
	63	!# Setup PCR Register to monitor DES operations
	64	set 0x00018048, %g2
65	wr %g2, %g0, %pcr
66
67	!# Execute Main Diag ..
68	!# setup ASI register to point to SPU
69	wr %g0, 0x40, %asi
70
71	!# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
72	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
73	and %l1, 0xf, %l2
74	cmp %g0, %l2
75	bne,pn %xcc, fail
76	nop
77
78	!# allocate control word queue (e.g., setup head/tail/first/last registers)
79	setx CWQ_BASE, %g1, %l6
80
81	!# write base addr to first, head, and tail ptr
82	!# first store to first
83	stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
84	ldxa [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
85	!# Mask off upper 16 bits
86	setx 0x0000ffffffffffff, %l5, %l0
87	and %l0, %l6, %l2
88	cmp %l1, %l2
89	bne,pn %xcc, fail
90	nop
91
92	!# then to head
93	stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
94	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
95	cmp %l1, %l2
96	bne,pn %xcc, fail
97	nop
98
99	!# then to tail
100	stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
101	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
102	cmp %l1, %l2
103	bne,pn %xcc, fail
104	nop
105
106	!# then end of CWQ region to LAST
107	setx CWQ_LAST, %g1, %l5
108	stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
109	ldxa [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
110
111	!# Mask off upper 16 bits
112	and %l0, %l5, %l2
113	cmp %l1, %l2
114	bne,pn %xcc, fail
115	nop
116
117	!# Build the first control word, for the first DES vector.
118	!# First build up word 0
119	!# For DES, set op = 64, Enc=1, SOB=EOB=1, SFAS=0, Int=CoreID=0, AuthType=0, EncType=09, status=0, Len=24
120	setx 0x40E0000009000017, %l1, %l2
121	!# %l6 points to CWQ_BASE
122	!# Note: All CWQ entry addresses must be physical!
123	stx %l2, [%l6 + 0x0]
124
125	!# Write source address to next CW field
126	setx cleartext_1, %g1, %l2
127	stx %l2, [%l6+0x8]
128
129	!# Write 0's to the next 3 CW fields as they are not used
130	stx %g0, [%l6+0x10]
131	stx %g0, [%l6+0x18]
132	stx %g0, [%l6+0x20]
133
134	!# Write address of Encryption key (e.g., initial RC4 state) to next CW field
135	setx des_key, %g1, %o2
136	stx %o2, [%l6 + 0x28]
137
138	!# Encryption IV is not used for RC4
139	setx des_iv, %g1, %o2
140	stx %o2, [%l6+0x30]
141
142	!# Finally write destination address to last CW field
143	setx result_1, %g1, %o3
144	stx %o3, [%l6 + 0x38]
145
146	!# Make sure all these stores get to memory before we start
147	membar #Sync
148
149	!# Now add 1 (actually 8*8B) to tail pointer
150	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
151	add %l2, 0x40, %l2
152	stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
153	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
154	cmp %l1, %l2
155	bne,pn %xcc, fail
156	nop
157
158	!# Kick off the CWQ operation by writing to the CWQ_CSR
159	!# Set the enabled bit and reset the other bits
160	or %g0, 0x1, %g1
161	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
162
163	!# increment event counter
164	inc %g6
165
166	!# set maximum wait loop count, setup mask for busy bit
167	!# This timeout may need adjustment
168	setx MA_TIMEOUT, %o3, %l3
169	!# mask out the busy bit
170	or %g0, 0x4, %l2
171
172
173	! give SPU time to start before reading ASI_SPU_CWQ_CSR
174	setx user_data_start, %g1, %g2
175	mov 10, %g1
176	loop_for_awhile:
177	ldx [%g2], %g3
178	bnz loop_for_awhile
179	dec %g1
180
181
182	wait1: !# loop on busy to fall through when done or loop count exceeded
183	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
184	andcc %l1, %l2, %l1
185	be idle1
186	addcc %l3, -1, %l3
187	bgt wait1
188	nop
189	ba fail
190	nop
191
192	idle1:
193	!# check the results...first check the data
194	!# The first RC4 is only 8B long (divide by 8 anyway)
195	or %g0, 0x1, %i0
196	!# set %l5 to be base address of result area, and
197	!# %l6 to be base address of known ciphertext area
198	setx result_1, %g1, %l5
199	setx ciphertext_1, %g1, %l6
200	or %g0, %g0, %g3
201
202	more1:
203	ldx [%l5 + %g3], %l1
204	ldx [%l6 + %g3], %l2
205	cmp %l1, %l2
206	bne,pn %xcc, fail
207	add %l3, 0x8, %l3 !# i++
208	addcc %i0, -1, %i0
209	bgt more1
210	nop
211
212
213	!# Check the PIC
214	rd %pic, %g4
215	cmp %g4, %g6
216	bne,pn %icc, fail
217	nop
218
219	!# Temporarily ignore the RC4 final state until we get the stream-out working
220	EXIT_GOOD
221
222	!# Now check the RC4 final state
223	!# check 32+1 doublewords
224
225	setx des_key, %g1, %l5
226	setx aes_expected_1, %g1, %l6
227	or %g0, %g0, %g3
228	or %g0, 0x21, %i0
229
230	more2:
231	ldx [%l5 + %g3], %l1
232	ldx [%l6 + %g3], %l2
233	cmp %l1, %l2
234	bne,pn %icc, fail
235	add %l3, 0x8, %l3 !# i++
236	addcc %i0, -1, %i0
237	bgt more2
238	nop
239
240	EXIT_GOOD
241
242
243	fail:
244	EXIT_BAD
245
246
247	/************************************************************************
248	Test case data start
249	************************************************************************/
250	.data
251	user_data_start:
252	scratch_area:
253
254	!# Subtest 1 start
255	!# input data
256	cleartext_1:
257	.xword 0x4e6f772069732074
258	.xword 0x68652074696d6520
259	.xword 0x666f7220616c6c20
260
261	!# DES key (also where final state will be written)
262	.align 16
263	des_key:
264	.xword 0x0123456789abcdef
265	.xword 0x08090a0b0c0d0e0f
266
267	des_iv:
268	.xword 0x1234567890abcdef
269
270	!# expected ciphertext
271	ciphertext_1:
272	.xword 0xe5c7cdde872bf27c
273	.xword 0x43e934008c389c0f
274	.xword 0x683788499a7c05f6
275
276	!# should also check final rc4 state, skip for now
277
278	!# temporary area for storing expected result
279	result_1:
280
281	.xword 0xDEADBEEFDEADBEEF
282
283	!# Final RC4 state matrix:
284	aes_expected_1:
285	.xword 0x0109ae9663c2d647
286	.xword 0x4510e8d16626f9e7
287	.xword 0xc9357b0e554a2a4f
288	.xword 0xe1944822d2214360
289	.xword 0x231514eb686d3382
290	.xword 0xf1770cf8ad9380cf
291	.xword 0xc5568c92e39f40ce
292	.xword 0x38b899c85a5c507d
293	.xword 0x13744ca673dd590b
294	.xword 0x1c5241c79c19afed
295	.xword 0xef8127d5e054d3e4
296	.xword 0x079dfcfe91208bf7
297	.xword 0x6e0308db6162fbb2
298	.xword 0xba9b72391e4670be
299	.xword 0xca2517cc1f2d31b6
300	.xword 0x28b31d7f3ff5448a
301	.xword 0x0d84bdfdb4008f58
302	.xword 0x025fcdbfac2e6f36
303	.xword 0xa8346c8553c4713a
304	.xword 0x05954ea57e30b19e
305	.xword 0x865ea46b2cd0cbb5
306	.xword 0x5d1ae95b8d659a11
307	.xword 0x78c07ad40683b0e2
308	.xword 0xe575374b49dcdf8e
309	.xword 0x1669291876aa67ea
310	.xword 0xa924a3d9982f3bd8
311	.xword 0x7912ee1bb9f4e6f6
312	.xword 0x3ebcbb3ca088de57
313	.xword 0x3d87c104dac6970a
314	.xword 0x2b514dd7b77cf3ff
315	.xword 0xf0f2abfa6490ecc3
316	.xword 0x89a232a142a70f6a
317
318	!# Final expected X, Y values
319	.xword 0x000000000000085e
320
321	!# CWQ data area, set aside 512 CW's worth
322	!# 51288 = 32KB
323	.align 32*1024
324	CWQ_BASE:
325	.xword 0xAAAAAAAAAAAAAAA
326	.xword 0xAAAAAAAAAAAAAAA
327	.xword 0xAAAAAAAAAAAAAAA
328	.xword 0xAAAAAAAAAAAAAAA
329	.xword 0xAAAAAAAAAAAAAAA
330	.xword 0xAAAAAAAAAAAAAAA
331	.xword 0xAAAAAAAAAAAAAAA
332	.xword 0xAAAAAAAAAAAAAAA
333	.align 32*1024
334	CWQ_LAST:
335
336	.end