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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / niu / NIU_Tx_Rx / FcNiuBasicTxRx_MULTI_FFFF_DMA_FF_DMA.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: FcNiuBasicTxRx_MULTI_FFFF_DMA_FF_DMA.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40#include "hboot.s"
41#include "niu_defines.h"
42#define TX_FAIR_PKT_CNT (NIU_TX_PKT_CNT / 2)
43#define FAIR_PKT_COUNT ((RXMAC_PKTCNT) - (RXMAC_PKTCNT%8))
44
45/************************************************************************
46 Test case code start
47 ************************************************************************/
48.text
49.global main
50
51main:
52 ta T_CHANGE_HPRIV
53 nop
54
55 mov 0x1, %g4
56
57 ta T_RD_THID
58 nop
59 cmp %g4, %o1 ! Check if its thread1
60 be thread_1 !
61 nop
62 brz %o1, thread_Tx ! Execute thread_0
63 nop
64 cmp %g4, %o1 ! Send the remaining threads to good-end, if any.
65 bne RX_test_passed !
66 nop
67
68!
69! Thread 0 Start
70!
71!
72thread_Tx:
73!#include "niu_init.h"
74!thread_0:
75 nop
76 wr %g0, ASI_CMP_CORE, %asi
77 mov 0x2, %g4
78 stxa %g4, [ASI_CMP_CORE_RUNNING_W1S]%asi ! Start Thread_1
79 nop
80
81Init_flow:
82 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS, NIU_TX_PKT_LEN_P0, NIU_TX_MULTI_PORT, NIU_TX_PKT_LEN_P1)
83
84P_TxDMAActivate:
85 setx MAC_ID, %g1, %o0 ! 1st Parameter
86 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
87 setx NIU_TX_MULTI_PORT, %g1, %o2
88 setx NIU_TX_MULTI_DMA_P0, %g1, %o3
89 setx NIU_TX_MULTI_DMA_P1, %g1, %o4
90 call SetTxDMAActive
91 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
92
93P_AddTxChannels :
94 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
95 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
96 nop
97
98P_SetTxMaxBurst :
99 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
100 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
101 setx NIU_TX_MULTI_PORT, %g1, %o2
102 setx NIU_TX_MULTI_DMA_P0, %g1, %o3
103 setx NIU_TX_MULTI_DMA_P1, %g1, %o4
104 call SetTxMaxBurst
105 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
106 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
107 nop
108
109 nop
110 setx NIU_TX_MULTI_PORT, %g1, %o2
111 setx NIU_TX_MULTI_DMA_P0, %g1, %o3
112 setx NIU_TX_MULTI_DMA_P1, %g1, %o4
113 call InitTxDma
114 nop
115 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
116 nop
117
118Gen_Packet:
119 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
120 nop
121
122 setx 0x50, %g1, %g4
123delay_loop_tmp:
124 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
125 nop
126 nop
127 nop
128 nop
129 dec %g4
130 brnz %g4, delay_loop_tmp
131 nop
132
133SetTxRingKick_0:
134 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_0)) -> NIU_SetTxRingKick(0, 0, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
135 setx 0x0, %g1, %o0
136 ldx [%g2] , %g3
137 nop
138 mulx %o0, 0x200, %g5
139 setx TX_RING_KICK_Addr, %g1, %g2
140 add %g2, %g5, %g2
141 setx 0x40, %g1, %g3
142 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
143 nop
144
145SetTxCs_0 :
146 setx 0x0, %g1, %o0
147 setx TX_CS_Data, %g1, %g3
148 mulx %o0, 0x200, %g5
149 setx TX_CS_Addr, %g1, %g2
150 add %g2, %g5, %g2
151 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
152 nop
153
154SetTxRingKick_1:
155 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_1)) -> NIU_SetTxRingKick(0, 1, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
156 setx 0x1, %g1, %o0
157 ldx [%g2] , %g3
158 nop
159 mulx %o0, 0x200, %g5
160 setx TX_RING_KICK_Addr, %g1, %g2
161 add %g2, %g5, %g2
162 setx 0x40, %g1, %g3
163 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
164 nop
165
166SetTxCs_1 :
167 setx 0x1, %g1, %o0
168 setx TX_CS_Data, %g1, %g3
169 mulx %o0, 0x200, %g5
170 setx TX_CS_Addr, %g1, %g2
171 add %g2, %g5, %g2
172 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
173 nop
174
175SetTxRingKick_2:
176 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_2)) -> NIU_SetTxRingKick(0, 2, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
177 setx 0x2, %g1, %o0
178 ldx [%g2] , %g3
179 nop
180 mulx %o0, 0x200, %g5
181 setx TX_RING_KICK_Addr, %g1, %g2
182 add %g2, %g5, %g2
183 setx 0x40, %g1, %g3
184 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
185 nop
186
187SetTxCs_2 :
188 setx 0x2, %g1, %o0
189 setx TX_CS_Data, %g1, %g3
190 mulx %o0, 0x200, %g5
191 setx TX_CS_Addr, %g1, %g2
192 add %g2, %g5, %g2
193 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
194 nop
195
196SetTxRingKick_3:
197 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_3)) -> NIU_SetTxRingKick(0, 3, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
198 setx 0x3, %g1, %o0
199 ldx [%g2] , %g3
200 nop
201 mulx %o0, 0x200, %g5
202 setx TX_RING_KICK_Addr, %g1, %g2
203 add %g2, %g5, %g2
204 setx 0x40, %g1, %g3
205 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
206 nop
207
208SetTxCs_3 :
209 setx 0x3, %g1, %o0
210 setx TX_CS_Data, %g1, %g3
211 mulx %o0, 0x200, %g5
212 setx TX_CS_Addr, %g1, %g2
213 add %g2, %g5, %g2
214 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
215 nop
216
217SetTxRingKick_4:
218 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_4)) -> NIU_SetTxRingKick(0, 4, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
219 setx 0x4, %g1, %o0
220 ldx [%g2] , %g3
221 nop
222 mulx %o0, 0x200, %g5
223 setx TX_RING_KICK_Addr, %g1, %g2
224 add %g2, %g5, %g2
225 setx 0x40, %g1, %g3
226 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
227 nop
228
229SetTxCs_4 :
230 setx 0x4, %g1, %o0
231 setx TX_CS_Data, %g1, %g3
232 mulx %o0, 0x200, %g5
233 setx TX_CS_Addr, %g1, %g2
234 add %g2, %g5, %g2
235 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
236 nop
237
238SetTxRingKick_5:
239 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_5)) -> NIU_SetTxRingKick(0, 5, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
240 setx 0x5, %g1, %o0
241 ldx [%g2] , %g3
242 nop
243 mulx %o0, 0x200, %g5
244 setx TX_RING_KICK_Addr, %g1, %g2
245 add %g2, %g5, %g2
246 setx 0x40, %g1, %g3
247 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
248 nop
249
250SetTxCs_5 :
251 setx 0x5, %g1, %o0
252 setx TX_CS_Data, %g1, %g3
253 mulx %o0, 0x200, %g5
254 setx TX_CS_Addr, %g1, %g2
255 add %g2, %g5, %g2
256 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
257 nop
258
259SetTxRingKick_6:
260 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_6)) -> NIU_SetTxRingKick(0, 6, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
261 setx 0x6, %g1, %o0
262 ldx [%g2] , %g3
263 nop
264 mulx %o0, 0x200, %g5
265 setx TX_RING_KICK_Addr, %g1, %g2
266 add %g2, %g5, %g2
267 setx 0x40, %g1, %g3
268 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
269 nop
270
271SetTxCs_6 :
272 setx 0x6, %g1, %o0
273 setx TX_CS_Data, %g1, %g3
274 mulx %o0, 0x200, %g5
275 setx TX_CS_Addr, %g1, %g2
276 add %g2, %g5, %g2
277 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
278 nop
279
280SetTxRingKick_7:
281 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_7)) -> NIU_SetTxRingKick(0, 7, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
282 setx 0x7, %g1, %o0
283 ldx [%g2] , %g3
284 nop
285 mulx %o0, 0x200, %g5
286 setx TX_RING_KICK_Addr, %g1, %g2
287 add %g2, %g5, %g2
288 setx 0x40, %g1, %g3
289 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
290 nop
291
292SetTxCs_7 :
293 setx 0x7, %g1, %o0
294 setx TX_CS_Data, %g1, %g3
295 mulx %o0, 0x200, %g5
296 setx TX_CS_Addr, %g1, %g2
297 add %g2, %g5, %g2
298 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
299 nop
300
301SetTxRingKick_8:
302 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_8)) -> NIU_SetTxRingKick(1, 8, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
303 setx 0x8, %g1, %o0
304 ldx [%g2] , %g3
305 nop
306 mulx %o0, 0x200, %g5
307 setx TX_RING_KICK_Addr, %g1, %g2
308 add %g2, %g5, %g2
309 setx 0x40, %g1, %g3
310 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
311 nop
312
313SetTxCs_8 :
314 setx 0x8, %g1, %o0
315 setx TX_CS_Data, %g1, %g3
316 mulx %o0, 0x200, %g5
317 setx TX_CS_Addr, %g1, %g2
318 add %g2, %g5, %g2
319 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
320 nop
321
322SetTxRingKick_9:
323 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_9)) -> NIU_SetTxRingKick(1, 9, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
324 setx 0x9, %g1, %o0
325 ldx [%g2] , %g3
326 nop
327 mulx %o0, 0x200, %g5
328 setx TX_RING_KICK_Addr, %g1, %g2
329 add %g2, %g5, %g2
330 setx 0x40, %g1, %g3
331 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
332 nop
333
334SetTxCs_9 :
335 setx 0x9, %g1, %o0
336 setx TX_CS_Data, %g1, %g3
337 mulx %o0, 0x200, %g5
338 setx TX_CS_Addr, %g1, %g2
339 add %g2, %g5, %g2
340 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
341 nop
342
343SetTxRingKick_a:
344 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_a)) -> NIU_SetTxRingKick(1, a, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
345 setx 0xa, %g1, %o0
346 ldx [%g2] , %g3
347 nop
348 mulx %o0, 0x200, %g5
349 setx TX_RING_KICK_Addr, %g1, %g2
350 add %g2, %g5, %g2
351 setx 0x40, %g1, %g3
352 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
353 nop
354
355SetTxCs_a :
356 setx 0xa, %g1, %o0
357 setx TX_CS_Data, %g1, %g3
358 mulx %o0, 0x200, %g5
359 setx TX_CS_Addr, %g1, %g2
360 add %g2, %g5, %g2
361 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
362 nop
363
364SetTxRingKick_b:
365 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_b)) -> NIU_SetTxRingKick(1, b, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
366 setx 0xb, %g1, %o0
367 ldx [%g2] , %g3
368 nop
369 mulx %o0, 0x200, %g5
370 setx TX_RING_KICK_Addr, %g1, %g2
371 add %g2, %g5, %g2
372 setx 0x40, %g1, %g3
373 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
374 nop
375
376SetTxCs_b :
377 setx 0xb, %g1, %o0
378 setx TX_CS_Data, %g1, %g3
379 mulx %o0, 0x200, %g5
380 setx TX_CS_Addr, %g1, %g2
381 add %g2, %g5, %g2
382 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
383 nop
384
385SetTxRingKick_c:
386 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_c)) -> NIU_SetTxRingKick(1, c, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
387 setx 0xc, %g1, %o0
388 ldx [%g2] , %g3
389 nop
390 mulx %o0, 0x200, %g5
391 setx TX_RING_KICK_Addr, %g1, %g2
392 add %g2, %g5, %g2
393 setx 0x40, %g1, %g3
394 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
395 nop
396
397SetTxCs_c :
398 setx 0xc, %g1, %o0
399 setx TX_CS_Data, %g1, %g3
400 mulx %o0, 0x200, %g5
401 setx TX_CS_Addr, %g1, %g2
402 add %g2, %g5, %g2
403 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
404 nop
405
406SetTxRingKick_d:
407 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_d)) -> NIU_SetTxRingKick(1, d, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
408 setx 0xd, %g1, %o0
409 ldx [%g2] , %g3
410 nop
411 mulx %o0, 0x200, %g5
412 setx TX_RING_KICK_Addr, %g1, %g2
413 add %g2, %g5, %g2
414 setx 0x40, %g1, %g3
415 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
416 nop
417
418SetTxCs_d :
419 setx 0xd, %g1, %o0
420 setx TX_CS_Data, %g1, %g3
421 mulx %o0, 0x200, %g5
422 setx TX_CS_Addr, %g1, %g2
423 add %g2, %g5, %g2
424 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
425 nop
426
427SetTxRingKick_e:
428 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_e)) -> NIU_SetTxRingKick(1, e, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
429 setx 0xe, %g1, %o0
430 ldx [%g2] , %g3
431 nop
432 mulx %o0, 0x200, %g5
433 setx TX_RING_KICK_Addr, %g1, %g2
434 add %g2, %g5, %g2
435 setx 0x40, %g1, %g3
436 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
437 nop
438
439SetTxCs_e :
440 setx 0xe, %g1, %o0
441 setx TX_CS_Data, %g1, %g3
442 mulx %o0, 0x200, %g5
443 setx TX_CS_Addr, %g1, %g2
444 add %g2, %g5, %g2
445 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
446 nop
447
448SetTxRingKick_f:
449 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick_f)) -> NIU_SetTxRingKick(1, f, NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0, NIU_TX_MULTI_DMA_P1)
450 setx 0xf, %g1, %o0
451 ldx [%g2] , %g3
452 nop
453 mulx %o0, 0x200, %g5
454 setx TX_RING_KICK_Addr, %g1, %g2
455 add %g2, %g5, %g2
456 setx 0x40, %g1, %g3
457 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
458 nop
459
460SetTxCs_f :
461 setx 0xf, %g1, %o0
462 setx TX_CS_Data, %g1, %g3
463 mulx %o0, 0x200, %g5
464 setx TX_CS_Addr, %g1, %g2
465 add %g2, %g5, %g2
466 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
467 nop
468
469
470#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
471 setx loop_count, %g1, %g4
472delay_loop:
473 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
474 nop
475 nop
476 nop
477 nop
478 dec %g4
479 brnz %g4, delay_loop
480 nop
481#endif
482
483NIUTx_Pkt_Cnt_Chk_P0:
484 setx 0x0, %g1, %o0 ! MAC PORT
485! setx 0x8, %g1, %o1 ! PKT CNT
486 setx TX_FAIR_PKT_CNT, %g1, %o1 ! PKT CNT
487 call NiuTx_check_pkt_cnt
488 nop
489
490 setx loop_count, %g1, %g4
491delay_loop_end_p0:
492 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
493 nop
494 nop
495 nop
496 nop
497 dec %g4
498 brnz %g4, delay_loop_end_p0
499 nop
500
501NIUTx_Pkt_Cnt_Chk_P1:
502 setx 0x1, %g1, %o0 ! MAC PORT
503! setx 0x8, %g1, %o1 ! PKT CNT
504 setx TX_FAIR_PKT_CNT, %g1, %o1 ! PKT CNT
505 call NiuTx_check_pkt_cnt
506 nop
507
508 setx loop_count, %g1, %g4
509delay_loop_end_p1:
510 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
511 nop
512 nop
513 nop
514 nop
515 dec %g4
516 brnz %g4, delay_loop_end_p1
517 nop
518
519TX_test_passed:
520 nop ! $EV trig_pc_d(1, @VA(.MAIN.TX_test_passed)) -> NIU_EXIT_chk(0)
521 nop ! $EV trig_pc_d(1, @VA(.MAIN.TX_test_passed)) -> NIU_EXIT_chk(1)
522 EXIT_GOOD
523
524!.global test_failed
525!test_failed:
526! nop
527! EXIT_BAD
528
529
530!
531! Thread 1 Start
532!
533!
534thread_1:
535
536/************************************************************************
537 NIU RX Template Port 0 ---> DMA(0,2,4,6)
538 Port 1 ---> DMA(1,3,5,7)
539 ************************************************************************/
540
541!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
542! Init DMA Channel 0 @@@@@@@@@@@@@@@@@@@@@@@@@@@@
543!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
544
545P_NIU_RxInitDma_0:
546 setx TX_CS, %g1, %g2
547 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma_0)) -> NIU_InitRxDma(0, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, 0x0, NIU_RX_MULTI_DMA)
548 setx 0x5, %g1, %g4
549delay_loop_Rx_0:
550 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
551 nop
552 nop
553 nop
554 nop
555 dec %g4
556 brnz %g4, delay_loop_Rx_0
557 nop
558
559 nop
560 setx 0x0, %g1, %o0
561 setx 0x0, %g1, %o1
562 setx RX_DESC_RING_LENGTH, %g1, %o2
563 setx RX_COMPL_RING_LEN, %g1, %o3
564 setx RBR_CONFIG_B_DATA, %g1, %o4
565 setx RX_INITIAL_KICK, %g1, %o5
566 setx NIU_RX_MULTI_DMA, %g1, %o6
567 call NiuInitRxDma
568 nop
569!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
570! Init DMA Channel 2 @@@@@@@@@@@@@@@@@@@@@@@@@@@@
571!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
572
573P_NIU_RxInitDma_2:
574 setx TX_CS, %g1, %g2
575 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma_2)) -> NIU_InitRxDma(2, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, 0x0, NIU_RX_MULTI_DMA)
576 setx 0x5, %g1, %g4
577delay_loop_Rx_2:
578 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
579 nop
580 nop
581 nop
582 nop
583 dec %g4
584 brnz %g4, delay_loop_Rx_2
585 nop
586
587 nop
588 setx 0x2, %g1, %o0
589 setx 0x2, %g1, %l2
590 setx RX_DESC_RING_LENGTH, %g1, %o2
591 setx RX_COMPL_RING_LEN, %g1, %o3
592 setx RBR_CONFIG_B_DATA, %g1, %o4
593 setx RX_INITIAL_KICK, %g1, %o5
594 setx 0x0, %g1, %o6
595 call NiuInitRxDma
596 nop
597!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
598! Init DMA Channel 4 @@@@@@@@@@@@@@@@@@@@@@@@@@@@
599!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
600
601P_NIU_RxInitDma_4:
602 setx TX_CS, %g1, %g2
603 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma_4)) -> NIU_InitRxDma(4, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, 0x0, NIU_RX_MULTI_DMA)
604 setx 0x5, %g1, %g4
605delay_loop_Rx_4:
606 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
607 nop
608 nop
609 nop
610 nop
611 dec %g4
612 brnz %g4, delay_loop_Rx_4
613 nop
614
615 nop
616 setx 0x4, %g1, %o0
617 setx 0x4, %g1, %l3
618 setx RX_DESC_RING_LENGTH, %g1, %o2
619 setx RX_COMPL_RING_LEN, %g1, %o3
620 setx RBR_CONFIG_B_DATA, %g1, %o4
621 setx RX_INITIAL_KICK, %g1, %o5
622 setx 0x0, %g1, %o6
623 call NiuInitRxDma
624 nop
625!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
626! Init DMA Channel 6 @@@@@@@@@@@@@@@@@@@@@@@@@@@@
627!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
628
629P_NIU_RxInitDma_6:
630 setx TX_CS, %g1, %g2
631 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma_6)) -> NIU_InitRxDma(6, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, 0x0, NIU_RX_MULTI_DMA)
632 setx 0x5, %g1, %g4
633delay_loop_Rx_6:
634 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
635 nop
636 nop
637 nop
638 nop
639 dec %g4
640 brnz %g4, delay_loop_Rx_6
641 nop
642
643 nop
644 setx 0x6, %g1, %o0
645 setx 0x6, %g1, %l4
646 setx RX_DESC_RING_LENGTH, %g1, %o2
647 setx RX_COMPL_RING_LEN, %g1, %o3
648 setx RBR_CONFIG_B_DATA, %g1, %o4
649 setx RX_INITIAL_KICK, %g1, %o5
650 setx 0x0, %g1, %o6
651 call NiuInitRxDma
652 nop
653!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
654! Init DMA Channel 1 @@@@@@@@@@@@@@@@@@@@@@@@@@@@
655!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
656
657P_NIU_RxInitDma_1:
658 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma_1)) -> NIU_InitRxDma(1, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, 0x0, NIU_RX_MULTI_DMA)
659 setx 0x5, %g1, %g4
660delay_loop_Rx_1:
661 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
662 nop
663 nop
664 nop
665 nop
666 dec %g4
667 brnz %g4, delay_loop_Rx_1
668 nop
669
670 nop
671 setx 0x1, %g1, %o0
672 setx RX_DESC_RING_LENGTH, %g1, %o2
673 setx RX_COMPL_RING_LEN, %g1, %o3
674 setx RBR_CONFIG_B_DATA, %g1, %o4
675 setx RX_INITIAL_KICK, %g1, %o5
676 setx 0x0, %g1, %o6
677 call NiuInitRxDma
678 nop
679!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
680! Init DMA Channel 3 @@@@@@@@@@@@@@@@@@@@@@@@@@@@
681!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
682
683P_NIU_RxInitDma_3:
684 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma_3)) -> NIU_InitRxDma(3, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, 0x0, NIU_RX_MULTI_DMA)
685 setx 0x5, %g1, %g4
686delay_loop_Rx_3:
687 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
688 nop
689 nop
690 nop
691 nop
692 dec %g4
693 brnz %g4, delay_loop_Rx_3
694 nop
695
696 nop
697 setx 0x3, %g1, %o0
698 setx RX_DESC_RING_LENGTH, %g1, %o2
699 setx RX_COMPL_RING_LEN, %g1, %o3
700 setx RBR_CONFIG_B_DATA, %g1, %o4
701 setx RX_INITIAL_KICK, %g1, %o5
702 setx 0x0, %g1, %o6
703 call NiuInitRxDma
704 nop
705!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
706! Init DMA Channel 5 @@@@@@@@@@@@@@@@@@@@@@@@@@@@
707!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
708
709P_NIU_RxInitDma_5:
710 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma_5)) -> NIU_InitRxDma(5, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, 0x0, NIU_RX_MULTI_DMA)
711 setx 0x5, %g1, %g4
712delay_loop_Rx_5:
713 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
714 nop
715 nop
716 nop
717 nop
718 dec %g4
719 brnz %g4, delay_loop_Rx_5
720 nop
721
722 nop
723 setx 0x5, %g1, %o0
724 setx RX_DESC_RING_LENGTH, %g1, %o2
725 setx RX_COMPL_RING_LEN, %g1, %o3
726 setx RBR_CONFIG_B_DATA, %g1, %o4
727 setx RX_INITIAL_KICK, %g1, %o5
728 setx 0x0, %g1, %o6
729 call NiuInitRxDma
730 nop
731!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
732! Init DMA Channel 7 @@@@@@@@@@@@@@@@@@@@@@@@@@@@
733!@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
734
735P_NIU_RxInitDma_7:
736 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma_7)) -> NIU_InitRxDma(7, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, 0x0, NIU_RX_MULTI_DMA)
737 setx 0x5, %g1, %g4
738delay_loop_Rx_7:
739 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
740 nop
741 nop
742 nop
743 nop
744 dec %g4
745 brnz %g4, delay_loop_Rx_7
746 nop
747
748 nop
749 setx 0x7, %g1, %o0
750 setx RX_DESC_RING_LENGTH, %g1, %o2
751 setx RX_COMPL_RING_LEN, %g1, %o3
752 setx RBR_CONFIG_B_DATA, %g1, %o4
753 setx RX_INITIAL_KICK, %g1, %o5
754 setx 0x0, %g1, %o6
755 call NiuInitRxDma
756 nop
757P0_NIU_RxPkt_Conf:
758 nop ! $EV trig_pc_d(1, @VA(.MAIN.P0_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT,0)
759 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
760 nop
761P1_NIU_RxPkt_Conf:
762 nop ! $EV trig_pc_d(1, @VA(.MAIN.P1_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT,1)
763 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
764 nop
765P_NIU_Rx_GenPkt:
766 setx RXMAC_PKTCNT, %g1, %g6
767 nop
768Rx_pktcnt_loop:
769 nop ! $EV trig_pc_d(1, @VA(.MAIN.Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, 0, RXMAC_PKTCNT, 0x100,0x1, NIU_RX_MULTI_DMA, 1)
770 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
771 nop
772 nop
773 nop
774 nop
775
776delay_loop0:
777 mov %g0, %g5
778
779 setx 0x0, %g7, %g1
780 mulx %g1, 0x200, %g4
781 setx RCR_STAT_A, %g7, %g2
782 add %g2, %g4, %g2
783 ldxa [%g2]ASI_PRIMARY_LITTLE, %l2
784 add %l2, %l3, %g5
785
786 setx 0x1, %g7, %g1
787 mulx %g1, 0x200, %g4
788 setx RCR_STAT_A, %g7, %g2
789 add %g2, %g4, %g2
790 ldxa [%g2]ASI_PRIMARY_LITTLE, %l2
791 add %l2, %g4, %g5
792
793 setx 0x2, %g7, %g1
794 mulx %g1, 0x200, %g4
795 setx RCR_STAT_A, %g7, %g2
796 add %g2, %g4, %g2
797 ldxa [%g2]ASI_PRIMARY_LITTLE, %l2
798 add %l2, %g4, %g5
799
800 setx 0x3, %g7, %g1
801 mulx %g1, 0x200, %g4
802 setx RCR_STAT_A, %g7, %g2
803 add %g2, %g4, %g2
804 ldxa [%g2]ASI_PRIMARY_LITTLE, %l2
805 add %l2, %g4, %g5
806
807 setx 0x4, %g7, %g1
808 mulx %g1, 0x200, %g4
809 setx RCR_STAT_A, %g7, %g2
810 add %g2, %g4, %g2
811 ldxa [%g2]ASI_PRIMARY_LITTLE, %l2
812 add %l2, %g4, %g5
813
814 setx 0x5, %g7, %g1
815 mulx %g1, 0x200, %g4
816 setx RCR_STAT_A, %g7, %g2
817 add %g2, %g4, %g2
818 ldxa [%g2]ASI_PRIMARY_LITTLE, %l2
819 add %l2, %g4, %g5
820
821 setx 0x6, %g7, %g1
822 mulx %g1, 0x200, %g4
823 setx RCR_STAT_A, %g7, %g2
824 add %g2, %g4, %g2
825 ldxa [%g2]ASI_PRIMARY_LITTLE, %l2
826 add %l2, %g4, %g5
827
828 setx 0x7, %g7, %g1
829 mulx %g1, 0x200, %g4
830 setx RCR_STAT_A, %g7, %g2
831 add %g2, %g4, %g2
832 ldxa [%g2]ASI_PRIMARY_LITTLE, %l2
833 add %l2, %g4, %g5
834
835 cmp %g5, FAIR_PKT_COUNT
836 bne delay_loop0
837 nop
838
839
840RX_test_passed:
841 nop
842 EXIT_GOOD
843
844
845/************************************************************************/
846
847SECTION SetRxLogMask1_init data_va=0x200000100
848attr_data {
849 Name = SetRxLogMask1_init,
850 hypervisor,
851 compressimage
852 }
853.data
854SetRxLogMask1_init:
855 .xword 0x0060452301000484
856/************************************************************************/
857
858SECTION SetRxLogVal1_init data_va=0x200000200
859attr_data {
860 Name = SetRxLogVal1_init,
861 hypervisor,
862 compressimage
863 }
864.data
865SetRxLogVal1_init:
866 .xword 0x0060452301000484
867/************************************************************************/
868
869SECTION SetRxLogRelo1_init data_va=0x200000300
870attr_data {
871 Name = SetRxLogRelo1_init,
872 hypervisor,
873 compressimage
874 }
875.data
876SetRxLogRelo1_init:
877 .xword 0x0060452301000484
878/************************************************************************/
879
880SECTION SetRxLogPgVld_init data_va=0x200000400
881attr_data {
882 Name = SetRxLogPgVld_init,
883 hypervisor,
884 compressimage
885 }
886.data
887SetRxLogPgVld_init:
888 .xword 0x0060452301000484
889/************************************************************************/
890SECTION SetRbrConfig_A_init data_va=0x200000500
891attr_data {
892 Name = SetRbrConfig_A_init,
893 hypervisor,
894 compressimage
895 }
896.data
897SetRbrConfig_A_init:
898 .xword 0x0060452301000484
899/************************************************************************/
900SECTION SetRbrConfig_B_init data_va=0x200000600
901attr_data {
902 Name = SetRbrConfig_B_init,
903 hypervisor,
904 compressimage
905 }
906.data
907SetRbrConfig_B_init:
908 .xword 0x0060452301000484
909/************************************************************************/
910SECTION SetRcrConfig_A_init data_va=0x200000700
911attr_data {
912 Name = SetRcrConfig_A_init,
913 hypervisor,
914 compressimage
915 }
916.data
917SetRcrConfig_A_init:
918 .xword 0x0060452301000484
919/************************************************************************/
920SECTION SetRxDmaCfig_1_0_init data_va=0x200000800
921attr_data {
922 Name = SetRxDmaCfig_1_0_init,
923 hypervisor,
924 compressimage
925 }
926.data
927SetRxDmaCfig_1_0_init:
928 .xword 0x0060452301000484
929/************************************************************************/
930SECTION SetRxdmaCfig2Start_init data_va=0x200000900
931attr_data {
932 Name = SetRxdmaCfig2Start_init,
933 hypervisor,
934 compressimage
935 }
936.data
937SetRxdmaCfig2Start_init:
938 .xword 0x0060452301000484
939/************************************************************************/
940SECTION SetRxDmaCfig_1_1_init data_va=0x200000a00
941attr_data {
942 Name = SetRxDmaCfig_1_1_init,
943 hypervisor,
944 compressimage
945 }
946.data
947SetRxDmaCfig_1_1_init:
948 .xword 0x0060452301000484
949
950/************************************************************************/
951
952SECTION SetRxRingKick_init data_va=0x200000b00
953attr_data {
954 Name = SetRxRingKick_init,
955 hypervisor,
956 compressimage
957 }
958.data
959SetRxRingKick_init:
960 .xword 0x0060452301000484
961/************************************************************************/
962
963SECTION SetRxLogMask2_init data_va=0x200000c00
964attr_data {
965 Name = SetRxLogMask2_init,
966 hypervisor,
967 compressimage
968 }
969.data
970SetRxLogMask2_init:
971 .xword 0x0060452301000484
972/************************************************************************/
973
974SECTION SetRxLogVal2_init data_va=0x200000d00
975attr_data {
976 Name = SetRxLogVal2_init,
977 hypervisor,
978 compressimage
979 }
980.data
981SetRxLogVal2_init:
982 .xword 0x0060452301000484
983/************************************************************************/
984
985SECTION SetRxLogRelo2_init data_va=0x200000e00
986attr_data {
987 Name = SetRxLogRelo2_init,
988 hypervisor,
989 compressimage
990 }
991.data
992SetRxLogRelo2_init:
993 .xword 0x0060452301000484
994
995/************************************************************************/
996
997/************************************************************************
998 Test case data start
999 ************************************************************************/
1000/* These initialization is temporary, as there looks some bug in mempli */
1001
1002SECTION SetRngConfig_init data_va=0x100000000
1003attr_data {
1004 Name = SetRngConfig_init,
1005 hypervisor,
1006 compressimage
1007 }
1008.data
1009SetRngConfig_init:
1010 .xword 0x0060452301000484
1011/************************************************************************/
1012
1013SECTION SetTxRingKick_init data_va=0x100000100
1014attr_data {
1015 Name = SetTxRingKick_init,
1016 hypervisor,
1017 compressimage
1018 }
1019.data
1020SetTxRingKick_init:
1021 .xword 0x0060452301000484
1022/************************************************************************/
1023
1024SECTION SetTxLPMask1_init data_va=0x100000200
1025attr_data {
1026 Name = SetTxLPMask1_init,
1027 hypervisor,
1028 compressimage
1029 }
1030.data
1031SetTxLPMask1_init:
1032 .xword 0x0060452301000484
1033/************************************************************************/
1034
1035SECTION SetTxLPValue1_init data_va=0x100000300
1036attr_data {
1037 Name = SetTxLPValue1_init,
1038 hypervisor,
1039 compressimage
1040 }
1041.data
1042SetTxLPValue1_init:
1043 .xword 0x0060452301000484
1044/************************************************************************/
1045
1046SECTION SetTxLPRELOC1_init data_va=0x100000400
1047attr_data {
1048 Name = SetTxLPRELOC1_init,
1049 hypervisor,
1050 compressimage
1051 }
1052.data
1053SetTxLPRELOC1_init:
1054 .xword 0x0060452301000484
1055/************************************************************************/
1056SECTION SetTxLPMask2_init data_va=0x100000500
1057attr_data {
1058 Name = SetTxLPMask2_init,
1059 hypervisor,
1060 compressimage
1061 }
1062.data
1063SetTxLPMask2_init:
1064 .xword 0x0060452301000484
1065/************************************************************************/
1066SECTION SetTxLPValue2_init data_va=0x100000600
1067attr_data {
1068 Name = SetTxLPValue2_init,
1069 hypervisor,
1070 compressimage
1071 }
1072.data
1073SetTxLPValue2_init:
1074 .xword 0x0060452301000484
1075
1076/************************************************************************/
1077SECTION SetTxLPRELOC2_init data_va=0x100000700
1078attr_data {
1079 Name = SetTxLPRELOC2_init,
1080 hypervisor,
1081 compressimage
1082 }
1083.data
1084SetTxLPRELOC2_init:
1085 .xword 0x0060452301000484
1086
1087/************************************************************************/
1088SECTION SetTxLPValid_init data_va=0x100000800
1089attr_data {
1090 Name = SetTxLPValid_init,
1091 hypervisor,
1092 compressimage
1093 }
1094.data
1095SetTxLPValid_init:
1096 .xword 0x0060452301000484
1097
1098/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.