projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / niu / basic_niu_pio_mask.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: basic_niu_pio_mask.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40//#include "defines.h"
41//#include "nmacros.h"
42#include "hboot.s"
43#include "asi_s.h"
44
45/************************************************************************
46 Test case code start
47 ************************************************************************/
48#define XPCS_CONTROL1 mpeval( 0x000 <<1)
49#define XPCS_STATUS1 mpeval( 0x004 <<1)
50#define XPCS_DEVICE_ID mpeval( 0x008 <<1)
51#define XPCS_SPEED_ABILITY mpeval( 0x00C <<1)
52#define XPCS_DEVICE_IN_PKG mpeval( 0x010 <<1)
53#define XPCS_CONTROL2 mpeval( 0x014 <<1)
54#define XPCS_STATUS2 mpeval( 0x018 <<1)
55#define XPCS_PKG_ID mpeval( 0x01C <<1)
56#define XPCS_STATUS mpeval( 0x020 <<1)
57#define XPCS_TEST_CONTROL mpeval( 0x024 <<1)
58#define XPCS_CONFIG_VENDOR1 mpeval( 0x028 <<1)
59#define XPCS_DIAG_VENDOR2 mpeval( 0x02C <<1)
60#define XPCS_MASK1 mpeval( 0x030 <<1)
61#define XPCS_PACKET_COUNTER mpeval( 0x034 <<1)
62#define XPCS_TX_STATEMACHINE mpeval( 0x038 <<1)
63#define XPCS_TX_DESKWERR_COUNTER mpeval( 0x03C <<1)
64
65#define NIU_BASE_ADDRESS 0x8100000000
66#define FZC_MAC_BASE_ADDRESS 0x180000
67#define TXC_BASE_ADDRESS 0x700000
68#define FZC_TXC_BASE_ADDRESS 0x780000
69
70#define TXC_DMA_MAXBURST 0x000
71#define TXC_DMA_MAXBURST_MASK 0x000000000000ffff
72#define TXC_PORT_CONTROL_MASK 0x000000000000ffff
73#define TXC_PORT0_DMA_ENBALE 0x028
74#define TXC_PORT0_CONTROL 0x010
75#define TXC_PORT1_CONTROL 0x018
76#define TXC_CONTROL 0x000
77#define TXC_CONTROL_MASK 0x000000000000001f
78#define XPCS_0_RANGE mpeval(0x00001000 << 1)
79#define XPCS_1_RANGE mpeval(0x00004000 << 1)
80
81#define NEPTUNE_BASE_ADDRESS NIU_BASE_ADDRESS
82#define MAC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_MAC_BASE_ADDRESS)
83#define XPCS0_BASE mpeval(MAC_ADDRESS_RANGE + XPCS_0_RANGE)
84#define XPCS1_BASE mpeval(MAC_ADDRESS_RANGE + XPCS_1_RANGE)
85#define TXC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + TXC_BASE_ADDRESS)
86#define FZC_TXC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_TXC_BASE_ADDRESS)
87
88#define TXC_DMA0_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x00 << 12))
89#define TXC_FZC_BASE mpeval(FZC_TXC_ADDRESS_RANGE + (0x20 << 12))
90#define TXC_PIO_BASE mpeval(TXC_ADDRESS_RANGE + (0x20 << 12))
91
92#define xpcs_reg0_addr mpeval(XPCS0_BASE + XPCS_CONTROL1)
93#define xpcs_reg1_addr mpeval(XPCS0_BASE + XPCS_TEST_CONTROL)
94#define xpcs_reg2_addr mpeval(XPCS0_BASE + XPCS_CONFIG_VENDOR1)
95#define xpcs_reg3_addr mpeval(XPCS0_BASE + XPCS_DIAG_VENDOR2)
96#define xpcs_reg4_addr mpeval(XPCS0_BASE + XPCS_MASK1)
97#define xpcs_reg5_addr mpeval(XPCS0_BASE + XPCS_PACKET_COUNTER)
98#define xpcs_reg6_addr mpeval(XPCS0_BASE + XPCS_TX_DESKWERR_COUNTER)
99#define xpcs_reg7_addr mpeval(XPCS0_BASE + XPCS_STATUS1)
100#define xpcs_reg8_addr mpeval(XPCS0_BASE + XPCS_DEVICE_ID)
101#define xpcs_reg9_addr mpeval(XPCS0_BASE + XPCS_SPEED_ABILITY)
102#define xpcs_reg10_addr mpeval(XPCS0_BASE + XPCS_DEVICE_IN_PKG)
103#define xpcs_reg11_addr mpeval(XPCS0_BASE + XPCS_CONTROL2)
104#define xpcs_reg12_addr mpeval(XPCS0_BASE + XPCS_STATUS2)
105#define xpcs_reg13_addr mpeval(XPCS0_BASE + XPCS_PKG_ID)
106#define xpcs_reg14_addr mpeval(XPCS0_BASE + XPCS_STATUS)
107#define xpcs_reg15_addr mpeval(XPCS0_BASE + XPCS_TX_STATEMACHINE)
108
109#define xpcs_reg0_data 0x00002040
110#define xpcs_reg1_data 0x00000000
111#define xpcs_reg2_data 0x00000003
112#define xpcs_reg3_data 0x00000000
113#define xpcs_reg4_data 0x00000084
114#define xpcs_reg5_data 0x00000000
115#define xpcs_reg6_data 0x00000000
116#define xpcs_reg7_data 0x00000080
117#define xpcs_reg8_data 0x00000000
118#define xpcs_reg9_data 0x00000001
119#define xpcs_reg10_data 0xC0000008
120#define xpcs_reg11_data 0x00000001
121#define xpcs_reg12_data 0x00000802
122#define xpcs_reg13_data 0x00000000
123#define xpcs_reg14_data 0x00000800
124#define xpcs_reg15_data 0x0000000C
125
126#define txc_dma0_addr mpeval(TXC_DMA0_BASE + TXC_DMA_MAXBURST)
127#define fzc_txc_addr mpeval(TXC_FZC_BASE + TXC_PORT0_CONTROL)
128#define txc_pio_addr mpeval(TXC_PIO_BASE + TXC_CONTROL)
129#define txc_port0_dma_enbale mpeval(TXC_FZC_BASE + TXC_PORT0_DMA_ENBALE)
130
131#define txc_dma0_data 0xa5a5a5a5a5a5a5a5
132#define fzc_txc_data 0xffffffffffffffff
133#define txc_pio_data 0x1f
134
135#define DMC_BASE_ADDRESS 0x600000
136#define FZC_DMC_BASE_ADDRESS 0x680000
137#define DMC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + DMC_BASE_ADDRESS)
138#define FZC_DMC_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_DMC_BASE_ADDRESS)
139#define RX_ADDR_MD mpeval(FZC_DMC_ADDRESS_RANGE+0x00070)
140#define RDC_TABLE_BASE mpeval(FZC_DMC_ADDRESS_RANGE+0x10000)
141#define RX_LOG_PAGE_VLD mpeval(FZC_DMC_ADDRESS_RANGE+0x20000)
142#define RX_LOG_PAGE1 mpeval(FZC_DMC_ADDRESS_RANGE+0x20008)
143#define RX_LOG_PAGE2 mpeval(FZC_DMC_ADDRESS_RANGE+0x20010)
144#define RX_LOG_PAGE_RELO1 mpeval(FZC_DMC_ADDRESS_RANGE+0x20018)
145#define RX_LOG_PAGE_RELO2 mpeval(FZC_DMC_ADDRESS_RANGE+0x20020)
146#define Rx_LOG_PAGE_HDL mpeval(FZC_DMC_ADDRESS_RANGE+0x20028)
147#define RDC_RED_PARA mpeval(FZC_DMC_ADDRESS_RANGE+0x30000)
148#define RXDMA_CFIG_BASE mpeval(DMC_ADDRESS_RANGE+0x00000)
149#define RBR_CFIG_A mpeval(DMC_ADDRESS_RANGE+0x00010)
150#define RCRCFIG_A mpeval(DMC_ADDRESS_RANGE+0x00040)
151#define TBR_CFIG_A mpeval(DMC_ADDRESS_RANGE+0x10000)
152#define RBR_KICK mpeval(DMC_ADDRESS_RANGE+0x00020)
153#define RBR_HD mpeval(DMC_ADDRESS_RANGE+0x00030)
154#define RBR_TL mpeval(DMC_ADDRESS_RANGE+0x00038)
155#define FZC_FFLP_BASE_ADDRESS 0x380000
156#define FZC_FFLP_BASE_OFFSET 0x020000
157#define FFLP_CONFIG 0x00100
158#define FFLP_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_FFLP_BASE_ADDRESS + FZC_FFLP_BASE_OFFSET)
159
160#define xpcs0_config_vendor1 mpeval(XPCS0_BASE + XPCS_CONFIG_VENDOR1)
161#define xpcs1_config_vendor1 mpeval(XPCS1_BASE + XPCS_CONFIG_VENDOR1)
162#define fflp_reg0 mpeval(FFLP_ADDRESS_RANGE +FFLP_CONFIG)
163#define txc_reg0 mpeval(TXC_DMA0_BASE + TXC_DMA_MAXBURST)
164#define txc_reg1 mpeval(TXC_FZC_BASE+ TXC_PORT0_CONTROL)
165#define txc_reg2 mpeval(TXC_FZC_BASE+ TXC_PORT1_CONTROL)
166#define txc_reg3 mpeval(TXC_PIO_BASE + TXC_CONTROL)
167
168.text
169.global main
170
171main:
172 ta T_CHANGE_HPRIV
173 nop
174
175!
176! Thread 0 Start
177!
178thread_0:
179
180 setx xpcs0_config_vendor1, %g1, %g2
181 stxa %g0, [%g2]ASI_PRIMARY_LITTLE
182 nop
183
184 setx xpcs1_config_vendor1, %g1, %g2
185 stxa %g0, [%g2]ASI_PRIMARY_LITTLE
186 nop
187
188txc_sanity_tx:
189 set 0x2, %g4
190 setx txc_dma0_addr, %g1, %g2
191 setx TXC_DMA_MAXBURST_MASK, %g1, %g6
192 setx txc_dma0_data, %g1, %g3
193
194pattern_loop1:
195 and %g3, %g6, %g1
196 stxa %g1, [%g2]ASI_PRIMARY_LITTLE
197 nop
198
199 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
200 nop
201 cmp %g5, %g1
202 bne test_failed
203 nop
204
205 inc %g3
206 dec %g4
207 brnz %g4, pattern_loop1
208 nop
209
210 setx txc_port0_dma_enbale, %g1, %g2
211 setx TXC_PORT_CONTROL_MASK, %g1, %g6
212 setx fzc_txc_data, %g1, %g3
213 and %g3, %g6, %g1
214 stxa %g1, [%g2]ASI_PRIMARY_LITTLE
215 nop
216
217 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
218 nop
219 cmp %g5, %g1
220 bne test_failed
221 nop
222
223
224// This code is to access an invalid address.
225// Nack is detected by a checker. Disabling in this
226// basic diag. Need to add to another diag
227
228 setx txc_pio_addr, %g1, %g2
229 setx TXC_CONTROL_MASK, %g1, %g6
230 setx txc_pio_data, %g1, %g3
231 and %g3, %g6, %g1
232// stxa %g1, [%g2]ASI_PRIMARY_LITTLE
233 nop
234
235// ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
236 nop
237// cmp %g5, %g1
238// bne test_failed
239 nop
240
241test_passed:
242 EXIT_GOOD
243
244test_failed:
245 EXIT_BAD
246
247
248/************************************************************************
249 Test case data start
250 ************************************************************************/
251.data
252user_data_start:
253 .xword 0x0000000000000000
254 .xword 0xffffffffffffffff
255 .xword 0xa55a5aa5a55a5aa5
256 .xword 0x5aa5a55a5aa5a55a
257.end
258
259
260
Full OpenSPARC design & verification tarball including full HDL.