[OpenSPARC-T2-DV] / verif / diag / assembly / niu / niu_ipp_regs.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: niu_ipp_regs.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
!#include "asi_s.h"


#define FZC_IPP_BASE_ADDRESS   0x280000
#define NIU_BASE_ADDRESS       0x8100000000
#define IPP_ADDRESS_RANGE      mpeval(NIU_BASE_ADDRESS + FZC_IPP_BASE_ADDRESS)

#define IPP_CFIG    		0x00000
#define IPP_CFIG1    		0x00000
#define IPP_CFIG2    		0x08000
#define CFIG              	mpeval(IPP_ADDRESS_RANGE + IPP_CFIG)
#define CFIG1              	mpeval(IPP_ADDRESS_RANGE + IPP_CFIG1)
#define CFIG2              	mpeval(IPP_ADDRESS_RANGE + IPP_CFIG2)

#define IPP_PKT_DIS1   		0x00020
#define IPP_PKT_DIS2   		0x08020
#define PKT_DIS1              	mpeval(IPP_ADDRESS_RANGE + IPP_PKT_DIS1)
#define PKT_DIS2              	mpeval(IPP_ADDRESS_RANGE + IPP_PKT_DIS2)

#define IPP_MSK1   		0x00048
#define IPP_MSK2   		0x08048
#define MSK1              	mpeval(IPP_ADDRESS_RANGE + IPP_MSK1)
#define MSK2              	mpeval(IPP_ADDRESS_RANGE + IPP_MSK2)

#define DATA_EN_32BITS    	0x00000000ffffffff
#define DATA_EN_25BITS          0x0000000001ffffff
#define DATA_EN_20BITS    	0x00000000000fffff
#define DATA_EN_14BITS    	0x0000000000003fff
#define DATA_EN_8BITS    	0x00000000000000ff
#define DATA_EN_7BITS    	0x000000000000007f
#define DATA_EN_6BITS    	0x000000000000003f

.text
.global	 main


main:
    ta   T_CHANGE_HPRIV

get_th_id:
    ta   T_RD_THID

//    cmp  %o1,0x0
//    bne  test_pass
    nop

!Write then read data of IPP_CFIG count 2 step x8000 
 setx CFIG,%g7,%g1
    setx wdata,%g7,%g2
    set  2,%g8

loop12:
    set  0x05,%g3
loop13:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_25BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop13
    nop
    add  %g1,2048,%g1
    sub  %g8,1, %g8	
    cmp  %g8,%g0
    bne  loop12	 
    nop

!Write then read data of  IPP_CFIG1  
 setx CFIG1,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop1:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_25BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop1
    nop


!Write then read data of  IPP_CFIG2  
 setx CFIG2,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop2:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_25BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop2
    nop


!Write then read data of  IPP_PKT_DIS1  
 setx PKT_DIS1,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop3:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_14BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop3
    nop


!Write then read data of  IPP_PKT_DIS2  
 setx PKT_DIS2,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop4:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_14BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop4
    nop


!Write then read data of  IPP_MSK1  
 setx MSK1,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop5:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_8BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop5
    nop


!Write then read data of  IPP_SMX_MSK2  
 setx MSK2,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop6:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_8BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop6
    nop


/*

!Write then read data of  IPP_SMX_CTL  count 64 step 8 
 setx SMX_CTL,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop7:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_32BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop7
    nop


!Write then read data of  IPP_SMX_CFIG_DAT  count 64 step 8 
 setx SMX_CFIG_DAT,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop8:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx SMX_CFIG_DAT_DATA_MASK, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop8
    nop


!Write then read data of  IPP_LDGITMRES  count 64 step 8 
 setx LDGITMRES,%g7,%g1
    setx wdata,%g7,%g2

    set  0x05,%g3
loop9:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_20BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop9
    nop


!Write then read data of  IPP_DMA_BIND  count 64 step 8 
 setx DMA_BIND,%g7,%g1
    setx wdata,%g7,%g2
    set  64,%g8

loop10:
    set  0x05,%g3
loop11:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DMA_BIND_DATA_MASK, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop11
    nop
    add  %g1,8,%g1
    cmp  %g8,%g0
    bne  loop10	 
    nop


!Write then read data of IPP_LDG_NUM count 69 step 8 
 setx LDG_NUM,%g7,%g1
    setx wdata,%g7,%g2
    set  64,%g8

loop12:
    set  0x05,%g3
loop13:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_6BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop13
    nop
    add  %g1,8,%g1
    cmp  %g8,%g0
    bne  loop12	 
    nop


!Write then read data of IPP_SID count 69 step 8 
 setx SID,%g7,%g1
    setx wdata,%g7,%g2
    set  64,%g8

loop14:
    set  0x05,%g3
loop15:
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE

    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    setx DATA_EN_7BITS, %g7, %g6 
    and %g4, %g6, %g4	

    cmp %g4, %g5
  
    bne %xcc, test_fail


    add  %g2,8,%g2
    sub  %g3,1,%g3
    cmp  %g3,%g0
    bne  loop15
    nop
    add  %g1,8,%g1
    cmp  %g8,%g0
    bne  loop14	 
    nop

*/


/******************************************************
 * Exit code
 *******************************************************/

test_pass:
EXIT_GOOD

test_fail:
EXIT_BAD


.data
.align 0x100
wdata:
    .xword 0xffffffffffffffff
    .xword 0xaaaaaaaaaaaaaaaa
    .xword 0x0000000000000000
    .xword 0x5555555555555555
    .xword 0x0123456789abcdef

.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: niu_ipp_regs.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#include "hboot.s"
	42	!#include "asi_s.h"
	43
	44
	45
	46
	47	#define FZC_IPP_BASE_ADDRESS 0x280000
	48	#define NIU_BASE_ADDRESS 0x8100000000
	49	#define IPP_ADDRESS_RANGE mpeval(NIU_BASE_ADDRESS + FZC_IPP_BASE_ADDRESS)
	50
	51	#define IPP_CFIG 0x00000
	52	#define IPP_CFIG1 0x00000
	53	#define IPP_CFIG2 0x08000
	54	#define CFIG mpeval(IPP_ADDRESS_RANGE + IPP_CFIG)
	55	#define CFIG1 mpeval(IPP_ADDRESS_RANGE + IPP_CFIG1)
	56	#define CFIG2 mpeval(IPP_ADDRESS_RANGE + IPP_CFIG2)
	57
	58	#define IPP_PKT_DIS1 0x00020
	59	#define IPP_PKT_DIS2 0x08020
	60	#define PKT_DIS1 mpeval(IPP_ADDRESS_RANGE + IPP_PKT_DIS1)
	61	#define PKT_DIS2 mpeval(IPP_ADDRESS_RANGE + IPP_PKT_DIS2)
	62
	63	#define IPP_MSK1 0x00048
	64	#define IPP_MSK2 0x08048
65	#define MSK1 mpeval(IPP_ADDRESS_RANGE + IPP_MSK1)
66	#define MSK2 mpeval(IPP_ADDRESS_RANGE + IPP_MSK2)
67
68	#define DATA_EN_32BITS 0x00000000ffffffff
69	#define DATA_EN_25BITS 0x0000000001ffffff
70	#define DATA_EN_20BITS 0x00000000000fffff
71	#define DATA_EN_14BITS 0x0000000000003fff
72	#define DATA_EN_8BITS 0x00000000000000ff
73	#define DATA_EN_7BITS 0x000000000000007f
74	#define DATA_EN_6BITS 0x000000000000003f
75
76	.text
77	.global main
78
79
80	main:
81	ta T_CHANGE_HPRIV
82
83	get_th_id:
84	ta T_RD_THID
85
86	// cmp %o1,0x0
87	// bne test_pass
88	nop
89
90	!Write then read data of IPP_CFIG count 2 step x8000
91	setx CFIG,%g7,%g1
92	setx wdata,%g7,%g2
93	set 2,%g8
94
95	loop12:
96	set 0x05,%g3
97	loop13:
98	ldx [%g2],%g4
99	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
100
101	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
102	setx DATA_EN_25BITS, %g7, %g6
103	and %g4, %g6, %g4
104
105	cmp %g4, %g5
106
107	bne %xcc, test_fail
108
109
110	add %g2,8,%g2
111	sub %g3,1,%g3
112	cmp %g3,%g0
113	bne loop13
114	nop
115	add %g1,2048,%g1
116	sub %g8,1, %g8
117	cmp %g8,%g0
118	bne loop12
119	nop
120
121	!Write then read data of IPP_CFIG1
122	setx CFIG1,%g7,%g1
123	setx wdata,%g7,%g2
124
125	set 0x05,%g3
126	loop1:
127	ldx [%g2],%g4
128	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
129
130	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
131	setx DATA_EN_25BITS, %g7, %g6
132	and %g4, %g6, %g4
133
134	cmp %g4, %g5
135
136	bne %xcc, test_fail
137
138
139	add %g2,8,%g2
140	sub %g3,1,%g3
141	cmp %g3,%g0
142	bne loop1
143	nop
144
145
146
147	!Write then read data of IPP_CFIG2
148	setx CFIG2,%g7,%g1
149	setx wdata,%g7,%g2
150
151	set 0x05,%g3
152	loop2:
153	ldx [%g2],%g4
154	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
155
156	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
157	setx DATA_EN_25BITS, %g7, %g6
158	and %g4, %g6, %g4
159
160	cmp %g4, %g5
161
162	bne %xcc, test_fail
163
164
165	add %g2,8,%g2
166	sub %g3,1,%g3
167	cmp %g3,%g0
168	bne loop2
169	nop
170
171
172
173	!Write then read data of IPP_PKT_DIS1
174	setx PKT_DIS1,%g7,%g1
175	setx wdata,%g7,%g2
176
177	set 0x05,%g3
178	loop3:
179	ldx [%g2],%g4
180	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
181
182	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
183	setx DATA_EN_14BITS, %g7, %g6
184	and %g4, %g6, %g4
185
186	cmp %g4, %g5
187
188	bne %xcc, test_fail
189
190
191	add %g2,8,%g2
192	sub %g3,1,%g3
193	cmp %g3,%g0
194	bne loop3
195	nop
196
197
198
199	!Write then read data of IPP_PKT_DIS2
200	setx PKT_DIS2,%g7,%g1
201	setx wdata,%g7,%g2
202
203	set 0x05,%g3
204	loop4:
205	ldx [%g2],%g4
206	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
207
208	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
209	setx DATA_EN_14BITS, %g7, %g6
210	and %g4, %g6, %g4
211
212	cmp %g4, %g5
213
214	bne %xcc, test_fail
215
216
217	add %g2,8,%g2
218	sub %g3,1,%g3
219	cmp %g3,%g0
220	bne loop4
221	nop
222
223
224
225	!Write then read data of IPP_MSK1
226	setx MSK1,%g7,%g1
227	setx wdata,%g7,%g2
228
229	set 0x05,%g3
230	loop5:
231	ldx [%g2],%g4
232	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
233
234	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
235	setx DATA_EN_8BITS, %g7, %g6
236	and %g4, %g6, %g4
237
238	cmp %g4, %g5
239
240	bne %xcc, test_fail
241
242
243	add %g2,8,%g2
244	sub %g3,1,%g3
245	cmp %g3,%g0
246	bne loop5
247	nop
248
249
250	!Write then read data of IPP_SMX_MSK2
251	setx MSK2,%g7,%g1
252	setx wdata,%g7,%g2
253
254	set 0x05,%g3
255	loop6:
256	ldx [%g2],%g4
257	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
258
259	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
260	setx DATA_EN_8BITS, %g7, %g6
261	and %g4, %g6, %g4
262
263	cmp %g4, %g5
264
265	bne %xcc, test_fail
266
267
268	add %g2,8,%g2
269	sub %g3,1,%g3
270	cmp %g3,%g0
271	bne loop6
272	nop
273
274
275	/*
276
277	!Write then read data of IPP_SMX_CTL count 64 step 8
278	setx SMX_CTL,%g7,%g1
279	setx wdata,%g7,%g2
280
281	set 0x05,%g3
282	loop7:
283	ldx [%g2],%g4
284	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
285
286	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
287	setx DATA_EN_32BITS, %g7, %g6
288	and %g4, %g6, %g4
289
290	cmp %g4, %g5
291
292	bne %xcc, test_fail
293
294
295	add %g2,8,%g2
296	sub %g3,1,%g3
297	cmp %g3,%g0
298	bne loop7
299	nop
300
301
302
303
304	!Write then read data of IPP_SMX_CFIG_DAT count 64 step 8
305	setx SMX_CFIG_DAT,%g7,%g1
306	setx wdata,%g7,%g2
307
308	set 0x05,%g3
309	loop8:
310	ldx [%g2],%g4
311	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
312
313	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
314	setx SMX_CFIG_DAT_DATA_MASK, %g7, %g6
315	and %g4, %g6, %g4
316
317	cmp %g4, %g5
318
319	bne %xcc, test_fail
320
321
322	add %g2,8,%g2
323	sub %g3,1,%g3
324	cmp %g3,%g0
325	bne loop8
326	nop
327
328
329	!Write then read data of IPP_LDGITMRES count 64 step 8
330	setx LDGITMRES,%g7,%g1
331	setx wdata,%g7,%g2
332
333	set 0x05,%g3
334	loop9:
335	ldx [%g2],%g4
336	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
337
338	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
339	setx DATA_EN_20BITS, %g7, %g6
340	and %g4, %g6, %g4
341
342	cmp %g4, %g5
343
344	bne %xcc, test_fail
345
346
347	add %g2,8,%g2
348	sub %g3,1,%g3
349	cmp %g3,%g0
350	bne loop9
351	nop
352
353
354
355	!Write then read data of IPP_DMA_BIND count 64 step 8
356	setx DMA_BIND,%g7,%g1
357	setx wdata,%g7,%g2
358	set 64,%g8
359
360	loop10:
361	set 0x05,%g3
362	loop11:
363	ldx [%g2],%g4
364	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
365
366	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
367	setx DMA_BIND_DATA_MASK, %g7, %g6
368	and %g4, %g6, %g4
369
370	cmp %g4, %g5
371
372	bne %xcc, test_fail
373
374
375	add %g2,8,%g2
376	sub %g3,1,%g3
377	cmp %g3,%g0
378	bne loop11
379	nop
380	add %g1,8,%g1
381	cmp %g8,%g0
382	bne loop10
383	nop
384
385
386
387	!Write then read data of IPP_LDG_NUM count 69 step 8
388	setx LDG_NUM,%g7,%g1
389	setx wdata,%g7,%g2
390	set 64,%g8
391
392	loop12:
393	set 0x05,%g3
394	loop13:
395	ldx [%g2],%g4
396	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
397
398	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
399	setx DATA_EN_6BITS, %g7, %g6
400	and %g4, %g6, %g4
401
402	cmp %g4, %g5
403
404	bne %xcc, test_fail
405
406
407	add %g2,8,%g2
408	sub %g3,1,%g3
409	cmp %g3,%g0
410	bne loop13
411	nop
412	add %g1,8,%g1
413	cmp %g8,%g0
414	bne loop12
415	nop
416
417
418	!Write then read data of IPP_SID count 69 step 8
419	setx SID,%g7,%g1
420	setx wdata,%g7,%g2
421	set 64,%g8
422
423	loop14:
424	set 0x05,%g3
425	loop15:
426	ldx [%g2],%g4
427	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
428
429	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
430	setx DATA_EN_7BITS, %g7, %g6
431	and %g4, %g6, %g4
432
433	cmp %g4, %g5
434
435	bne %xcc, test_fail
436
437
438	add %g2,8,%g2
439	sub %g3,1,%g3
440	cmp %g3,%g0
441	bne loop15
442	nop
443	add %g1,8,%g1
444	cmp %g8,%g0
445	bne loop14
446	nop
447
448	*/
449
450
451
452
453	/******************************************************
454	* Exit code
455	*******************************************************/
456
457	test_pass:
458	EXIT_GOOD
459
460	test_fail:
461	EXIT_BAD
462
463
464	.data
465	.align 0x100
466	wdata:
467	.xword 0xffffffffffffffff
468	.xword 0xaaaaaaaaaaaaaaaa
469	.xword 0x0000000000000000
470	.xword 0x5555555555555555
471	.xword 0x0123456789abcdef
472
473	.end