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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / Bug107906.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: Bug107906.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39!!! #define ENABLE_PCIE_MPS_256 !! comment out so this can be set from command line
40#define MAIN_PAGE_HV_ALSO
41
42#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
43#define DMA_DATA_ADDR 0x0000000052340000
44
45
46#include "hboot.s"
47#include "peu_defines.h"
48# 108 "diag.j.pp"
49.text
50.global main
51
52main:
53 ta T_CHANGE_HPRIV
54 nop
55
56! set the Traffic Class for all the DMA R&W TLPs to 4, so denali doesn't
57! send them out of order
58settc: nop ! $EV trig_pc_d(1, @VA(.MAIN.settc)) -> EnablePCIeIgCmd ("SET_TC", 4, 0, 0, 1 )
59
60 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g2, %g3
61 mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1
62
63LinkTrainingLoop2:
64 ldx [%g3], %g4
65 andcc %l1, %g4, %g5
66 bne LinkTrainingDone2
67 nop
68
69 b LinkTrainingLoop2
70 nop
71
72LinkTrainingDone2:
73 nop
74 nop
75
76 ta %icc, T_RD_THID
77! fork: source strm = 0xffffffffffffffff; target strm = 0x1
78 cmp %o1, 0
79 setx fork_lbl_0_1, %g2, %g3
80 be,a .+8
81 jmp %g3
82 nop
83! fork: source strm = 0xffffffffffffffff; target strm = 0x2
84 cmp %o1, 1
85 setx fork_lbl_0_2, %g2, %g3
86 be,a .+8
87 jmp %g3
88 nop
89! fork: source strm = 0xffffffffffffffff; target strm = 0x4
90 cmp %o1, 2
91 setx fork_lbl_0_3, %g2, %g3
92 be,a .+8
93 jmp %g3
94 nop
95! fork: source strm = 0xffffffffffffffff; target strm = 0x8
96 cmp %o1, 3
97 setx fork_lbl_0_4, %g2, %g3
98 be,a .+8
99 jmp %g3
100 nop
101! fork: source strm = 0xffffffffffffffff; target strm = 0x10
102 cmp %o1, 4
103 setx fork_lbl_0_5, %g2, %g3
104 be,a .+8
105 jmp %g3
106 nop
107! fork: source strm = 0xffffffffffffffff; target strm = 0x20
108 cmp %o1, 5
109 setx fork_lbl_0_6, %g2, %g3
110 be,a .+8
111 jmp %g3
112 nop
113! fork: source strm = 0xffffffffffffffff; target strm = 0x40
114 cmp %o1, 6
115 setx fork_lbl_0_7, %g2, %g3
116 be,a .+8
117 jmp %g3
118 nop
119! fork: source strm = 0xffffffffffffffff; target strm = 0x80
120 cmp %o1, 7
121 setx fork_lbl_0_8, %g2, %g3
122 be,a .+8
123 jmp %g3
124 nop
125.text
126 setx join_lbl_0_0, %g1, %g2
127 jmp %g2
128 nop
129.text
130 setx join_lbl_0_0, %g1, %g2
131 jmp %g2
132 nop
133fork_lbl_0_8:
134
135th7_DMA_read_0: nop
136
137 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h35d", 1)
138
139th7_DMA_read_1: nop
140
141 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h1f7", 1)
142
143th7_DMA_read_2: nop
144
145 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h2dd", 1)
146
147th7_DMA_read_3: nop
148
149 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'he66", 1)
150
151th7_DMA_read_4: nop
152
153 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h7d0", 1)
154
155th7_DMA_read_5: nop
156
157 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h71a", 1)
158
159th7_DMA_read_6: nop
160
161 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h218", 1)
162
163th7_DMA_read_7: nop
164
165 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'he69", 1)
166
167th7_DMA_read_8: nop
168
169 ! $EV trig_pc_d(1, @VA(.MAIN.th7_DMA_read_8)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hbc8", 1)
170 nop
171 nop
172
173 ! select a MEM32 address in PCI address range and transmit the command to NCU
174
175 setx 0x800000c100000c00, %g1, %g2
176 setx 0x080, %g1, %g4 ! loop 48 times
177
178delay_loop7:
179 stx %g2, [%g2] ! MEM32 PIO Write
180 ldx [%g2], %l0 ! MEM32 PIO Read
181 add %g2, 8, %g2 ! increment PIO address
182
183 dec %g4 ! decrement counter
184 brnz %g4, delay_loop7 ! loop if not zero
185 nop
186
187.text
188 setx join_lbl_0_0, %g1, %g2
189 jmp %g2
190 nop
191fork_lbl_0_7:
192
193th6_DMA_read_0: nop
194
195 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h5c9", 1)
196
197th6_DMA_read_1: nop
198
199 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hfbd", 1)
200
201th6_DMA_read_2: nop
202
203 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'ha57", 1)
204
205th6_DMA_read_3: nop
206
207 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'ha8f", 1)
208
209th6_DMA_read_4: nop
210
211 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h612", 1)
212
213th6_DMA_read_5: nop
214
215 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h74c", 1)
216
217th6_DMA_read_6: nop
218
219 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'he1e", 1)
220
221th6_DMA_read_7: nop
222
223 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'ha40", 1)
224
225th6_DMA_read_8: nop
226
227 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_8)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hc54", 1)
228
229th6_DMA_read_9: nop
230
231 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_9)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h11", 1)
232
233th6_DMA_read_10: nop
234
235 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_10)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hcb6", 1)
236
237th6_DMA_read_11: nop
238
239 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_11)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'haa7", 1)
240
241th6_DMA_read_12: nop
242
243 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_12)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h65b", 1)
244
245th6_DMA_read_13: nop
246
247 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_13)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hb93", 1)
248
249th6_DMA_read_14: nop
250
251 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_14)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hf1f", 1)
252
253th6_DMA_read_15: nop
254
255 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_15)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h19c", 1)
256
257th6_DMA_read_16: nop
258
259 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_16)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h6fe", 1)
260
261th6_DMA_read_17: nop
262
263 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_17)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hf21", 1)
264
265th6_DMA_read_18: nop
266
267 ! $EV trig_pc_d(1, @VA(.MAIN.th6_DMA_read_18)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h6d7", 1)
268 nop
269 nop
270
271 ! select a MEM32 address in PCI address range and transmit the command to NCU
272
273 setx 0x800000c100000a00, %g1, %g2
274 setx 0x080, %g1, %g4 ! loop 48 times
275
276delay_loop6:
277 stx %g2, [%g2] ! MEM32 PIO Write
278 ldx [%g2], %l0 ! MEM32 PIO Read
279 add %g2, 8, %g2 ! increment PIO address
280
281 dec %g4 ! decrement counter
282 brnz %g4, delay_loop6 ! loop if not zero
283 nop
284
285.text
286 setx join_lbl_0_0, %g1, %g2
287 jmp %g2
288 nop
289fork_lbl_0_6:
290
291th5_DMA_read_0: nop
292
293 ! $EV trig_pc_d(1, @VA(.MAIN.th5_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h7c8", 1)
294
295th5_DMA_read_1: nop
296
297 ! $EV trig_pc_d(1, @VA(.MAIN.th5_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hec7", 1)
298
299th5_DMA_read_2: nop
300
301 ! $EV trig_pc_d(1, @VA(.MAIN.th5_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hd24", 1)
302
303th5_DMA_read_3: nop
304
305 ! $EV trig_pc_d(1, @VA(.MAIN.th5_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'he0f", 1)
306
307th5_DMA_read_4: nop
308
309 ! $EV trig_pc_d(1, @VA(.MAIN.th5_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h8bc", 1)
310
311th5_DMA_read_5: nop
312
313 ! $EV trig_pc_d(1, @VA(.MAIN.th5_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h645", 1)
314
315th5_DMA_read_6: nop
316
317 ! $EV trig_pc_d(1, @VA(.MAIN.th5_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h6fc", 1)
318
319th5_DMA_read_7: nop
320
321 ! $EV trig_pc_d(1, @VA(.MAIN.th5_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h103", 1)
322 nop
323 nop
324
325 ! select a MEM32 address in PCI address range and transmit the command to NCU
326
327 setx 0x800000c100000800, %g1, %g2
328 setx 0x080, %g1, %g4 ! loop 48 times
329
330delay_loop5:
331 stx %g2, [%g2] ! MEM32 PIO Write
332 ldx [%g2], %l0 ! MEM32 PIO Read
333 add %g2, 8, %g2 ! increment PIO address
334
335 dec %g4 ! decrement counter
336 brnz %g4, delay_loop5 ! loop if not zero
337 nop
338
339.text
340 setx join_lbl_0_0, %g1, %g2
341 jmp %g2
342 nop
343fork_lbl_0_5:
344
345th4_DMA_read_0: nop
346
347 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hba3", 1)
348
349th4_DMA_read_1: nop
350
351 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h97b", 1)
352
353th4_DMA_read_2: nop
354
355 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hb4c", 1)
356
357th4_DMA_read_3: nop
358
359 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hb9c", 1)
360
361th4_DMA_read_4: nop
362
363 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h986", 1)
364
365th4_DMA_read_5: nop
366
367 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h904", 1)
368
369th4_DMA_read_6: nop
370
371 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hcc9", 1)
372
373th4_DMA_read_7: nop
374
375 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h204", 1)
376
377th4_DMA_read_8: nop
378
379 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_8)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hca9", 1)
380
381th4_DMA_read_9: nop
382
383 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_9)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hd9d", 1)
384
385th4_DMA_read_10: nop
386
387 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_10)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hfd2", 1)
388
389th4_DMA_read_11: nop
390
391 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_11)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h919", 1)
392
393th4_DMA_read_12: nop
394
395 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_12)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h764", 1)
396
397th4_DMA_read_13: nop
398
399 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_13)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hdcf", 1)
400
401th4_DMA_read_14: nop
402
403 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_14)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hae2", 1)
404
405th4_DMA_read_15: nop
406
407 ! $EV trig_pc_d(1, @VA(.MAIN.th4_DMA_read_15)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hbce", 1)
408 nop
409 nop
410
411 ! select a MEM32 address in PCI address range and transmit the command to NCU
412
413 setx 0x800000c100000600, %g1, %g2
414 setx 0x080, %g1, %g4 ! loop 48 times
415
416delay_loop4:
417 stx %g2, [%g2] ! MEM32 PIO Write
418 ldx [%g2], %l0 ! MEM32 PIO Read
419 add %g2, 8, %g2 ! increment PIO address
420
421 dec %g4 ! decrement counter
422 brnz %g4, delay_loop4 ! loop if not zero
423 nop
424
425.text
426 setx join_lbl_0_0, %g1, %g2
427 jmp %g2
428 nop
429fork_lbl_0_4:
430
431th3_DMA_read_0: nop
432
433 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h285", 1)
434
435th3_DMA_read_1: nop
436
437 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hfd7", 1)
438
439th3_DMA_read_2: nop
440
441 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hf16", 1)
442
443th3_DMA_read_3: nop
444
445 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hc3f", 1)
446
447th3_DMA_read_4: nop
448
449 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h7aa", 1)
450
451th3_DMA_read_5: nop
452
453 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hd7b", 1)
454
455th3_DMA_read_6: nop
456
457 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'haf3", 1)
458
459th3_DMA_read_7: nop
460
461 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h601", 1)
462
463th3_DMA_read_8: nop
464
465 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_8)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hb2d", 1)
466
467th3_DMA_read_9: nop
468
469 ! $EV trig_pc_d(1, @VA(.MAIN.th3_DMA_read_9)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h817", 1)
470 nop
471 nop
472
473 ! select a MEM32 address in PCI address range and transmit the command to NCU
474
475 setx 0x800000c100000400, %g1, %g2
476 setx 0x080, %g1, %g4 ! loop 48 times
477
478delay_loop3:
479 stx %g2, [%g2] ! MEM32 PIO Write
480 ldx [%g2], %l0 ! MEM32 PIO READ
481 add %g2, 8, %g2 ! increment PIO address
482# 206 "diag.j.pp"
483 dec %g4 ! decrement counter
484 brnz %g4, delay_loop3 ! loop if not zero
485 nop
486
487.text
488 setx join_lbl_0_0, %g1, %g2
489 jmp %g2
490 nop
491fork_lbl_0_3:
492
493th2_DMA_read_0: nop
494
495 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h787", 1)
496
497th2_DMA_read_1: nop
498
499 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h2fd", 1)
500
501th2_DMA_read_2: nop
502
503 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hcd8", 1)
504
505th2_DMA_read_3: nop
506
507 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h80f", 1)
508
509th2_DMA_read_4: nop
510
511 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h594", 1)
512
513th2_DMA_read_5: nop
514
515 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hed5", 1)
516
517th2_DMA_read_6: nop
518
519 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h3c3", 1)
520
521th2_DMA_read_7: nop
522
523 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hbfd", 1)
524
525th2_DMA_read_8: nop
526
527 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_8)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h802", 1)
528
529th2_DMA_read_9: nop
530
531 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_9)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h6b3", 1)
532
533th2_DMA_read_10: nop
534
535 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_10)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hd5b", 1)
536
537th2_DMA_read_11: nop
538
539 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_11)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h605", 1)
540
541th2_DMA_read_12: nop
542
543 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_12)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hfb4", 1)
544
545th2_DMA_read_13: nop
546
547 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_13)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h37b", 1)
548
549th2_DMA_read_14: nop
550
551 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_14)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hbab", 1)
552
553th2_DMA_read_15: nop
554
555 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_15)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h72d", 1)
556
557th2_DMA_read_16: nop
558
559 ! $EV trig_pc_d(1, @VA(.MAIN.th2_DMA_read_16)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h81f", 1)
560 nop
561 nop
562
563 ! select a MEM32 address in PCI address range and transmit the command to NCU
564
565 setx 0x800000c100000200, %g1, %g6
566 setx 0x080, %g1, %g7 ! loop 48 times
567
568delay_loop2:
569 stx %g6, [%g6] ! MEM32 PIO Write
570 ldx [%g6], %l0 ! MEM32 PIO Read
571 add %g6, 8, %g6 ! increment PIO address
572# 185 "diag.j.pp"
573 dec %g7 ! decrement counter
574 brnz %g7, delay_loop2 ! loop if not zero
575 nop
576
577.text
578 setx join_lbl_0_0, %g1, %g2
579 jmp %g2
580 nop
581fork_lbl_0_2:
582
583th1_DMA_read_0: nop
584
585 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h284", 1)
586
587th1_DMA_read_1: nop
588
589 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hc72", 1)
590
591th1_DMA_read_2: nop
592
593 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'he36", 1)
594
595th1_DMA_read_3: nop
596
597 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hd32", 1)
598
599th1_DMA_read_4: nop
600
601 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h20a", 1)
602
603th1_DMA_read_5: nop
604
605 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h10a", 1)
606
607th1_DMA_read_6: nop
608
609 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h918", 1)
610
611th1_DMA_read_7: nop
612
613 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h544", 1)
614
615th1_DMA_read_8: nop
616
617 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_8)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hc0e", 1)
618
619th1_DMA_read_9: nop
620
621 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_9)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hbc0", 1)
622
623th1_DMA_read_10: nop
624
625 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_10)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hdfb", 1)
626
627th1_DMA_read_11: nop
628
629 ! $EV trig_pc_d(1, @VA(.MAIN.th1_DMA_read_11)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h32e", 1)
630 nop
631 nop
632
633 ! select a MEM32 address in PCI address range and transmit the command to NCU
634
635 setx MEM32_RD_ADDR, %g1, %g3
636 setx 0x080, %g1, %g5 ! loop 48 times
637
638delay_loop1:
639 stx %g3, [%g3] ! MEM32 PIO Write
640 ldx [%g3], %l0 ! MEM32 PIO Read
641 add %g3, 8, %g3 ! increment PIO address
642# 164 "diag.j.pp"
643 dec %g5 ! decrement counter
644 brnz %g5, delay_loop1 ! loop if not zero
645 nop
646
647.text
648 setx join_lbl_0_0, %g1, %g2
649 jmp %g2
650 nop
651fork_lbl_0_1:
652
653DMA_ldst_0: nop
654
655th0_DMA_read_0: nop
656
657 ! $EV trig_pc_d(1, @VA(.MAIN.th0_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hb12", 1)
658
659th0_DMA_read_1: nop
660
661 ! $EV trig_pc_d(1, @VA(.MAIN.th0_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h7d8", 1)
662
663th0_DMA_read_2: nop
664
665 ! $EV trig_pc_d(1, @VA(.MAIN.th0_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h7f0", 1)
666
667th0_DMA_read_3: nop
668
669 ! $EV trig_pc_d(1, @VA(.MAIN.th0_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h97c", 1)
670
671th0_DMA_read_4: nop
672
673 ! $EV trig_pc_d(1, @VA(.MAIN.th0_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'hb60", 1)
674
675th0_DMA_read_5: nop
676
677 ! $EV trig_pc_d(1, @VA(.MAIN.th0_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'heb0", 1)
678
679th0_DMA_read_6: nop
680
681 ! $EV trig_pc_d(1, @VA(.MAIN.th0_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'h1bf", 1)
682
683th0_DMA_read_7: nop
684
685 ! $EV trig_pc_d(1, @VA(.MAIN.th0_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000052340000,fffc000052350000, "64'he0c", 1)
686 nop
687 nop
688
689 ! select a MEM32 address in PCI address range and transmit the command to NCU
690
691 setx 0x800000c100000e00, %g1, %g2
692 setx 0x080, %g1, %g4 ! loop 128 times
693
694delay_loop:
695 stx %g2, [%g2] ! MEM32 PIO Write
696 ldx [%g2], %l0 ! MEM32 PIO Read
697 add %g2, 8, %g2 ! increment PIO address
698
699 dec %g4 ! decrement counter
700 brnz %g4, delay_loop ! loop if not zero
701 nop
702
703
704join_lbl_0_0:
705
706pcie_test_passed:
707 EXIT_GOOD
708
709pcie_test_failed:
710 EXIT_BAD
711
712SECTION descriptor data_va=DMA_DATA_ADDR
713attr_data {
714 Name = descriptor,
715 hypervisor,
716 compressimage
717}
718
719.data
720init_mem(0x0101010201030104, 1024*8, 8, +, 0, +, 0x0004000400040004)
721# 416 "diag.j.pp"
722
723#if 0
724#endif
725
726
Full OpenSPARC design & verification tarball including full HDL.