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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: PCIDMAEptWrRd.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | #define DBG_CONFIG_PA 0x8600000000 | |
40 | #define DBG_REPEAT_VAL 0x8000000000000005 | |
41 | ||
42 | #ifndef DMAEPTADDR | |
43 | #define DMAEPTADDR 0xfffc00000abc1014 | |
44 | #endif | |
45 | ||
46 | #ifndef DMAEPTCNT | |
47 | #define DMAEPTCNT 0x14 | |
48 | #endif | |
49 | ||
50 | #ifndef DMAEPTPYLD | |
51 | #define DMAEPTPYLD 0x80 | |
52 | #endif | |
53 | ||
54 | ! Pick a value that pauses some, but not for the full duration of | |
55 | ! the operation. I think the value below is about one quarter of | |
56 | ! the full operation with four engines running. | |
57 | #ifndef DMAEPTPAUSE | |
58 | #define DMAEPTPAUSE ((DMAEPTCNT*4)/4) | |
59 | #endif | |
60 | ||
61 | #ifndef DMAEPTENGCNT | |
62 | #define DMAEPTENGCNT 1 | |
63 | #endif | |
64 | ||
65 | #define DMAEPTMWTO ((DMAEPTCNT/0x500)*DMAEPTENGCNT)+2 | |
66 | #define DMAEPTMRTO (DMAEPTCNT/0x140)+2 | |
67 | ||
68 | #include "hboot.s" | |
69 | #include "pep_util.s" | |
70 | ||
71 | /************************************************************************ | |
72 | Test case code start | |
73 | ************************************************************************/ | |
74 | .text | |
75 | .global main | |
76 | ||
77 | main: | |
78 | ta T_CHANGE_HPRIV | |
79 | nop | |
80 | ||
81 | ! Turn on the N2 Debug port, setting it to | |
82 | ! repeatability mode. | |
83 | setx DBG_CONFIG_PA,%g1,%g2 | |
84 | setx DBG_REPEAT_VAL,%g3,%g4 | |
85 | !stx %g4,[%g2] | |
86 | ||
87 | thread_0: | |
88 | ! | |
89 | ! Thread 0 Start | |
90 | ! | |
91 | ||
92 | ! Setup an operation in the engines, using from one | |
93 | ! to all four. This sets up everthing other than the | |
94 | ! operation code and count. | |
95 | setx DMAEPTENGCNT, %l0, %l1 ! Initial engine number | |
96 | Setup: | |
97 | setx DMAEPTADDR, %l0, %o1 | |
98 | ! Insert Engine number in bits 31:28 of addr | |
99 | sll %l1, 28, %l5 | |
100 | or %l5, %o1, %o1 | |
101 | setx 0x6990, %l0, %o2 | |
102 | or %l1, %o2, %o2 ! Insert engine num into pattern | |
103 | setx 0x50000, %l0, %o3 ! Generate MSI at the end | |
104 | setx DMAEPTPYLD, %l0, %o4 ! Max packet size, 512 bytes | |
105 | call SetupDMA | |
106 | mov %l1, %o0 ! Engine number | |
107 | ||
108 | ! Setup operation on next engine? | |
109 | dec %l1 | |
110 | brnz %l1, Setup | |
111 | nop | |
112 | ||
113 | ! Now start each engine to do an MW | |
114 | setx DMAEPTENGCNT, %l0, %l1 ! Initial engine number | |
115 | setx 0x02000000 + DMAEPTCNT, %l0, %o1 ! MW by device | |
116 | StartMW: | |
117 | call InitiateDMA | |
118 | mov %l1, %o0 ! Engine number | |
119 | ||
120 | ! Start next engine? | |
121 | dec %l1 | |
122 | brnz %l1, StartMW | |
123 | nop | |
124 | ||
125 | ! Pause long enough for operation to | |
126 | ! make some progress before blasting | |
127 | ! it with PIOs. | |
128 | rd %tick, %l1 | |
129 | setx DMAEPTPAUSE, %l0, %l2 | |
130 | add %l1, %l2, %l1 | |
131 | PauseMW: | |
132 | rd %tick, %l2 | |
133 | cmp %l1, %l2 | |
134 | bpos PauseMW | |
135 | nop | |
136 | ||
137 | ! Now wait for each engine to finish | |
138 | setx DMAEPTENGCNT, %l0, %l1 ! Initial engine number | |
139 | setx DMAEPTMWTO, %l0, %o1 | |
140 | WaitMW: ! Scale MW wait time by number of engines | |
141 | call WaitOnDMA | |
142 | mov %l1, %o0 ! Engine number | |
143 | brnz %o0, test_failed | |
144 | ||
145 | ! Wait on next engine? | |
146 | dec %l1 | |
147 | brnz %l1, WaitMW | |
148 | nop | |
149 | ||
150 | setx DMAEPTENGCNT, %l0, %l1 ! Initial engine number | |
151 | SetupMR: | |
152 | setx DMAEPTADDR, %l0, %o1 | |
153 | ! Insert Engine number in bits 31:28 of addr | |
154 | sll %l1, 28, %l5 | |
155 | or %l5, %o1, %o1 | |
156 | setx 0x6990, %l0, %o2 | |
157 | or %l1, %o2, %o2 ! Insert engine num into pattern | |
158 | setx 0x50000, %l0, %o3 ! Generate MSI at the end | |
159 | setx 0x200, %l0, %o4 ! 2K requests | |
160 | call SetupDMA | |
161 | mov %l1, %o0 ! Engine number | |
162 | ||
163 | ! Setup operation on next engine? | |
164 | dec %l1 | |
165 | brnz %l1, SetupMR | |
166 | nop | |
167 | ||
168 | ! Now start each engine doing an MR to same memory area | |
169 | setx DMAEPTENGCNT, %l0, %l1 ! Initial engine number | |
170 | setx 0x01000000 + DMAEPTCNT, %l0, %o1 ! MR by device | |
171 | StartMR: ! Scale MW wait time by number of engines | |
172 | call InitiateDMA | |
173 | mov %l1, %o0 ! Engine number | |
174 | ||
175 | ! Start next engine? | |
176 | dec %l1 | |
177 | brnz %l1, StartMR | |
178 | nop | |
179 | ||
180 | ! Pause long enough for operation to | |
181 | ! make some progress before blasting | |
182 | ! it with PIOs. | |
183 | rd %tick, %l1 | |
184 | setx DMAEPTPAUSE, %l0, %l2 | |
185 | add %l1, %l2, %l1 | |
186 | PauseMR: | |
187 | rd %tick, %l2 | |
188 | cmp %l1, %l2 | |
189 | bpos PauseMR | |
190 | nop | |
191 | ||
192 | ! Wait for each engine to finish the MR | |
193 | ! MR wait time is function of DRAM latency, | |
194 | ! not number of engines active. | |
195 | setx DMAEPTENGCNT, %l0, %l1 ! Initial engine number | |
196 | setx DMAEPTMRTO, %l0, %o1 | |
197 | WaitMR: | |
198 | call WaitOnDMA | |
199 | mov %l1, %o0 ! Engine number | |
200 | brnz %o0, test_failed | |
201 | ||
202 | ! Wait on next engine? | |
203 | dec %l1 | |
204 | brnz %l1, WaitMR | |
205 | nop | |
206 | ||
207 | test_passed: | |
208 | EXIT_GOOD | |
209 | nop | |
210 | ||
211 | test_failed: | |
212 | EXIT_BAD | |
213 | nop |