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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeDMARdAdr64.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeDMARdAdr64.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39#define ENABLE_PCIE_MPS_512
40#define MAIN_PAGE_HV_ALSO
41
42#include "hboot.s"
43#include "peu_defines.h"
44
45#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
46
47#define DMA_DATA_ADDR 0x0000000123456700
48#define DMA_DATA_BYP_ADDR mpeval(IOMMU_BYP_SADDR + DMA_DATA_ADDR)
49
50!!#define DMA_ADDR_1 mpeval(DMA_DATA_ADDR + 0*256, 16, 16)
51!!#define DMA_ADDR_2 mpeval(DMA_DATA_ADDR + 1*256, 16, 16)
52
53#define DMA_ADDR_1 mpeval(DMA_DATA_BYP_ADDR + 0*256, 16, 16)
54#define DMA_ADDR_2 mpeval(DMA_DATA_BYP_ADDR + 1*256, 16, 16)
55
56
57/************************************************************************
58 Test case code start
59 ************************************************************************/
60.text
61.global main
62
63main:
64 ta T_CHANGE_HPRIV
65 nop
66
67 ! enable bypass in IOMMU
68 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
69 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
70 stx %g3, [%g2]
71 ldx [%g2], %g3
72
73! Trigger some DMA Reads of various lengths
74
75Xmt1: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt1)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1", 1 )
76 nop
77 nop
78Xmt2: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt2)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2", 1 )
79 nop
80 nop
81Xmt3: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt3)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h3", 1 )
82 nop
83 nop
84Xmt4: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt4)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h4", 1 )
85 nop
86 nop
87Xmt5: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt5)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h3f", 1 )
88 nop
89 nop
90Xmt6: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt6)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h40", 1 )
91 nop
92 nop
93Xmt7: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt7)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h41", 1 )
94 nop
95 nop
96Xmt8: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt8)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h7f", 1 )
97 nop
98 nop
99Xmt9: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt9)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h80", 1 )
100 nop
101 nop
102Xmt10: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt10)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h81", 1 )
103 nop
104 nop
105Xmt11: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt11)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'hff", 1 )
106 nop
107 nop
108Xmt12: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt12)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h100", 1 )
109 nop
110 nop
111Xmt13: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt13)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h101", 1 )
112 nop
113 nop
114Xmt14: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt14)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1ff", 1 )
115 nop
116 nop
117Xmt15: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt15)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h200", 1 )
118 nop
119 nop
120Xmt16: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt16)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h400", 1 )
121 nop
122 nop
123Xmt17: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt17)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h800", 1 )
124 nop
125 nop
126Xmt18: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt18)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1000", 1 )
127 nop
128 nop
129
130 ! select a MEM32 address in PCI address range and transmit the command to NCU
131
132 setx MEM32_RD_ADDR, %g1, %g2
133 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
134 setx 0x020, %g1, %g4 ! loop 32 times
135
136delay_loop:
137 ldx [%g3], %l1 ! PIU CSR READ
138 !!stx %g2, [%g2] ! MEM32 PIO Write
139 !!ldx [%g2], %l0 ! MEM32 PIO READ
140 add %g2, 8, %g2 ! increment PIO address
141
142 dec %g4 ! decrement counter
143 brnz %g4, delay_loop ! loop if not zero
144 nop
145
146
147test_passed:
148 EXIT_GOOD
149
150test_failed:
151 EXIT_BAD
152
153
154/************************************************************************
155 Test case data start
156************************************************************************/
157
158SECTION .DATA DATA_VA=DMA_DATA_ADDR
159attr_data {
160 Name = .DATA,
161 hypervisor,
162 compressimage
163}
164.data
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Full OpenSPARC design & verification tarball including full HDL.