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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeDMARdLk.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeDMARdLk.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#ifndef DTM_ENABLED
39#define ENABLE_PCIE_LINK_TRAINING
40#define SKIP_PCIE_LINK_WAIT
41#endif
42
43#define MAIN_PAGE_HV_ALSO
44
45#define H_HT0_Interrupt_0x60
46#define My_HT0_Interrupt_0x60 \
47 call piu_trap_code; \
48 nop; \
49 retry; \
50 nop;
51
52#include "hboot.s"
53#include "peu_defines.h"
54#include "ncu_defines.h"
55#include "cmp_macros.h"
56
57#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
58
59#define DMA_DATA_ADDR 0x0000000123456600
60#define DMA_DATA_BYP_SADDR 0xfffc000123456600
61#define DMA_DATA_BYP_EADDR 0xfffc000123456800
62
63#define DMA_DATA_ADDR32 0x00000000007f0000
64
65#define IOMMU_TTE_ADDR 0x0000000040000000
66
67! Bit 8 = Page Size: 0=8KB, 1=64KB; Bits 3:0 = TSB Table size: 6=64k entries
68#define MMU_TSB_CNTRL_REG_DATA mpeval(IOMMU_TTE_ADDR | 0x100 | 6)
69
70#define MEM_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
71
72/************************************************************************
73 Test case code start
74 ************************************************************************/
75.text
76.global main
77
78main:
79 ta T_CHANGE_HPRIV
80 nop
81
82th_fork(th_main, %l0)
83
84/*************************************************************************
85 Thread 0 will test mem 64 pios
86 *************************************************************************/
87th_main_0:
88
89! enable SUN4U translation in the IOMMU
90
91 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
92 setx 0x00303, %g1, %g3 ! 9:8 11 = Cache enabled, 0: 1 = translation enabled
93 stx %g3, [%g2]
94 ldx [%g2], %g3
95
96! load address of the TSB table, and the page size (64KB)
97
98 setx FIRE_DLC_MMU_CSR_A_TSB_ADDR, %g1, %g2
99 setx MMU_TSB_CNTRL_REG_DATA, %g1, %g3
100 stx %g3, [%g2]
101 ldx [%g2], %g3
102
103#ifndef DTM_ENABLED
104! wait here until pcie link training is done, then start other threads
105 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g2
106 mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %g1
107 mov 100, %g3
108
109PcieLinkTrainingLoop:
110 ldx [%g2], %g4
111 andcc %g1, %g4, %g4
112 bne LinkTrainingDone
113
114 dec %g3
115 brnz %g3, PcieLinkTrainingLoop
116 nop
117
118LinkTrainingTimeout:
119 ta T_BAD_TRAP
120 nop
121
122LinkTrainingDone:
123#endif
124! enable interrupts & provide basic handler
125#include "piu_rupt_enable.s"
126
127 !setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
128 !setx 0x0000003e0000003e, %g1, %g3
129 !ldx [%g2], %g4
130 !andn %g4, %g3, %g4
131 !stx %g4, [%g2] ! turn off interupts for error messages
132
133 /* Sync up all the treads. */
134
135#ifndef PORTABLE_CORE
136sync_t0:
137 SYNC_THREAD_MAIN( test_failed, %g1, %g2, %g3 )
138#else
139 cmp_sync_threads
140#endif
141
142
143DMARD1: nop;nop;nop;nop;
144 nop;nop;nop;nop;
145! $EV trig_pc_d(1,@VA(.MAIN.DMARD1)) -> EnablePCIeIgCmd("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h100",1)
146
147DMARDLK:nop;nop;nop;nop;
148 nop;nop;nop;nop;
149! $EV trig_pc_d(1,@VA(.MAIN.DMARDLK)) -> EnablePCIeIgCmd("DMARDLK", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_EADDR, "64'h80",1)
150
151
152ERR_COR: nop;nop;nop;nop;
153! $EV trig_pc_d(1,@VA(.MAIN.ERR_COR)) -> EnablePCIeIgCmd("ERR_COR", 0, 0, "64'h10",1)
154 setx err_cor_int_cnt,%g1,%o0
155 best_set_reg(100, %g1, %o2)
156 setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %o3 ! 631000
157
158err_cor_delay:
159 ldx [%o3+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
160 ldx [%o0], %o1
161 cmp %o1, 0
162 bne ERR_NONFATAL
163 nop
164 dec %o2
165 cmp %o2, 0
166 bne err_cor_delay
167 nop
168 !ba test_failed
169 nop
170
171ERR_NONFATAL: nop;nop;nop;nop;
172! $EV trig_pc_d(1,@VA(.MAIN.ERR_NONFATAL)) -> EnablePCIeIgCmd("ERR_NONFATAL", 0, 0, "64'h10",1)
173 setx err_nonfatal_int_cnt,%g1,%o0
174 best_set_reg(100, %g1, %o2)
175
176err_nonfatal_delay:
177 ldx [%o3+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
178 ldx [%o0], %o1
179 cmp %o1, 0
180 bne ERR_FATAL
181 nop
182 dec %o2
183 cmp %o2, 0
184 bne err_nonfatal_delay
185 nop
186 !ba test_failed
187 nop
188
189
190ERR_FATAL: nop;nop;nop;nop;
191! $EV trig_pc_d(1,@VA(.MAIN.ERR_FATAL)) -> EnablePCIeIgCmd("ERR_FATAL", 0, 0, "64'h10",1)
192 setx err_fatal_int_cnt,%g1,%o0
193 best_set_reg(100, %g1, %o2)
194
195err_fatal_delay:
196 ldx [%o3+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
197 ldx [%o0], %o1
198 cmp %o1, 0
199 bne ATTN
200 nop
201 dec %o2
202 cmp %o2, 0
203 bne err_fatal_delay
204 nop
205 !ba test_failed
206 nop
207
208
209ATTN: nop;nop;nop;nop;
210 nop;nop;nop;nop;
211! $EV trig_pc_d(1,@VA(.MAIN.ATTN)) -> EnablePCIeIgCmd("ATTN", 0, 0, "64'h10",1)
212
213VENDOR_TYPE_0: nop;nop;nop;nop;
214 nop;nop;nop;nop;
215! $EV trig_pc_d(1,@VA(.MAIN.VENDOR_TYPE_0)) -> EnablePCIeIgCmd("VENDOR_TYPE_0", 0, 0, "64'h10",1)
216
217VENDOR_TYPE_1: nop;nop;nop;nop;
218 nop;nop;nop;nop;
219! $EV trig_pc_d(1,@VA(.MAIN.VENDOR_TYPE_1)) -> EnablePCIeIgCmd("VENDOR_TYPE_1", 0, 0, "64'h10",1)
220
221DMARDLK2:nop;nop;nop;nop;
222 nop;nop;nop;nop;
223! $EV trig_pc_d(1,@VA(.MAIN.DMARDLK2)) -> EnablePCIeIgCmd("DMARDLK", DMA_DATA_ADDR32, DMA_DATA_ADDR32, "64'h44",1)
224
225
226DMARD2: nop;nop;nop;nop;
227 nop;nop;nop;nop;
228! $EV trig_pc_d(1,@VA(.MAIN.DMARD2)) -> EnablePCIeIgCmd("DMARD_INTA", DMA_DATA_ADDR32, DMA_DATA_ADDR32, "64'h40",1)
229
230
231 !!! Wait for the INTA following the last DMA Read completion
232 setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2
233 mov 100, %g3 ! loop count
234 mov 8, %g4 ! INTA asserted bit
235
236delay_loop1:
237 ldx [%g2], %g5
238 cmp %g4,%g5
239 be test_passed
240
241 dec %g3
242 cmp %g3, 0
243 bne delay_loop1
244 nop
245
246test_failed:
247 EXIT_BAD
248
249
250
251th_main_1:
252th_main_2:
253th_main_3:
254th_main_6:
255th_main_7:
256
257
258#ifndef PORTABLE_CORE
259 SYNC_THREAD_OTHER( %o1,%g1,%g2 )
260#else
261 cmp_sync_threads
262#endif
263
264test_passed:
265 EXIT_GOOD
266
267
268
269 .align 64
270/*************************************************************************
271 Thread 4 will cycle thru the imu perf cntr a selects
272 *************************************************************************/
273th_main_4:
274
275#ifndef PORTABLE_CORE
276 SYNC_THREAD_OTHER( %o1,%g1,%g2 )
277#else
278 cmp_sync_threads
279#endif
280
281
282 setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR, %g1, %g2
283 best_set_reg(0xff00, %g1, %g3) ! Mask to zero cntr 0 select
284 setx imu_cntr_values, %g1, %g4 ! valid cntr 0 select values
285 ldub [%g4], %l0 ! get new cntr 0 select value
286
287 setx MEM_RD_ADDR, %g1, %l1
288 setx imu_cntr_select_lock, %g1, %l2
289
290imu_cntr0_loop:
291 ! get the counter lock
292 ldstub [%l2], %l3
293 cmp %l3, 0
294 bne imu_cntr0_loop
295
296 ! store the new cntr 0 select value
297 ldx [%g2], %g5
298 and %g5, %g3, %g5
299 or %g5, %l0, %g5
300 stx %g5, [%g2]
301
302 ! free the counter lock
303 st %g0, [%l2]
304
305 ! wait a bit, then load the cntr and write to pio location
306 setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_ADDR, %g1, %g7
307 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
308 ldx [%g7], %g5
309 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
310 ldx [%g7], %g5
311 stx %g5, [%l1] ! write perf cntr 0 value onto pcie bus
312
313 ! incr cntr 0 select value & exit if done
314 inc %g4
315 ldub [%g4], %l0 ! get new cntr 0 select value
316 cmp %l0, 0xff
317 be test_passed
318 nop
319
320 ba imu_cntr0_loop
321 nop
322
323 .align 64
324imu_cntr_values:
325 .xword 0x0102030405060102
326 .xword 0x03040506ffffffff
327
328imu_cntr_select_lock:
329 .xword 0x0000000000000000
330
331/************************************************************************
332 Cycle thru the IMU performance counter 1 selects
333 ************************************************************************/
334 .align 64
335th_main_5:
336
337#ifndef PORTABLE_CORE
338 SYNC_THREAD_OTHER( %o1,%g1,%g2 )
339#else
340 cmp_sync_threads
341#endif
342
343 setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR, %g1, %g2
344 best_set_reg(0x00ff, %g1, %g3) ! Mask to zero cntr 1 select
345 setx imu_cntr_values, %g1, %g4 ! valid cntr 1 select values
346 ldub [%g4], %l0 ! get new cntr 1 select value
347 sll %l0, 8, %l0
348
349 setx MEM_RD_ADDR, %g1, %l1
350 setx imu_cntr_select_lock, %g1, %l2
351
352imu_cntr1_loop:
353 ! get the counter lock
354 ldstub [%l2], %l3
355 cmp %l3, 0
356 bne imu_cntr1_loop
357
358 ! store the new cntr 1 select value
359 ldx [%g2], %g5
360 and %g5, %g3, %g5
361 or %g5, %l0, %g5
362 stx %g5, [%g2]
363
364 ! free the counter lock
365 st %g0, [%l2]
366
367 ! wait a bit, then load the cntr and write to pio location
368 setx FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_ADDR, %g1, %g7
369 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
370 ldx [%g7], %g5
371 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
372 ldx [%g7], %g5
373 stx %g5, [%l1 + 16] ! write perf cntr 1 value onto pcie bus
374
375 ! incr cntr 1 select value & exit if done
376 inc %g4
377 ldub [%g4], %l0 ! get new cntr 1 select value
378 cmp %l0, 0xff
379 be test_passed
380 sll %l0, 8, %l0
381
382 ba imu_cntr1_loop
383 nop
384
385/************************************************************************
386 Interrupt Handler
387 ************************************************************************/
388 .align 64
389.global piu_trap_code
390piu_trap_code:
391 best_set_reg(MONDO_INT_ADATA0, %g4, %g3)
392 ldx [%g3], %g3
393 and %g3, 0x3f, %g3 /* WIP: Mask to get INO */
394
395 cmp %g3, 62
396 be mondo_62_handler
397 nop
398
399 cmp %g3, 63
400 be mondo_63_handler
401 nop
402
403 ba test_failed ! if neither, must be an error
404
405 ! read DMU error status registers
406mondo_62_handler:
407 setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %g3 ! 631000
408 ldx [%g3+0x808], %l7 ! 631808 - DMU Core and Block Error Status Reg
409 cmp %l7, 1 ! test if the IMU has an interrupt
410 be rd_imu_error_regs
411
412 cmp %l7, 2 ! test if the MMU has an interrupt
413 be rd_mmu_error_regs
414 nop
415
416 ba test_failed ! if 0, must be an error
417
418
419rd_imu_error_regs:
420 ldx [%g3+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
421 cmp %l3, 2 ! check for Correctable Err Message
422 bne not_err_cor
423 nop
424 setx err_cor_int_cnt,%g1,%l4
425 ldx [%l4], %l5
426 inc %l5
427 stx %l5, [%l4]
428 stx %l3, [%g3+0x18] ! clear error bit
429 ldx [%g3+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
430 cmp %l3, 0 ! check that error bit is cleared
431 be trap_done
432 nop
433 ba test_failed
434 nop
435
436not_err_cor:
437 cmp %l3, 4 ! check for Nonfatal Err Message
438 bne not_err_nonfatal
439 nop
440 setx err_nonfatal_int_cnt,%g1,%l4
441 ldx [%l4], %l5
442 inc %l5
443 stx %l5, [%l4]
444 stx %l3, [%g3+0x18] ! clear error bit
445 ldx [%g3+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
446 cmp %l3, 0 ! check that error bit is cleared
447 be trap_done
448 nop
449 ba test_failed
450 nop
451
452not_err_nonfatal:
453 cmp %l3, 8 ! check for Fatal Err Message
454 bne test_failed
455 nop
456 setx err_fatal_int_cnt,%g1,%l4
457 ldx [%l4], %l5
458 inc %l5
459 stx %l5, [%l4]
460 stx %l3, [%g3+0x18] ! clear error bit
461 ldx [%g3+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
462 cmp %l3, 0 ! check that error bit is cleared
463 be trap_done
464 nop
465 ba test_failed
466 nop
467
468
469
470rd_mmu_error_regs:
471 setx FIRE_DLC_MMU_CSR_A_LOG_ADDR, %g1, %g2 ! 641000
472 ldx [%g2+0x10], %l0 ! 641010 - MMU Interrupt Status Reg
473 ldx [%g2+0x28], %l1 ! 641028 - MMU Translation Fault Address Reg
474 ldx [%g2+0x30], %l2 ! 641030 - MMU Translation Fault Status Reg
475 b test_failed ! No errors expected - go to bad trap
476 nop
477
478 ! read PEU error status registers
479mondo_63_handler:
480 setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR, %g1, %g3 ! 651000
481 ldx [%g3+0x808], %l7 ! 651808 - PEU Core and Block Interrupt Status Reg
482 cmp %l7, 0
483 bz test_failed ! one of the bits should have been set
484
485 and %l7, 0x8, %g4 ! test if the ILU has an interrupt
486 cmp %g4, 0
487 bnz rd_ilu_error_regs
488
489 and %l7, 0x4, %g4 ! test if its an Uncorrectable error from PEU
490 cmp %g4, 0
491 bnz rd_ue_error_regs
492
493 and %l7, 0x2, %g4 ! test if its a Correctable error from PEU
494 cmp %g4, 0
495 bnz rd_ce_error_regs
496 nop
497
498rd_oe_error_regs:
499 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR, %g1, %g3 ! 681000
500 ldx [%g3+0x10], %l0 ! 681010 - PEU OE Status Reg
501 and %l0, 0x800, %l1 ! test if its a Correctable error from PEU
502 cmp %l1, 0
503 bnz rd_dlpl_error_regs
504 nop
505 ldx [%g2+0x28], %l1 ! 681028 - PEU OE Rx Hdr1 Log Reg
506 ldx [%g2+0x30], %l2 ! 681030 - PEU OE Rx Hdr2 Log Reg
507 ldx [%g2+0x38], %l3 ! 681038 - PEU OE Tx Hdr1 Log Reg
508 ldx [%g2+0x40], %l4 ! 681040 - PEU OE Tx Hdr2 Log Reg
509 b test_failed ! No errors expected - go to bad trap
510 nop
511
512rd_ue_error_regs:
513 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR, %g1, %g3 ! 691000
514 ldx [%g3+0x10], %l0 ! 691010 - PEU UE Status Reg
515 ldx [%g2+0x28], %l1 ! 691028 - PEU UE Rx Hdr1 Log Reg
516 ldx [%g2+0x30], %l2 ! 691030 - PEU UE Rx Hdr2 Log Reg
517 ldx [%g2+0x38], %l3 ! 691038 - PEU UE Tx Hdr1 Log Reg
518 ldx [%g2+0x40], %l4 ! 691040 - PEU UE Tx Hdr2 Log Reg
519 b test_failed ! No errors expected - go to bad trap
520 nop
521
522rd_ce_error_regs:
523 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR, %g1, %g3 ! 6a1000
524 ldx [%g3+0x10], %l0 ! 6a1010 - PEU CE Status Reg
525 b test_failed ! No errors expected - go to bad trap
526 nop
527
528rd_dlpl_error_regs:
529 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g3 ! 6e2100
530 ldx [%g3+0x18], %l1 ! 6e2118 - PEU DLPL Status Reg
531 b test_failed ! No errors expected - go to bad trap
532 nop
533
534rd_ilu_error_regs:
535 ldx [%g3+0x10], %l0 ! 651010 - ILU Interrupt Status Reg
536 b test_failed ! No errors expected - go to bad trap
537 nop
538
539 ! Done.
540
541trap_done:
542 best_set_reg(FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_ADDR, %g1, %g4)
543 stx %g0, [%g4]
544 ldx [%g4], %l0
545
546 best_set_reg(FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_ADDR, %g1, %g4)
547 stx %g0, [%g4]
548 ldx [%g4], %l0
549
550 best_set_reg(MONDO_INT_ABUSY, %g1, %g4)
551 stx %g0, [%g4]
552 ldx [%g4], %l0
553
554 ldxa [%g0]ASI_SWVR_INTR_R, %l5
555
556 jmpl %o7+0x8, %g0
557 nop
558
559 .align 64
560err_cor_int_cnt: .xword 0
561err_fatal_int_cnt: .xword 0
562err_nonfatal_int_cnt: .xword 0
563
564/************************************************************************
565 Test case data start
566 ************************************************************************/
567
568SECTION .DATA DATA_VA=DMA_DATA_ADDR
569attr_data {
570 Name = .DATA,
571 hypervisor,
572 compressimage
573}
574
575.data
576 .xword 0x0001020304050607
577 .xword 0x08090a0b0c0d0e0f
578 .xword 0x1011121314151617
579 .xword 0x18191a1b1c1d1e1f
580 .xword 0x2021222324252627
581 .xword 0x28292a2b2c2d2e2f
582 .xword 0x3031323334353637
583 .xword 0x38393a3b3c3d3e3f
584
585 .xword 0x4041424344454647
586 .xword 0x48494a4b4c4d4e4f
587 .xword 0x5051525354555657
588 .xword 0x58595a5b5c5d5e5f
589 .xword 0x6061626364656667
590 .xword 0x68696a6b6c6d6e6f
591 .xword 0x7071727374757677
592 .xword 0x78797a7b7c7d7e7f
593
594 .xword 0x8081828384858687
595 .xword 0x88898a8b8c8d8e8f
596 .xword 0x9091929394959697
597 .xword 0x98999a9b9c9d9e9f
598 .xword 0xa0a1a2a3a4a5a6a7
599 .xword 0xa8a9aaabacadaeaf
600 .xword 0xb0b1b2b3b4b5b6b7
601 .xword 0xb8b9babbbcbdbebf
602
603 .xword 0xc0c1c2c3c4c5c6c7
604 .xword 0xc8c9cacbcccdcecf
605 .xword 0xd0d1d2d3d4d5d6d7
606 .xword 0xd8d9dadbdcdddedf
607 .xword 0xe0e1e2e3e4e5e6e7
608 .xword 0xe8e9eaebecedeeef
609 .xword 0xf0f1f2f3f4f5f6f7
610 .xword 0xf8f9fafbfcfdfeff
611
612 .xword 0x0001020304050607
613 .xword 0x08090a0b0c0d0e0f
614 .xword 0x1011121314151617
615 .xword 0x18191a1b1c1d1e1f
616 .xword 0x2021222324252627
617 .xword 0x28292a2b2c2d2e2f
618 .xword 0x3031323334353637
619 .xword 0x38393a3b3c3d3e3f
620
621 .xword 0x4041424344454647
622 .xword 0x48494a4b4c4d4e4f
623 .xword 0x5051525354555657
624 .xword 0x58595a5b5c5d5e5f
625 .xword 0x6061626364656667
626 .xword 0x68696a6b6c6d6e6f
627 .xword 0x7071727374757677
628 .xword 0x78797a7b7c7d7e7f
629
630 .xword 0x8081828384858687
631 .xword 0x88898a8b8c8d8e8f
632 .xword 0x9091929394959697
633 .xword 0x98999a9b9c9d9e9f
634 .xword 0xa0a1a2a3a4a5a6a7
635 .xword 0xa8a9aaabacadaeaf
636 .xword 0xb0b1b2b3b4b5b6b7
637 .xword 0xb8b9babbbcbdbebf
638
639 .xword 0xc0c1c2c3c4c5c6c7
640 .xword 0xc8c9cacbcccdcecf
641 .xword 0xd0d1d2d3d4d5d6d7
642 .xword 0xd8d9dadbdcdddedf
643 .xword 0xe0e1e2e3e4e5e6e7
644 .xword 0xe8e9eaebecedeeef
645 .xword 0xf0f1f2f3f4f5f6f7
646 .xword 0xf8f9fafbfcfdfeff
647
648/************************************************************************/
649
650
651/************************************************************************
652 IOMMU TTE start
653 TTE Format:
65463: 48 DEV KEY - set to 0
65547: 39 reserved - set to 0
65638: 13 DATA PA - set to VA for VA=RA
65712: 7 DATA_SOFT - set to 0
6586: 5 reserved - set to 0
6595: 3 FNM MASK - set to 0
6602: 2 KEY VALID - set to 0
6611: 1 DATA_W - set to 1
6620: 0 DATA_V - set to 1
663************************************************************************/
664
665SECTION .DATA2 DATA_VA=IOMMU_TTE_ADDR
666attr_data {
667 Name = .DATA2,
668 hypervisor,
669 compressimage
670}
671
672.data
673 init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000000010000)
674
675/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.