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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeDMARdMPS256Rcb.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeDMARdMPS256Rcb.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39#define ENABLE_PCIE_MPS_256
40!!#define ENABLE_PCIE_MPS_512
41#define MAIN_PAGE_HV_ALSO
42
43#include "hboot.s"
44#include "peu_defines.h"
45
46#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
47
48#define DMA_DATA_ADDR 0x0000000123456700
49#define DMA_DATA_BYP_ADDR mpeval(IOMMU_BYP_SADDR + DMA_DATA_ADDR)
50
51#define DMA_ADDR_1 mpeval(DMA_DATA_BYP_ADDR + 6*256, 16, 16)
52#define DMA_ADDR_2 mpeval(DMA_DATA_BYP_ADDR + 9*256, 16, 16)
53#define DMA_ADDR_3 mpeval(DMA_DATA_BYP_ADDR + 9*256, 16, 16)
54#define DMA_ADDR_4 mpeval(DMA_DATA_BYP_ADDR +10*256, 16, 16)
55#define DMA_ADDR_5 mpeval(DMA_DATA_BYP_ADDR +11*256, 16, 16)
56#define DMA_ADDR_6 mpeval(DMA_DATA_BYP_ADDR +12*256, 16, 16)
57#define DMA_ADDR_7 mpeval(DMA_DATA_BYP_ADDR +13*256, 16, 16)
58
59
60/************************************************************************
61 Test case code start
62 ************************************************************************/
63.text
64.global main
65
66main:
67 ta T_CHANGE_HPRIV
68 nop
69
70 ! enable bypass in IOMMU
71 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
72 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
73 stx %g3, [%g2]
74 ldx [%g2], %g3
75
76! Trigger some DMA Reads of various lengths
77
78Xmt1: nop
79! $EV trig_pc_d(1, @VA(.MAIN.Xmt1)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h188", 1 )
80 nop
81 nop
82Xmt2: nop
83! $EV trig_pc_d(1, @VA(.MAIN.Xmt2)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h196", 1 )
84 nop
85 nop
86Xmt3: nop
87! $EV trig_pc_d(1, @VA(.MAIN.Xmt3)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1aa", 1 )
88 nop
89 nop
90Xmt4: nop
91! $EV trig_pc_d(1, @VA(.MAIN.Xmt4)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1bb", 1 )
92 nop
93 nop
94Xmt5: nop
95! $EV trig_pc_d(1, @VA(.MAIN.Xmt5)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1cc", 1 )
96 nop
97 nop
98Xmt6: nop
99! $EV trig_pc_d(1, @VA(.MAIN.Xmt6)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1dd", 1 )
100 nop
101 nop
102Xmt7: nop
103! $EV trig_pc_d(1, @VA(.MAIN.Xmt7)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1ee", 1 )
104 nop
105 nop
106Xmt8: nop
107! $EV trig_pc_d(1, @VA(.MAIN.Xmt8)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h1ff", 1 )
108 nop
109 nop
110Xmt9: nop
111! $EV trig_pc_d(1, @VA(.MAIN.Xmt9)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h200", 1 )
112 nop
113 nop
114Xmt10: nop
115! $EV trig_pc_d(1, @VA(.MAIN.Xmt10)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h211", 1 )
116 nop
117 nop
118Xmt11: nop
119! $EV trig_pc_d(1, @VA(.MAIN.Xmt11)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2ff", 1 )
120 nop
121 nop
122Xmt12: nop
123! $EV trig_pc_d(1, @VA(.MAIN.Xmt12)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h200", 1 )
124 nop
125 nop
126Xmt13: nop
127! $EV trig_pc_d(1, @VA(.MAIN.Xmt13)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h201", 1 )
128 nop
129 nop
130Xmt14: nop
131! $EV trig_pc_d(1, @VA(.MAIN.Xmt14)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2ff", 1 )
132 nop
133 nop
134Xmt15: nop
135! $EV trig_pc_d(1, @VA(.MAIN.Xmt15)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h233", 1 )
136 nop
137 nop
138Xmt16: nop
139! $EV trig_pc_d(1, @VA(.MAIN.Xmt16)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h240", 1 )
140 nop
141 nop
142Xmt17: nop
143! $EV trig_pc_d(1, @VA(.MAIN.Xmt17)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h280", 1 )
144 nop
145 nop
146Xmt18: nop
147! $EV trig_pc_d(1, @VA(.MAIN.Xmt18)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2cc", 1 )
148 nop
149 nop
150
151
152 !!! pick coverage points for a few specific # DWs: 28, 312, 7, 700, 741, 853, 907
153
154Xmt19: nop
155! $EV trig_pc_d(1, @VA(.MAIN.Xmt19)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_1, "64'h070", 1 )
156 nop
157 nop
158 nop
159Xmt20: nop
160! $EV trig_pc_d(1, @VA(.MAIN.Xmt20)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_2, DMA_ADDR_2, "64'h4e0", 1 )
161 nop
162 nop
163 nop
164Xmt21: nop
165! $EV trig_pc_d(1, @VA(.MAIN.Xmt21)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_3, DMA_ADDR_3, "64'h01c", 1 )
166 nop
167 nop
168Xmt22: nop
169! $EV trig_pc_d(1, @VA(.MAIN.Xmt22)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_4, DMA_ADDR_4, "64'haf0", 1 )
170 nop
171 nop
172 nop
173Xmt23: nop
174! $EV trig_pc_d(1, @VA(.MAIN.Xmt23)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_5, DMA_ADDR_5, "64'hb94", 1 )
175 nop
176 nop
177 nop
178Xmt24: nop
179! $EV trig_pc_d(1, @VA(.MAIN.Xmt24)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_6, DMA_ADDR_6, "64'hd54", 1 )
180 nop
181 nop
182Xmt25: nop
183! $EV trig_pc_d(1, @VA(.MAIN.Xmt25)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_7, DMA_ADDR_7, "64'he2c", 1 )
184 nop
185 nop
186
187
188
189 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
190 setx 0x030, %g1, %g4 ! loop 48 times
191
192delay_loop:
193 ldx [%g3], %l1 ! PIU CSR READ
194
195 dec %g4 ! decrement counter
196 brnz %g4, delay_loop ! loop if not zero
197 nop
198
199
200test_passed:
201 EXIT_GOOD
202
203test_failed:
204 EXIT_BAD
205
206
207/************************************************************************
208 Test case data start
209************************************************************************/
210
211SECTION .DATA DATA_VA=DMA_DATA_ADDR
212attr_data {
213 Name = .DATA,
214 hypervisor,
215 compressimage
216}
217.data
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Full OpenSPARC design & verification tarball including full HDL.