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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeDMARdMPS512Rcb.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeDMARdMPS512Rcb.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39#define ENABLE_PCIE_MPS_512
40#define MAIN_PAGE_HV_ALSO
41
42#include "hboot.s"
43#include "peu_defines.h"
44
45#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
46
47#define DMA_DATA_ADDR 0x0000000123456700
48#define DMA_DATA_BYP_ADDR mpeval(IOMMU_BYP_SADDR + DMA_DATA_ADDR)
49
50#define DMA_ADDR_1 mpeval(DMA_DATA_BYP_ADDR + 5*256, 16, 16)
51#define DMA_ADDR_2 mpeval(DMA_DATA_BYP_ADDR + 10*256, 16, 16)
52#define DMA_ADDR_3 mpeval(DMA_DATA_BYP_ADDR + 11*256, 16, 16)
53#define DMA_ADDR_4 mpeval(DMA_DATA_BYP_ADDR + 12*256, 16, 16)
54
55
56/************************************************************************
57 Test case code start
58 ************************************************************************/
59.text
60.global main
61
62main:
63 ta T_CHANGE_HPRIV
64 nop
65
66 ! enable bypass in IOMMU
67 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
68 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
69 stx %g3, [%g2]
70 ldx [%g2], %g3
71
72! Trigger some DMA Reads of various lengths
73
74Xmt1: nop
75! $EV trig_pc_d(1, @VA(.MAIN.Xmt1)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h288", 1 )
76 nop
77 nop
78Xmt2: nop
79! $EV trig_pc_d(1, @VA(.MAIN.Xmt2)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h296", 1 )
80 nop
81 nop
82Xmt3: nop
83! $EV trig_pc_d(1, @VA(.MAIN.Xmt3)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2aa", 1 )
84 nop
85 nop
86Xmt4: nop
87! $EV trig_pc_d(1, @VA(.MAIN.Xmt4)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2bb", 1 )
88 nop
89 nop
90Xmt5: nop
91! $EV trig_pc_d(1, @VA(.MAIN.Xmt5)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2cc", 1 )
92 nop
93 nop
94Xmt6: nop
95! $EV trig_pc_d(1, @VA(.MAIN.Xmt6)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2dd", 1 )
96 nop
97 nop
98Xmt7: nop
99! $EV trig_pc_d(1, @VA(.MAIN.Xmt7)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2ee", 1 )
100 nop
101 nop
102Xmt8: nop
103! $EV trig_pc_d(1, @VA(.MAIN.Xmt8)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2ff", 1 )
104 nop
105 nop
106Xmt9: nop
107! $EV trig_pc_d(1, @VA(.MAIN.Xmt9)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h300", 1 )
108 nop
109 nop
110Xmt10: nop
111! $EV trig_pc_d(1, @VA(.MAIN.Xmt10)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h311", 1 )
112 nop
113 nop
114Xmt11: nop
115! $EV trig_pc_d(1, @VA(.MAIN.Xmt11)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h3ff", 1 )
116 nop
117 nop
118Xmt12: nop
119! $EV trig_pc_d(1, @VA(.MAIN.Xmt12)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h233", 1 )
120 nop
121 nop
122Xmt13: nop
123! $EV trig_pc_d(1, @VA(.MAIN.Xmt13)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h245", 1 )
124 nop
125 nop
126Xmt14: nop
127! $EV trig_pc_d(1, @VA(.MAIN.Xmt14)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h2ff", 1 )
128 nop
129 nop
130Xmt15: nop
131! $EV trig_pc_d(1, @VA(.MAIN.Xmt15)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h333", 1 )
132 nop
133 nop
134Xmt16: nop
135! $EV trig_pc_d(1, @VA(.MAIN.Xmt16)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h400", 1 )
136 nop
137 nop
138 nop
139Xmt18: nop
140! $EV trig_pc_d(1, @VA(.MAIN.Xmt18)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_1, DMA_ADDR_2, "64'h300", 1 )
141 nop
142 nop
143
144 !!! pick coverage points for a few specific # DWs: 106, 527, and 630
145
146Xmt19: nop
147! $EV trig_pc_d(1, @VA(.MAIN.Xmt19)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_2, DMA_ADDR_2, "64'h1a8", 1 )
148 nop
149 nop
150 nop
151Xmt20: nop
152! $EV trig_pc_d(1, @VA(.MAIN.Xmt20)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_3, DMA_ADDR_3, "64'h83c", 1 )
153 nop
154 nop
155 nop
156Xmt21: nop
157! $EV trig_pc_d(1, @VA(.MAIN.Xmt21)) -> EnablePCIeIgCmd ("DMARD", DMA_ADDR_4, DMA_ADDR_4, "64'h9d8", 1 )
158 nop
159 nop
160
161INTA:
162! $EV trig_pc_d(1,@VA(.MAIN.INTA)) -> EnablePCIeIgCmd("DMARD_INTA", DMA_ADDR_2, DMA_ADDR_2, "64'h0",1)
163 setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2
164 mov 100, %g3 ! loop count
165 mov 8, %g4 ! INTA asserted bit
166
167inta_wait:
168 ldx [%g2], %g5
169 cmp %g4,%g5
170 be got_inta
171
172 dec %g3
173 cmp %g3, 0
174 bne inta_wait
175 nop
176
177test_failed0:
178! $EV trig_pc_d(1, @VA(.MAIN.test_failed0)) -> printf("\n ERROR: timeout while waiting for INTA\n")
179 EXIT_BAD
180 nop
181
182got_inta:
183test_passed:
184 EXIT_GOOD
185
186test_failed:
187 EXIT_BAD
188
189
190/************************************************************************
191 Test case data start
192************************************************************************/
193
194SECTION .DATA DATA_VA=DMA_DATA_ADDR
195attr_data {
196 Name = .DATA,
197 hypervisor,
198 compressimage
199}
200.data
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Full OpenSPARC design & verification tarball including full HDL.