[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeDMAWrAdr64.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeDMAWrAdr64.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING
#define ENABLE_PCIE_MPS_512
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "peu_defines.h"

#define MEM32_RD_ADDR 		   mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)

!! #define DMA_DATA_ADDR		   0x0000000010000000
!! #define	DMA_DATA_BYP_ADDR	   mpeval(IOMMU_BYP_SADDR + DMA_DATA_ADDR)

#define DMA_DATA_ADDR          0000000123456000
	
#define DMA_ADDR_1           0xfffc000123456000 
#define DMA_ADDR_2           0xfffc000123456100 
#define DMA_ADDR_3           0xfffc000123456200 
#define DMA_ADDR_4           0xfffc000123456300 
#define DMA_ADDR_5           0xfffc000123456400 
#define DMA_ADDR_6           0xfffc000123456500 
#define DMA_ADDR_7           0xfffc000123456600 
#define DMA_ADDR_8           0xfffc000123456700 
#define DMA_ADDR_9           0xfffc000123456800 
#define DMA_ADDR_10          0xfffc000123456900 
#define DMA_ADDR_11          0xfffc000123456a00 
#define DMA_ADDR_12          0xfffc000123456b00 
#define DMA_ADDR_13          0xfffc000123456c00 
#define DMA_ADDR_14          0xfffc000123459000 
#define DMA_ADDR_15          0xfffc00012345a000 
#define DMA_ADDR_16          0xfffc00012345b000 
#define DMA_ADDR_17          0xfffc00012345c000


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

	! enable bypass in IOMMU
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
	setx	FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
	stx	%g3, [%g2]
	ldx	[%g2], %g3

! Trigger some DMA Writes of various lengths
	
Xmt1:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_1, DMA_ADDR_2, "64'h1", 1 )
	nop
	nop
Xmt2:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt2)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_2, DMA_ADDR_3, "64'h2", 1 )
	nop
	nop
Xmt3:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt3)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_3, DMA_ADDR_4, "64'h3", 1 )
	nop
	nop
Xmt4:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt4)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_4, DMA_ADDR_5, "64'h4", 1 )
	nop
	nop
Xmt5:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt5)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_5, DMA_ADDR_6, "64'h3f", 1 )
	nop
	nop
Xmt6:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt6)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_6, DMA_ADDR_7, "64'h40", 1 )
	nop
	nop
Xmt7:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt7)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_7, DMA_ADDR_8, "64'h41", 1 )
	nop
	nop
Xmt8:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt8)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_8, DMA_ADDR_9, "64'h7f", 1 )
	nop
	nop
Xmt9:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt9)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_9, DMA_ADDR_10, "64'h80", 1 )
	nop
	nop
Xmt10:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt10)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_10, DMA_ADDR_11, "64'h81", 1 )
	nop
	nop
Xmt11:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt11)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_11, DMA_ADDR_12, "64'hff", 1 )
	nop
	nop
Xmt12:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt12)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_12, DMA_ADDR_13, "64'h100", 1 )
	nop
	nop
Xmt13:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt13)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_13, DMA_ADDR_14, "64'h101", 1 )
	nop
	nop
Xmt14:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt14)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_14, DMA_ADDR_15, "64'h1ff", 1 )
	nop
	nop
Xmt15:	nop         ! $EV trig_pc_d(1, @VA(.MAIN.Xmt15)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_15, DMA_ADDR_16, "64'h200", 1 )
	nop
	nop

	! select a MEM32 address in PCI address range and transmit the command to NCU
	
	setx    MEM32_RD_ADDR, %g1, %g2
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
	setx	0x020, %g1, %g4		! loop 32 times

delay_loop:
	ldx	[%g3], %l1		! PIU CSR READ
	!!stx	%g2, [%g2]		! MEM32 PIO Write
	!!ldx	[%g2], %l0		! MEM32 PIO READ
	add	%g2, 8, %g2		! increment PIO  address
	
	dec	%g4			! decrement counter
	brnz	%g4, delay_loop		! loop if not zero
	nop

	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
	
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0xffffffffffffffff
	.xword 0xffffffffffffffff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeDMAWrAdr64.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	#define ENABLE_PCIE_MPS_512
	40	#define MAIN_PAGE_HV_ALSO
	41
	42	#include "hboot.s"
	43	#include "peu_defines.h"
	44
	45	#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	46
	47	!! #define DMA_DATA_ADDR 0x0000000010000000
	48	!! #define DMA_DATA_BYP_ADDR mpeval(IOMMU_BYP_SADDR + DMA_DATA_ADDR)
	49
	50	#define DMA_DATA_ADDR 0000000123456000
	51
	52	#define DMA_ADDR_1 0xfffc000123456000
	53	#define DMA_ADDR_2 0xfffc000123456100
	54	#define DMA_ADDR_3 0xfffc000123456200
	55	#define DMA_ADDR_4 0xfffc000123456300
	56	#define DMA_ADDR_5 0xfffc000123456400
	57	#define DMA_ADDR_6 0xfffc000123456500
	58	#define DMA_ADDR_7 0xfffc000123456600
	59	#define DMA_ADDR_8 0xfffc000123456700
	60	#define DMA_ADDR_9 0xfffc000123456800
	61	#define DMA_ADDR_10 0xfffc000123456900
	62	#define DMA_ADDR_11 0xfffc000123456a00
	63	#define DMA_ADDR_12 0xfffc000123456b00
	64	#define DMA_ADDR_13 0xfffc000123456c00
65	#define DMA_ADDR_14 0xfffc000123459000
66	#define DMA_ADDR_15 0xfffc00012345a000
67	#define DMA_ADDR_16 0xfffc00012345b000
68	#define DMA_ADDR_17 0xfffc00012345c000
69
70
71	/************************************************************************
72	Test case code start
73	************************************************************************/
74	.text
75	.global main
76
77	main:
78	ta T_CHANGE_HPRIV
79	nop
80
81	! enable bypass in IOMMU
82	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
83	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
84	stx %g3, [%g2]
85	ldx [%g2], %g3
86
87	! Trigger some DMA Writes of various lengths
88
89	Xmt1: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_1, DMA_ADDR_2, "64'h1", 1 )
90	nop
91	nop
92	Xmt2: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt2)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_2, DMA_ADDR_3, "64'h2", 1 )
93	nop
94	nop
95	Xmt3: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt3)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_3, DMA_ADDR_4, "64'h3", 1 )
96	nop
97	nop
98	Xmt4: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt4)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_4, DMA_ADDR_5, "64'h4", 1 )
99	nop
100	nop
101	Xmt5: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt5)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_5, DMA_ADDR_6, "64'h3f", 1 )
102	nop
103	nop
104	Xmt6: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt6)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_6, DMA_ADDR_7, "64'h40", 1 )
105	nop
106	nop
107	Xmt7: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt7)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_7, DMA_ADDR_8, "64'h41", 1 )
108	nop
109	nop
110	Xmt8: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt8)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_8, DMA_ADDR_9, "64'h7f", 1 )
111	nop
112	nop
113	Xmt9: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt9)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_9, DMA_ADDR_10, "64'h80", 1 )
114	nop
115	nop
116	Xmt10: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt10)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_10, DMA_ADDR_11, "64'h81", 1 )
117	nop
118	nop
119	Xmt11: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt11)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_11, DMA_ADDR_12, "64'hff", 1 )
120	nop
121	nop
122	Xmt12: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt12)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_12, DMA_ADDR_13, "64'h100", 1 )
123	nop
124	nop
125	Xmt13: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt13)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_13, DMA_ADDR_14, "64'h101", 1 )
126	nop
127	nop
128	Xmt14: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt14)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_14, DMA_ADDR_15, "64'h1ff", 1 )
129	nop
130	nop
131	Xmt15: nop ! $EV trig_pc_d(1, @VA(.MAIN.Xmt15)) -> EnablePCIeIgCmd ("DMAWR", DMA_ADDR_15, DMA_ADDR_16, "64'h200", 1 )
132	nop
133	nop
134
135	! select a MEM32 address in PCI address range and transmit the command to NCU
136
137	setx MEM32_RD_ADDR, %g1, %g2
138	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
139	setx 0x020, %g1, %g4 ! loop 32 times
140
141	delay_loop:
142	ldx [%g3], %l1 ! PIU CSR READ
143	!!stx %g2, [%g2] ! MEM32 PIO Write
144	!!ldx [%g2], %l0 ! MEM32 PIO READ
145	add %g2, 8, %g2 ! increment PIO address
146
147	dec %g4 ! decrement counter
148	brnz %g4, delay_loop ! loop if not zero
149	nop
150
151
152	test_passed:
153	EXIT_GOOD
154
155	test_failed:
156	EXIT_BAD
157
158
159	/************************************************************************
160	Test case data start
161	************************************************************************/
162
163	SECTION .DATA DATA_VA=DMA_DATA_ADDR
164	attr_data {
165	Name = .DATA,
166	hypervisor,
167	compressimage
168	}
169
170	.data
171	.global PCIAddr9
172
173	.xword 0x1011121314151617
174	.xword 0x18191a1b1c1d1e1f
175	.xword 0x2021222324252627
176	.xword 0x28292a2b2c2d2e2f
177	.xword 0x3031323334353637
178	.xword 0x38393a3b3c3d3e3f
179	.xword 0x4041424344454647
180	.xword 0x48494a4b4c4d4e4f
181	.xword 0xffffffffffffffff
182	.xword 0xffffffffffffffff
183	.xword 0x1011121314151617
184	.xword 0x18191a1b1c1d1e1f
185	.xword 0x2021222324252627
186	.xword 0x28292a2b2c2d2e2f
187	.xword 0x3031323334353637
188	.xword 0x38393a3b3c3d3e3f
189	.xword 0x4041424344454647
190	.xword 0x48494a4b4c4d4e4f
191	.xword 0xffffffffffffffff
192	.xword 0xffffffffffffffff
193	.xword 0x1011121314151617
194	.xword 0x18191a1b1c1d1e1f
195	.xword 0x2021222324252627
196	.xword 0x28292a2b2c2d2e2f
197	.xword 0x3031323334353637
198	.xword 0x38393a3b3c3d3e3f
199	.xword 0x4041424344454647
200	.xword 0x48494a4b4c4d4e4f
201	.xword 0xffffffffffffffff
202	.xword 0xffffffffffffffff
203	.xword 0x1011121314151617
204	.xword 0x18191a1b1c1d1e1f
205	.xword 0x2021222324252627
206	.xword 0x28292a2b2c2d2e2f
207	.xword 0x3031323334353637
208	.xword 0x38393a3b3c3d3e3f
209	.xword 0x4041424344454647
210	.xword 0x48494a4b4c4d4e4f
211	.xword 0xffffffffffffffff
212	.xword 0xffffffffffffffff
213	.xword 0x1011121314151617
214	.xword 0x18191a1b1c1d1e1f
215	.xword 0x2021222324252627
216	.xword 0x28292a2b2c2d2e2f
217	.xword 0x3031323334353637
218	.xword 0x38393a3b3c3d3e3f
219	.xword 0x4041424344454647
220	.xword 0x48494a4b4c4d4e4f
221	.xword 0xffffffffffffffff
222	.xword 0xffffffffffffffff
223	.xword 0x1011121314151617
224	.xword 0x18191a1b1c1d1e1f
225	.xword 0x2021222324252627
226	.xword 0x28292a2b2c2d2e2f
227	.xword 0x3031323334353637
228	.xword 0x38393a3b3c3d3e3f
229	.xword 0x4041424344454647
230	.xword 0x48494a4b4c4d4e4f
231	.xword 0xffffffffffffffff
232	.xword 0xffffffffffffffff
233	.xword 0x1011121314151617
234	.xword 0x18191a1b1c1d1e1f
235	.xword 0x2021222324252627
236	.xword 0x28292a2b2c2d2e2f
237	.xword 0x3031323334353637
238	.xword 0x38393a3b3c3d3e3f
239	.xword 0x4041424344454647
240	.xword 0x48494a4b4c4d4e4f
241	.xword 0xffffffffffffffff
242	.xword 0xffffffffffffffff
243	.xword 0x1011121314151617
244	.xword 0x18191a1b1c1d1e1f
245	.xword 0x2021222324252627
246	.xword 0x28292a2b2c2d2e2f
247	.xword 0x3031323334353637
248	.xword 0x38393a3b3c3d3e3f
249	.xword 0x4041424344454647
250	.xword 0x48494a4b4c4d4e4f
251	.xword 0xffffffffffffffff
252	.xword 0xffffffffffffffff
253	.xword 0x1011121314151617
254	.xword 0x18191a1b1c1d1e1f
255	.xword 0x2021222324252627
256	.xword 0x28292a2b2c2d2e2f
257	.xword 0x3031323334353637
258	.xword 0x38393a3b3c3d3e3f
259	.xword 0x4041424344454647
260	.xword 0x48494a4b4c4d4e4f
261	.xword 0xffffffffffffffff
262	.xword 0xffffffffffffffff
263
264	/************************************************************************/