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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeDMAWrNonContigDWBE.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeDMAWrNonContigDWBE.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39#define MAIN_PAGE_HV_ALSO
40
41#include "hboot.s"
42#include "peu_defines.h"
43
44#define DMA_DATA_ADDR 0x0000000123456000
45
46#define DMA_ADDR_1 0xfffc000123456000
47#define DMA_ADDR_2 0xfffc000123456040
48#define DMA_ADDR_3 0xfffc000123456080
49#define DMA_ADDR_4 0xfffc0001234560c0
50#define DMA_ADDR_5 0xfffc000123456100
51#define DMA_ADDR_6 0xfffc000123456140
52#define DMA_ADDR_7 0xfffc000123456180
53#define DMA_ADDR_8 0xfffc0001234561c0
54#define DMA_ADDR_9 0xfffc000123456200
55#define DMA_ADDR_10 0xfffc000123456240
56#define DMA_ADDR_11 0xfffc000123456280
57#define DMA_ADDR_12 0xfffc0001234562c0
58#define DMA_ADDR_13 0xfffc000123456300
59#define DMA_ADDR_14 0xfffc000123459340
60#define DMA_ADDR_15 0xfffc00012345a380
61#define DMA_ADDR_16 0xfffc00012345b3c0
62#define DMA_ADDR_17 0xfffc00012345c400
63
64
65/************************************************************************
66 Test case code start
67 ************************************************************************/
68.text
69.global main
70
71main:
72 ta T_CHANGE_HPRIV
73 nop
74
75! Trigger some DMA Writes of 1 DW with non-contiguous FirstDWBE = 0101, 1001, 1010, 1011, 1101
76
77Xmt1: nop
78! $EV trig_pc_d(1, @VA(.MAIN.Xmt1)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_1, 0x05, "64'h4", 1 )
79 nop
80 nop
81Xmt2: nop
82! $EV trig_pc_d(1, @VA(.MAIN.Xmt2)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_2, 0x09, "64'h4", 1 )
83 nop
84 nop
85Xmt3: nop
86! $EV trig_pc_d(1, @VA(.MAIN.Xmt3)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_3, 0x0a, "64'h4", 1 )
87 nop
88 nop
89Xmt4: nop
90! $EV trig_pc_d(1, @VA(.MAIN.Xmt4)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_4, 0x0b, "64'h4", 1 )
91 nop
92 nop
93Xmt5: nop
94! $EV trig_pc_d(1, @VA(.MAIN.Xmt5)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_5, 0x0d, "64'h4", 1 )
95 nop
96 nop
97
98! Trigger some DMA Writes of 2 DW with non-contiguous LastDWBE
99
100 nop
101 nop
102Xmt6: nop
103! $EV trig_pc_d(1, @VA(.MAIN.Xmt6)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_6, 0x55, "64'h8", 1 )
104 nop
105 nop
106Xmt7: nop
107! $EV trig_pc_d(1, @VA(.MAIN.Xmt7)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_7, 0x99, "64'h8", 1 )
108 nop
109 nop
110Xmt8: nop
111! $EV trig_pc_d(1, @VA(.MAIN.Xmt8)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_8, 0xaa, "64'h8", 1 )
112 nop
113 nop
114Xmt9: nop
115! $EV trig_pc_d(1, @VA(.MAIN.Xmt9)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_9, 0xbb, "64'h8", 1 )
116 nop
117 nop
118Xmt10: nop
119! $EV trig_pc_d(1, @VA(.MAIN.Xmt10)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_10, 0xdd, "64'h8", 1 )
120 nop
121 nop
122 nop
123Xmt11: nop
124! $EV trig_pc_d(1, @VA(.MAIN.Xmt11)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_11, 0x54, "64'h8", 1 )
125 nop
126 nop
127Xmt12: nop
128! $EV trig_pc_d(1, @VA(.MAIN.Xmt12)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_12, 0x92, "64'h8", 1 )
129 nop
130 nop
131Xmt13: nop
132! $EV trig_pc_d(1, @VA(.MAIN.Xmt13)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_13, 0xa1, "64'h8", 1 )
133 nop
134 nop
135Xmt14: nop
136! $EV trig_pc_d(1, @VA(.MAIN.Xmt14)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_14, 0xb3, "64'h8", 1 )
137 nop
138 nop
139Xmt15: nop
140! $EV trig_pc_d(1, @VA(.MAIN.Xmt15)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_15, 0xd6, "64'h8", 1 )
141 nop
142 nop
143Xmt16: nop
144! $EV trig_pc_d(1, @VA(.MAIN.Xmt16)) -> EnablePCIeIgCmd ("DMAWR_DWBE", DMA_ADDR_16, 0xd7, "64'h8", 1 )
145 nop
146 nop
147 nop
148
149 ! select a MEM32 address in PCI address range and transmit the command to NCU
150
151 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
152 setx 0x010, %g1, %g4 ! loop 16 times
153
154delay_loop:
155 ldx [%g3], %l1 ! PIU CSR READ
156 add %g2, 8, %g2 ! increment PIO address
157
158 dec %g4 ! decrement counter
159 brnz %g4, delay_loop ! loop if not zero
160 nop
161
162 ! read the data area
163 setx DMA_DATA_ADDR, %g1, %g2
164 setx 16, %g1, %g4 ! loop 16 times
165
166read_loop:
167 ldx [%g2], %l1 ! Read the data area
168 add %g2, 0x40, %g2 ! increment data address
169
170 dec %g4 ! decrement counter
171 brnz %g4, read_loop ! loop if not zero
172 nop
173
174test_passed:
175 EXIT_GOOD
176
177test_failed:
178 EXIT_BAD
179
180
181/************************************************************************
182 Test case data start
183************************************************************************/
184
185SECTION .DATA DATA_VA=DMA_DATA_ADDR
186attr_data {
187 Name = .DATA,
188 hypervisor,
189 compressimage
190}
191
192.data
193 .xword 0x1011121314151617
194 .xword 0x18191a1b1c1d1e1f
195 .align 64
196 .xword 0x2021222324252627
197 .xword 0x28292a2b2c2d2e2f
198 .align 64
199 .xword 0x3031323334353637
200 .xword 0x38393a3b3c3d3e3f
201 .align 64
202 .xword 0x4041424344454647
203 .xword 0x48494a4b4c4d4e4f
204 .align 64
205 .xword 0xffffffffffffffff
206 .xword 0xffffffffffffffff
207 .align 64
208 .xword 0x1011121314151617
209 .xword 0x18191a1b1c1d1e1f
210 .align 64
211 .xword 0x2021222324252627
212 .xword 0x28292a2b2c2d2e2f
213 .align 64
214 .xword 0x3031323334353637
215 .xword 0x38393a3b3c3d3e3f
216 .align 64
217 .xword 0x4041424344454647
218 .xword 0x48494a4b4c4d4e4f
219 .align 64
220 .xword 0x1011121314151617
221 .xword 0x18191a1b1c1d1e1f
222 .align 64
223 .xword 0x2021222324252627
224 .xword 0x28292a2b2c2d2e2f
225 .align 64
226 .xword 0x3031323334353637
227 .xword 0x38393a3b3c3d3e3f
228 .align 64
229 .xword 0x4041424344454647
230 .xword 0x48494a4b4c4d4e4f
231 .align 64
232 .xword 0xffffffffffffffff
233 .xword 0xffffffffffffffff
234 .align 64
235 .xword 0x1011121314151617
236 .xword 0x18191a1b1c1d1e1f
237 .align 64
238 .xword 0x2021222324252627
239 .xword 0x28292a2b2c2d2e2f
240 .align 64
241 .xword 0x3031323334353637
242 .xword 0x38393a3b3c3d3e3f
243 .align 64
244 .xword 0x4041424344454647
245 .xword 0x48494a4b4c4d4e4f
246
247/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.