[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeEgrHPeDrainState.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeEgrHPeDrainState.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING    
#define MAIN_PAGE_HV_ALSO

#ifndef PCIE_USE_SSYS_RESET
#define RESET_STAT_CHECK
#define RESET_CHECK_REG
#define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler
#endif

#define H_HT0_Data_access_error_0x32
#define SUN_H_HT0_Data_access_error_0x32 \
	inc     %l4; \
	done;

#include "hboot.s"
#include "peu_defines.h"
#include "dmu_peu_regs.h"
#include "rst_defines.h"

#define MEM_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
#define DMA_DATA_ADDR   	0x0000000123456000
#define DMARD_ADDR1		0xfffc000123456000
#define DMARD_ADDR2		0xfffc000123457000
#define DMARD_ADDR3		0xfffc000123458000
#define DMARD_ADDR4		0xfffc000123459000

/*
Test case code start
*/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

/************************************************************
 Check if this is the first time thru here
 ************************************************************/
	setx	test_entered, %g1, %g2
	ldx	[%g2], %g3
	brnz	%g3, After_Warm_Reset
	nop
	
! First time thru, Store a non-zero value there 
	dec	%g3
	stx	%g3, [%g2]
	
/************************************************************
 make sure the detect.quiet bit is set
 ************************************************************/
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
	ldx	[%g3], %g4
	mov	0x100, %g5
        orcc    %g5, %g4, %g5	! OR in bit 8 == 1
	stx	%g5, [%g3]
	ldx	[%g3], %g4
	
/************************************************************
 Fire off some PIOs and DMA Reads, then bring down the link.
 ************************************************************/
Start_PIOs_and_DMARDs:
	setx	MEM_WR_ADDR, %g1, %g2
	setx	0x3335373992828384, %g1, %l0
	stb	%l0, [%g2]
	sth	%l0, [%g2 + 4]
	stw	%l0, [%g2 + 8]
	ldx	[%g2], %l1

	! here is where we bring down the link, to force an error
Bring_down_the_link:
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
        ldx	[%g3], %l3
        stx	%l3, [%g3]	! clear any OE status bits

!	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_ADDR, %g1, %g4
!	best_set_reg( 0xa5a50080, %g1, %l4 )
!        stx	%l4, [%g4]	! set the EHP error injection triggers
/***************************************************************
 Write the EHI_PAR and EHI_TRG fields of the ILU DIAGNOSTIC CSR
 ***************************************************************/
	setx	FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR, %g1, %g4
	ldx	[%g4], %l3
	best_set_reg(0x00000110, %g1, %l4) ! set bits 8 & 4 (EHI_PAR & EHI_TRG)
	or	%l3, %l4, %l3
	stx	%l3, [%g4]		   ! set the EDP error injection triggers

	
	stx	%l0, [%g2 + 16]	! PIO write ===> should get the EHP error
	

	! now wait for the "Egress Parity Error (EHP)" primary or secondary status to be set
	mov	10, %l0
         setx	0x0000100000001000, %g1, %l1	! mask for EHP Primary and Secondary Events
Wait_for_EHP:
        ldx	[%g3], %l3
        andcc   %l1, %l3, %l4
        bne     %xcc, Check_drain_state
	nop
	dec	%l0
	brnz	%l0, Wait_for_EHP
	nop
	b       test_failed
	nop
	
/************************************************************
 check that drain.state bit is set in the PEU Status Register
 ************************************************************/
Check_drain_state:
	
! This user event will force the next PIO to NOT to call expectPCIE().
! $EV trig_pc_d(1,@VA(.MAIN.Check_drain_state)) -> EnablePCIeIgCmd("PIO_NOEXP",0,0,0,1)
	
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR, %g1, %g4
	ldx	[%g4], %l4
	mov	0x100, %g5
	andcc   %l4, %g5, %l0
	bz	test_failed		! branch if drain state is not set
	nop	
	
	! issue PIO read request(s) - these should complete with Bus Error
	mov	0, %l4
	setx	MEM_WR_ADDR, %g1, %g5
PioBusErr:
	ldx	[%g5], %l3		! ==> this should get a bus error

	dec	%l4			! <== only one interrupt expected
	brnz    %l4, test_failed
	nop
	
	! insure that no outstanding DMA read requests are outstanding
	! by checking that there are no entries on the Transaction Scoreboard
	setx	FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR, %g1, %g5
	mov	0, %l0
	dec	%l0
	mov	0x01, %l1
	xor	%l1, %l0, %l1
Wait_for_dma_read_clear:
	ldx	[%g5], %l4
	andcc	%l4, %l1, %l2
	bnz     Wait_for_dma_read_clear
	nop
	
	! clear the EHP status bit
        ldx	[%g3], %l1
	stx	%l1, [%g3]		! RW1C
        ldx	[%g3], %l1
	brnz	%l1, test_failed	! branch if link down is not cleared
	nop
	
	! clear the drain bit - its also a RW1C bit
	mov	0x100, %g5
	stx	%g5, [%g4]		! RW1C
	ldx	[%g4], %l4
	andcc   %l4, %g5, %l4
	bnz	test_failed		! branch if drain state is not cleared
	nop
	
/************************************************************
 do the warm reset
 ************************************************************/
do_WARM_RESET:
! xxx trig_pc_d(1,@VA(.MAIN.do_WARM_RESET)) -> EnablePCIeIgCmd("SOFTRESET",0,0,0,1)
	
#ifdef PCIE_USE_SSYS_RESET
        setx    RST_SSYS_RESET, %g1, %g5	! subsystem reset reg
        mov	RST_SSYS_RESET__DMU_PEU, %g7	! subsystem reset reg data
        stx     %g7, [%g5]			! Subsystem Reset
	
	mov	10, %l0				! loop timeout count
	
Wait4SsysReset:
	ldx     [%g5], %l7		!  check if reset bit has cleared
	brz	%l7, redo_link_training
	nop
	dec	%l0
	brnz	%l0, Wait4SsysReset
	nop
	ba	test_failed		! Subsystem reset should have completed
	nop
/************************************************************
 Now redo link training...
 ************************************************************/
redo_link_training:
        setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3
	ldx	[%g3], %g4
        mov     0x0010, %g5	! FAST LINK MODE, for simulation.
	or	%g4, %g5, %g5
        stx     %g5, [%g3]

	! clear bit 8, to not remain in Detect.Quiet state
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
	mov	0x001, %l4
	stx	%l4, [%g3]

	! enable bypass in IOMMU
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
	setx	FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
	stx	%g3, [%g2]

! wait for the "Link Up" status bit to get set in the PEU
! (this code copied from peu_init.h)
	
        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
        ldx	[%g3], %l4
        stx	%l4, [%g3]		! clear any status bits that are set
        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
	mov	255, %l0
        mov	FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1

LinkTrainingLoop2:
        ldx	[%g3], %l4		! bit 8 is Link Up primary event
        ldx	[%g4], %l5		! bits 48:44 are the LTSSM state
        andcc   %l1, %l4, %l4
        bne     After_Warm_Reset
	nop

	dec	%l0
	brnz	%l0, LinkTrainingLoop2
	nop
	b       test_failed
	nop

#else
        setx    RST_RESET_GEN, %g1, %g5	! warm reset reg
        mov	RST_RESET_GEN__WMR_GEN, %g7	! warm reset reg data
	mov	255, %l0		! loop timeout count
	
        stx     %g7, [%g5]		! Warm Reset
        ldx     [%g5], %g7
	
Wait4WarmReset:
	dec	%l0
	brnz	%l0, Wait4WarmReset
	nop
	ba	test_failed		! Warm reset should have happened
	nop
#endif	

/********************************************************************
 Do a couple of PIOs and DMAs to verify that the PCIe link is working.
 ********************************************************************/
After_Warm_Reset:
	nop
	! clear any error bits from from the DLPL Status reg
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
	ldx	[%g6], %l7
	stx	%l7, [%g6]		! RW1C
	ldx	[%g6], %l7
	brnz	%l7, test_failed	! branch if it is not cleared
	nop
	
DmaRd5:	nop
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd5)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR2,DMARD_ADDR2,"64'h40",1)
	setx	MEM_WR_ADDR, %g1, %g5
	mov	0, %l4
	stx	%g3, [%g5]		! 3 PIO Writes
	stx	%g4, [%g5+8]
	stx	%g5, [%g5+16]
DmaRd6:	nop
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd6)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR3,DMARD_ADDR3,"64'h40",1)
	ldx	[%g5], %l0		! 3 PIO Reads
	ldx	[%g5+8], %l1
	ldx	[%g5+16], %l2
	
DmaRd7:	nop
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd7)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR4,DMARD_ADDR4,"64'h40",1)
        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
        ldx	[%g3], %l5		! bit 8 is Link Up primary event
	
        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
        ldx	[%g4], %l6		! bits 48:44 are the LTSSM state
	
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
	ldx	[%g6], %l7		! dlpl status
	
	brnz    %l4, test_failed	! no interrupts were expected
	nop
	nop
		
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
 Test case data start
 ************************************************************************/
	.align 64
test_entered:
	.xword 0


SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}
.data
	init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004)
/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeEgrHPeDrainState.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#ifndef PCIE_USE_SSYS_RESET
	42	#define RESET_STAT_CHECK
	43	#define RESET_CHECK_REG
	44	#define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler
	45	#endif
	46
	47	#define H_HT0_Data_access_error_0x32
	48	#define SUN_H_HT0_Data_access_error_0x32 \
	49	inc %l4; \
	50	done;
	51
	52	#include "hboot.s"
	53	#include "peu_defines.h"
	54	#include "dmu_peu_regs.h"
	55	#include "rst_defines.h"
	56
	57	#define MEM_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	58	#define DMA_DATA_ADDR 0x0000000123456000
	59	#define DMARD_ADDR1 0xfffc000123456000
	60	#define DMARD_ADDR2 0xfffc000123457000
	61	#define DMARD_ADDR3 0xfffc000123458000
	62	#define DMARD_ADDR4 0xfffc000123459000
	63
	64	/*
65	Test case code start
66	*/
67	.text
68	.global main
69
70	main:
71	ta T_CHANGE_HPRIV
72	nop
73
74	/************************************************************
75	Check if this is the first time thru here
76	************************************************************/
77	setx test_entered, %g1, %g2
78	ldx [%g2], %g3
79	brnz %g3, After_Warm_Reset
80	nop
81
82	! First time thru, Store a non-zero value there
83	dec %g3
84	stx %g3, [%g2]
85
86	/************************************************************
87	make sure the detect.quiet bit is set
88	************************************************************/
89	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
90	ldx [%g3], %g4
91	mov 0x100, %g5
92	orcc %g5, %g4, %g5 ! OR in bit 8 == 1
93	stx %g5, [%g3]
94	ldx [%g3], %g4
95
96	/************************************************************
97	Fire off some PIOs and DMA Reads, then bring down the link.
98	************************************************************/
99	Start_PIOs_and_DMARDs:
100	setx MEM_WR_ADDR, %g1, %g2
101	setx 0x3335373992828384, %g1, %l0
102	stb %l0, [%g2]
103	sth %l0, [%g2 + 4]
104	stw %l0, [%g2 + 8]
105	ldx [%g2], %l1
106
107	! here is where we bring down the link, to force an error
108	Bring_down_the_link:
109	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
110	ldx [%g3], %l3
111	stx %l3, [%g3] ! clear any OE status bits
112
113	! setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_ADDR, %g1, %g4
114	! best_set_reg( 0xa5a50080, %g1, %l4 )
115	! stx %l4, [%g4] ! set the EHP error injection triggers
116	/***************************************************************
117	Write the EHI_PAR and EHI_TRG fields of the ILU DIAGNOSTIC CSR
118	***************************************************************/
119	setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR, %g1, %g4
120	ldx [%g4], %l3
121	best_set_reg(0x00000110, %g1, %l4) ! set bits 8 & 4 (EHI_PAR & EHI_TRG)
122	or %l3, %l4, %l3
123	stx %l3, [%g4] ! set the EDP error injection triggers
124
125
126	stx %l0, [%g2 + 16] ! PIO write ===> should get the EHP error
127
128
129	! now wait for the "Egress Parity Error (EHP)" primary or secondary status to be set
130	mov 10, %l0
131	setx 0x0000100000001000, %g1, %l1 ! mask for EHP Primary and Secondary Events
132	Wait_for_EHP:
133	ldx [%g3], %l3
134	andcc %l1, %l3, %l4
135	bne %xcc, Check_drain_state
136	nop
137	dec %l0
138	brnz %l0, Wait_for_EHP
139	nop
140	b test_failed
141	nop
142
143	/************************************************************
144	check that drain.state bit is set in the PEU Status Register
145	************************************************************/
146	Check_drain_state:
147
148	! This user event will force the next PIO to NOT to call expectPCIE().
149	! $EV trig_pc_d(1,@VA(.MAIN.Check_drain_state)) -> EnablePCIeIgCmd("PIO_NOEXP",0,0,0,1)
150
151	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR, %g1, %g4
152	ldx [%g4], %l4
153	mov 0x100, %g5
154	andcc %l4, %g5, %l0
155	bz test_failed ! branch if drain state is not set
156	nop
157
158	! issue PIO read request(s) - these should complete with Bus Error
159	mov 0, %l4
160	setx MEM_WR_ADDR, %g1, %g5
161	PioBusErr:
162	ldx [%g5], %l3 ! ==> this should get a bus error
163
164	dec %l4 ! <== only one interrupt expected
165	brnz %l4, test_failed
166	nop
167
168	! insure that no outstanding DMA read requests are outstanding
169	! by checking that there are no entries on the Transaction Scoreboard
170	setx FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR, %g1, %g5
171	mov 0, %l0
172	dec %l0
173	mov 0x01, %l1
174	xor %l1, %l0, %l1
175	Wait_for_dma_read_clear:
176	ldx [%g5], %l4
177	andcc %l4, %l1, %l2
178	bnz Wait_for_dma_read_clear
179	nop
180
181	! clear the EHP status bit
182	ldx [%g3], %l1
183	stx %l1, [%g3] ! RW1C
184	ldx [%g3], %l1
185	brnz %l1, test_failed ! branch if link down is not cleared
186	nop
187
188	! clear the drain bit - its also a RW1C bit
189	mov 0x100, %g5
190	stx %g5, [%g4] ! RW1C
191	ldx [%g4], %l4
192	andcc %l4, %g5, %l4
193	bnz test_failed ! branch if drain state is not cleared
194	nop
195
196	/************************************************************
197	do the warm reset
198	************************************************************/
199	do_WARM_RESET:
200	! xxx trig_pc_d(1,@VA(.MAIN.do_WARM_RESET)) -> EnablePCIeIgCmd("SOFTRESET",0,0,0,1)
201
202	#ifdef PCIE_USE_SSYS_RESET
203	setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg
204	mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data
205	stx %g7, [%g5] ! Subsystem Reset
206
207	mov 10, %l0 ! loop timeout count
208
209	Wait4SsysReset:
210	ldx [%g5], %l7 ! check if reset bit has cleared
211	brz %l7, redo_link_training
212	nop
213	dec %l0
214	brnz %l0, Wait4SsysReset
215	nop
216	ba test_failed ! Subsystem reset should have completed
217	nop
218	/************************************************************
219	Now redo link training...
220	************************************************************/
221	redo_link_training:
222	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3
223	ldx [%g3], %g4
224	mov 0x0010, %g5 ! FAST LINK MODE, for simulation.
225	or %g4, %g5, %g5
226	stx %g5, [%g3]
227
228	! clear bit 8, to not remain in Detect.Quiet state
229	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
230	mov 0x001, %l4
231	stx %l4, [%g3]
232
233	! enable bypass in IOMMU
234	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
235	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
236	stx %g3, [%g2]
237
238	! wait for the "Link Up" status bit to get set in the PEU
239	! (this code copied from peu_init.h)
240
241	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
242	ldx [%g3], %l4
243	stx %l4, [%g3] ! clear any status bits that are set
244	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
245	mov 255, %l0
246	mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1
247
248	LinkTrainingLoop2:
249	ldx [%g3], %l4 ! bit 8 is Link Up primary event
250	ldx [%g4], %l5 ! bits 48:44 are the LTSSM state
251	andcc %l1, %l4, %l4
252	bne After_Warm_Reset
253	nop
254
255	dec %l0
256	brnz %l0, LinkTrainingLoop2
257	nop
258	b test_failed
259	nop
260
261	#else
262	setx RST_RESET_GEN, %g1, %g5 ! warm reset reg
263	mov RST_RESET_GEN__WMR_GEN, %g7 ! warm reset reg data
264	mov 255, %l0 ! loop timeout count
265
266	stx %g7, [%g5] ! Warm Reset
267	ldx [%g5], %g7
268
269	Wait4WarmReset:
270	dec %l0
271	brnz %l0, Wait4WarmReset
272	nop
273	ba test_failed ! Warm reset should have happened
274	nop
275	#endif
276
277	/********************************************************************
278	Do a couple of PIOs and DMAs to verify that the PCIe link is working.
279	********************************************************************/
280	After_Warm_Reset:
281	nop
282	! clear any error bits from from the DLPL Status reg
283	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
284	ldx [%g6], %l7
285	stx %l7, [%g6] ! RW1C
286	ldx [%g6], %l7
287	brnz %l7, test_failed ! branch if it is not cleared
288	nop
289
290	DmaRd5: nop
291	! $EV trig_pc_d(1, @VA(.MAIN.DmaRd5)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR2,DMARD_ADDR2,"64'h40",1)
292	setx MEM_WR_ADDR, %g1, %g5
293	mov 0, %l4
294	stx %g3, [%g5] ! 3 PIO Writes
295	stx %g4, [%g5+8]
296	stx %g5, [%g5+16]
297	DmaRd6: nop
298	! $EV trig_pc_d(1, @VA(.MAIN.DmaRd6)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR3,DMARD_ADDR3,"64'h40",1)
299	ldx [%g5], %l0 ! 3 PIO Reads
300	ldx [%g5+8], %l1
301	ldx [%g5+16], %l2
302
303	DmaRd7: nop
304	! $EV trig_pc_d(1, @VA(.MAIN.DmaRd7)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR4,DMARD_ADDR4,"64'h40",1)
305	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
306	ldx [%g3], %l5 ! bit 8 is Link Up primary event
307
308	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
309	ldx [%g4], %l6 ! bits 48:44 are the LTSSM state
310
311	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
312	ldx [%g6], %l7 ! dlpl status
313
314	brnz %l4, test_failed ! no interrupts were expected
315	nop
316	nop
317
318	test_passed:
319	EXIT_GOOD
320
321	test_failed:
322	EXIT_BAD
323
324
325	/************************************************************************
326	Test case data start
327	************************************************************************/
328	.align 64
329	test_entered:
330	.xword 0
331
332
333	SECTION .DATA DATA_VA=DMA_DATA_ADDR
334	attr_data {
335	Name = .DATA,
336	hypervisor,
337	compressimage
338	}
339	.data
340	init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004)
341	/************************************************************************/