[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeFireDeadlockScn1.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeFireDeadlockScn1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING
#define ENABLE_PCIE_MPS_256
#define MAIN_PAGE_HV_ALSO

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
        call    my_trap_code; \
        nop; \
        retry; \
        nop; 

#include "hboot.s"
#include "peu_defines.h"
#include "ncu_defines.h"
#include "cmp_macros.h"

#define MEM32_RD_ADDR		mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
#define MEM32_WR_ADDR 		mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
#define CFG1_WR_ADDR		mpeval((N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA) | CFG1_ACCESS_PA)

#define DMA_DATA_ADDR		0x00800000

#define IOMMU_TTE_ADDR		0x40000000

! Bit 8 = Page Size: 0=8KB, 1=64KB;  Bits 3:0 = TSB Table size:	6=64k entries 
#define MMU_TSB_CNTRL_REG_DATA	   mpeval(IOMMU_TTE_ADDR | 0x100 | 6)

#define	NCU_IOMMU_INVALIDATE_REG_ADDR	0x8000002030

/************************************************************************
   Test case code start
 ************************************************************************/
SECTION .MAIN
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

th_fork(th_main, %l0)

th_main_0:
! enable interrupts & provide basic handler
#include "piu_rupt_enable.s"

StallCpl: nop
! $EV trig_pc_d(1,@VA(.MAIN.StallCpl)) -> EnablePCIeIgCmd("STALL_CPL", 0, 0, "64'h40",1)

! set the Traffic Class for all the DMA R&W TLPs to 5, so denali doesn't
! send them out of order
settc:	nop ! $EV trig_pc_d(1, @VA(.MAIN.settc)) -> EnablePCIeIgCmd ("SET_TC", 5, 0, 0, 1 )

	SYNC_THREAD_MAIN( test_failed, %g1, %g2, %g3 )

	!!! 1. Do a Memory Read request A
	
	setx	MEM32_RD_ADDR, %g1, %g2
	ldx	[%g2], %l1		! completion on this PIO READ will stall

	ldx	[%g2+8], %l2

	ldx	[%g2+16],%l3

	ldx	[%g2+24],%l4

	ldx	[%g2+32],%l5

	ba	test_passed
	nop
	
/************************************************************************
   Thread 1 will issue the PIO Memory Write requests
 ************************************************************************/
th_main_1:

! enable SUN4U translation in the IOMMU
	
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
	setx	0x00301, %g1, %g3	! 9:8 11 = Cache enabled, 0: 1 = translation enabled
	stx	%g3, [%g2]
	ldx	[%g2], %g3
	
! load address of the TSB table, and the page size (64KB)
	
	setx	FIRE_DLC_MMU_CSR_A_TSB_ADDR, %g1, %g2
	setx	MMU_TSB_CNTRL_REG_DATA, %g1, %g3
	stx	%g3, [%g2]
	ldx	[%g2], %g3

	SYNC_THREAD_OTHER( %o1,%g1,%g2 )

	!!! 2. Cfg Write Request B
	
	mov	5, %g2
delay_loop:			! give thread 0 a chance to do the memory read pio
	dec	%g2
	cmp	%g2, 0
	bne	delay_loop
	nop

	setx	CFG1_WR_ADDR, %g1, %g2
	setx	0x11223344, %g1, %l1
	stw	%l1, [%g2]		! this PIO write will stall due to NPWR_EN

	!!! 3. 5 of the 35 Memory write requests C0-C34
	
	setx	MEM32_RD_ADDR, %g1, %g2
	sll	%l0, 24, %l1
	or	%l1, %g2, %g2

	setx	0x1111111111111111, %g1, %g3
	stx	%g3, [%g2] 

	setx	0x1212121212121212, %g1, %g3
	stx	%g3, [%g2+8]
	
	setx	0x1313131313131313, %g1, %g3
	stx	%g3, [%g2+16] 

	setx	0x1414141414141414, %g1, %g3
	stx	%g3, [%g2+24] 

	setx	0x1515151515151515, %g1, %g3
	stx	%g3, [%g2+32] 

	mov	30, %g2
delay_loop0:
	dec	%g2
	cmp	%g2, 0
	bne	delay_loop0
	nop;nop;nop;nop
	
	!!! 4. DMA Memory Read Requests E (4k byte total)
 	
#define DMARD_ADDR_1 mpeval(0x00800000,16,16)
DMARD1: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMARD1)) -> EnablePCIeIgCmd("DMARD", DMARD_ADDR_1, DMARD_ADDR_1, "64'h1000",1)

	!!! 5. DMA Memory Read Request F (any size)
 	
#define DMARD_ADDR_2 mpeval(0x00801000,16,16)
DMARD2: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMARD2)) -> EnablePCIeIgCmd("DMARD_INTA", DMARD_ADDR_2, DMARD_ADDR_2, "64'h100",1)

	mov	200, %g2
delay_loop00:			! give denali a chance to send the dma reads & L2 to respond
	dec	%g2
	cmp	%g2, 0
	bne	delay_loop00
	nop;nop;nop;nop;
	nop;nop;nop;nop;

	!!! 6. 61 DMA Memory Write Requests G (each 64 bytes)
	!!! 7. DMA Memory Write Requests H (any size)
		
#define DMA_ADDR_1 mpeval(0x00800000,16,16)
#define DMA_ADDR_2 mpeval(0x00900000,16,16)
DMAWR: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMAWR)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_1, DMA_ADDR_2, "64'h40", 3e )

	mov	200, %g2
delay_loop000:			! give denali a chance to send the dma writes
	dec	%g2
	cmp	%g2, 0
	bne	delay_loop000
	nop;nop;nop;nop
	nop;nop;nop;nop;
	
	!!! 8. CplD for Memory Read A
	!!! 9. Cpl for Cfg Write B
UnstallCpl: nop
! $EV trig_pc_d(1,@VA(.MAIN.UnstallCpl)) -> EnablePCIeIgCmd("UNSTALL_CPL", 0, 0, "64'h40",1)
		
	!!! Wait for the INTA following the last DMA Read completion
	setx	FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2
	mov	1000, %g3		! loop count
	mov	8, %g4			! INTA asserted bit
	
delay_loop1:
	ldx	[%g2], %g5
	cmp     %g4,%g5
	be	test_passed
	
	dec	%g3
	cmp	%g3, 0
	bne	delay_loop1
	nop

	ba	test_failed
	nop
	
/***********************************************************************
   Threads 2 - 7 go here
 ***********************************************************************/
th_main_2:
th_main_3:
th_main_4:
th_main_5:
th_main_6:
th_main_7:
        SYNC_THREAD_OTHER( %o1,%g1,%g2 )

	! short delay to allow threads 0 and 1 to do thier stuff

	mov	10, %g2
delay_loop2:
	dec	%g2
	cmp	%g2, 0
	bne	delay_loop2
	nop
	
th_1to7_join:	
	setx	MEM32_WR_ADDR, %g1, %g2
	sll	%l0, 24, %l1
	or	%l1, %g2, %g2

	!!! 3. 5 of the 35 Memory write requests C0-C34
	
	setx	0x2121212121212121, %g1, %g3
	stx	%g3, [%g2] 

	setx	0x2222222222222222, %g1, %g3
	stx	%g3, [%g2+8] 

	setx	0x2323232323232323, %g1, %g3
	stx	%g3, [%g2+16] 

	setx	0x2424242424242424, %g1, %g3
	stx	%g3, [%g2+24] 

	setx	0x3535353535353535, %g1, %g3
	stx	%g3, [%g2+32] 

	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD
	
/***********************************************************************
   Test case data start
 ***********************************************************************/

SECTION       .DATA DATA_VA=MEM32_RD_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}
.data	
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0x5051525354555657
	.xword 0x58595a5b5c5d5e5f

/************************************************************************
   Test case DMA data start.
************************************************************************/

SECTION       .DMADATA DATA_VA=DMA_DATA_ADDR
attr_data {     
      Name = .DMADATA,
      hypervisor,
      compressimage
}
.data
	init_mem(0x0101010201030104, 512, 8, +, 0, +, 0x0004000400040004)

	
/************************************************************************
   IOMMU TTE start
	TTE Format:
63:	48 DEV KEY	- set to 0
47:	39 reserved	- set to 0
38:	13 DATA PA	- set to VA for VA=RA
12:	7  DATA_SOFT	- set to 0
6:	5  reserved	- set to 0
5:	3  FNM MASK	- set to 0
2:	2  KEY VALID	- set to 0
1:	1  DATA_W	- set to 1
0:	0  DATA_V	- set to 1
************************************************************************/

SECTION       .DATA2 DATA_VA=IOMMU_TTE_ADDR
attr_data {     
      Name = .DATA2,
      hypervisor,
      compressimage
}

.data
	.skip 8*0x80
	
iommu_tte_addr:	
	init_mem(0x0000000000800003, 256, 8, +, 0, +, 0x0000000000010000)
	
/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeFireDeadlockScn1.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	#define ENABLE_PCIE_MPS_256
	40	#define MAIN_PAGE_HV_ALSO
	41
	42	#define H_HT0_Interrupt_0x60
	43	#define My_HT0_Interrupt_0x60 \
	44	call my_trap_code; \
	45	nop; \
	46	retry; \
	47	nop;
	48
	49	#include "hboot.s"
	50	#include "peu_defines.h"
	51	#include "ncu_defines.h"
	52	#include "cmp_macros.h"
	53
	54	#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	55	#define MEM32_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	56	#define CFG1_WR_ADDR mpeval((N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA) \| CFG1_ACCESS_PA)
	57
	58	#define DMA_DATA_ADDR 0x00800000
	59
	60	#define IOMMU_TTE_ADDR 0x40000000
	61
	62	! Bit 8 = Page Size: 0=8KB, 1=64KB; Bits 3:0 = TSB Table size: 6=64k entries
	63	#define MMU_TSB_CNTRL_REG_DATA mpeval(IOMMU_TTE_ADDR \| 0x100 \| 6)
	64
65	#define NCU_IOMMU_INVALIDATE_REG_ADDR 0x8000002030
66
67	/************************************************************************
68	Test case code start
69	************************************************************************/
70	SECTION .MAIN
71	.text
72	.global main
73
74	main:
75	ta T_CHANGE_HPRIV
76	nop
77
78	th_fork(th_main, %l0)
79
80	th_main_0:
81	! enable interrupts & provide basic handler
82	#include "piu_rupt_enable.s"
83
84	StallCpl: nop
85	! $EV trig_pc_d(1,@VA(.MAIN.StallCpl)) -> EnablePCIeIgCmd("STALL_CPL", 0, 0, "64'h40",1)
86
87	! set the Traffic Class for all the DMA R&W TLPs to 5, so denali doesn't
88	! send them out of order
89	settc: nop ! $EV trig_pc_d(1, @VA(.MAIN.settc)) -> EnablePCIeIgCmd ("SET_TC", 5, 0, 0, 1 )
90
91	SYNC_THREAD_MAIN( test_failed, %g1, %g2, %g3 )
92
93	!!! 1. Do a Memory Read request A
94
95	setx MEM32_RD_ADDR, %g1, %g2
96	ldx [%g2], %l1 ! completion on this PIO READ will stall
97
98	ldx [%g2+8], %l2
99
100	ldx [%g2+16],%l3
101
102	ldx [%g2+24],%l4
103
104	ldx [%g2+32],%l5
105
106	ba test_passed
107	nop
108
109	/************************************************************************
110	Thread 1 will issue the PIO Memory Write requests
111	************************************************************************/
112	th_main_1:
113
114	! enable SUN4U translation in the IOMMU
115
116	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
117	setx 0x00301, %g1, %g3 ! 9:8 11 = Cache enabled, 0: 1 = translation enabled
118	stx %g3, [%g2]
119	ldx [%g2], %g3
120
121	! load address of the TSB table, and the page size (64KB)
122
123	setx FIRE_DLC_MMU_CSR_A_TSB_ADDR, %g1, %g2
124	setx MMU_TSB_CNTRL_REG_DATA, %g1, %g3
125	stx %g3, [%g2]
126	ldx [%g2], %g3
127
128	SYNC_THREAD_OTHER( %o1,%g1,%g2 )
129
130	!!! 2. Cfg Write Request B
131
132	mov 5, %g2
133	delay_loop: ! give thread 0 a chance to do the memory read pio
134	dec %g2
135	cmp %g2, 0
136	bne delay_loop
137	nop
138
139	setx CFG1_WR_ADDR, %g1, %g2
140	setx 0x11223344, %g1, %l1
141	stw %l1, [%g2] ! this PIO write will stall due to NPWR_EN
142
143	!!! 3. 5 of the 35 Memory write requests C0-C34
144
145	setx MEM32_RD_ADDR, %g1, %g2
146	sll %l0, 24, %l1
147	or %l1, %g2, %g2
148
149	setx 0x1111111111111111, %g1, %g3
150	stx %g3, [%g2]
151
152	setx 0x1212121212121212, %g1, %g3
153	stx %g3, [%g2+8]
154
155	setx 0x1313131313131313, %g1, %g3
156	stx %g3, [%g2+16]
157
158	setx 0x1414141414141414, %g1, %g3
159	stx %g3, [%g2+24]
160
161	setx 0x1515151515151515, %g1, %g3
162	stx %g3, [%g2+32]
163
164	mov 30, %g2
165	delay_loop0:
166	dec %g2
167	cmp %g2, 0
168	bne delay_loop0
169	nop;nop;nop;nop
170
171	!!! 4. DMA Memory Read Requests E (4k byte total)
172
173	#define DMARD_ADDR_1 mpeval(0x00800000,16,16)
174	DMARD1: nop
175	! $EV trig_pc_d(1,@VA(.MAIN.DMARD1)) -> EnablePCIeIgCmd("DMARD", DMARD_ADDR_1, DMARD_ADDR_1, "64'h1000",1)
176
177	!!! 5. DMA Memory Read Request F (any size)
178
179	#define DMARD_ADDR_2 mpeval(0x00801000,16,16)
180	DMARD2: nop
181	! $EV trig_pc_d(1,@VA(.MAIN.DMARD2)) -> EnablePCIeIgCmd("DMARD_INTA", DMARD_ADDR_2, DMARD_ADDR_2, "64'h100",1)
182
183	mov 200, %g2
184	delay_loop00: ! give denali a chance to send the dma reads & L2 to respond
185	dec %g2
186	cmp %g2, 0
187	bne delay_loop00
188	nop;nop;nop;nop;
189	nop;nop;nop;nop;
190
191	!!! 6. 61 DMA Memory Write Requests G (each 64 bytes)
192	!!! 7. DMA Memory Write Requests H (any size)
193
194	#define DMA_ADDR_1 mpeval(0x00800000,16,16)
195	#define DMA_ADDR_2 mpeval(0x00900000,16,16)
196	DMAWR: nop
197	! $EV trig_pc_d(1,@VA(.MAIN.DMAWR)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_1, DMA_ADDR_2, "64'h40", 3e )
198
199	mov 200, %g2
200	delay_loop000: ! give denali a chance to send the dma writes
201	dec %g2
202	cmp %g2, 0
203	bne delay_loop000
204	nop;nop;nop;nop
205	nop;nop;nop;nop;
206
207	!!! 8. CplD for Memory Read A
208	!!! 9. Cpl for Cfg Write B
209	UnstallCpl: nop
210	! $EV trig_pc_d(1,@VA(.MAIN.UnstallCpl)) -> EnablePCIeIgCmd("UNSTALL_CPL", 0, 0, "64'h40",1)
211
212	!!! Wait for the INTA following the last DMA Read completion
213	setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2
214	mov 1000, %g3 ! loop count
215	mov 8, %g4 ! INTA asserted bit
216
217	delay_loop1:
218	ldx [%g2], %g5
219	cmp %g4,%g5
220	be test_passed
221
222	dec %g3
223	cmp %g3, 0
224	bne delay_loop1
225	nop
226
227	ba test_failed
228	nop
229
230	/***********************************************************************
231	Threads 2 - 7 go here
232	***********************************************************************/
233	th_main_2:
234	th_main_3:
235	th_main_4:
236	th_main_5:
237	th_main_6:
238	th_main_7:
239	SYNC_THREAD_OTHER( %o1,%g1,%g2 )
240
241	! short delay to allow threads 0 and 1 to do thier stuff
242
243	mov 10, %g2
244	delay_loop2:
245	dec %g2
246	cmp %g2, 0
247	bne delay_loop2
248	nop
249
250	th_1to7_join:
251	setx MEM32_WR_ADDR, %g1, %g2
252	sll %l0, 24, %l1
253	or %l1, %g2, %g2
254
255	!!! 3. 5 of the 35 Memory write requests C0-C34
256
257	setx 0x2121212121212121, %g1, %g3
258	stx %g3, [%g2]
259
260	setx 0x2222222222222222, %g1, %g3
261	stx %g3, [%g2+8]
262
263	setx 0x2323232323232323, %g1, %g3
264	stx %g3, [%g2+16]
265
266	setx 0x2424242424242424, %g1, %g3
267	stx %g3, [%g2+24]
268
269	setx 0x3535353535353535, %g1, %g3
270	stx %g3, [%g2+32]
271
272
273	test_passed:
274	EXIT_GOOD
275
276	test_failed:
277	EXIT_BAD
278
279	/***********************************************************************
280	Test case data start
281	***********************************************************************/
282
283	SECTION .DATA DATA_VA=MEM32_RD_ADDR
284	attr_data {
285	Name = .DATA,
286	hypervisor,
287	compressimage
288	}
289	.data
290	.xword 0x1011121314151617
291	.xword 0x18191a1b1c1d1e1f
292	.xword 0x2021222324252627
293	.xword 0x28292a2b2c2d2e2f
294	.xword 0x3031323334353637
295	.xword 0x38393a3b3c3d3e3f
296	.xword 0x4041424344454647
297	.xword 0x48494a4b4c4d4e4f
298	.xword 0x5051525354555657
299	.xword 0x58595a5b5c5d5e5f
300
301	/************************************************************************
302	Test case DMA data start.
303	************************************************************************/
304
305	SECTION .DMADATA DATA_VA=DMA_DATA_ADDR
306	attr_data {
307	Name = .DMADATA,
308	hypervisor,
309	compressimage
310	}
311	.data
312	init_mem(0x0101010201030104, 512, 8, +, 0, +, 0x0004000400040004)
313
314
315	/************************************************************************
316	IOMMU TTE start
317	TTE Format:
318	63: 48 DEV KEY - set to 0
319	47: 39 reserved - set to 0
320	38: 13 DATA PA - set to VA for VA=RA
321	12: 7 DATA_SOFT - set to 0
322	6: 5 reserved - set to 0
323	5: 3 FNM MASK - set to 0
324	2: 2 KEY VALID - set to 0
325	1: 1 DATA_W - set to 1
326	0: 0 DATA_V - set to 1
327	************************************************************************/
328
329	SECTION .DATA2 DATA_VA=IOMMU_TTE_ADDR
330	attr_data {
331	Name = .DATA2,
332	hypervisor,
333	compressimage
334	}
335
336	.data
337	.skip 8*0x80
338
339	iommu_tte_addr:
340	init_mem(0x0000000000800003, 256, 8, +, 0, +, 0x0000000000010000)
341
342	/************************************************************************/