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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeHotRst.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeHotRst.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39#define MAIN_PAGE_HV_ALSO
40#define RESET_STAT_CHECK
41#define RESET_CHECK_REG
42
43#include "hboot.s"
44#include "peu_defines.h"
45#include "dmu_peu_regs.h"
46#include "rst_defines.h"
47
48#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) | IO_ACCESS_PA)
49
50#define DMA_DATA_ADDR 0x0000000123457000
51#define DMA_DATA_BYP_ADDR1 0xfffc000123457000
52#define DMA_DATA_BYP_ADDR2 0xfffc000123457100
53#define DMA_DATA_BYP_ADDR3 0xfffc000123457200
54#define DMA_DATA_BYP_ADDR4 0xfffc000123457300
55
56/*
57Test case code start
58*/
59.text
60.global main
61
62main:
63 ta T_CHANGE_HPRIV
64 nop
65
66/************************************************************
67 Check if this is the first time thru here
68 ************************************************************/
69 setx test_entered, %g1, %g2
70 ldx [%g2], %g3
71 brnz %g3, After_Warm_Reset
72 nop
73
74! First time thru, Store a non-zero value there
75 dec %g3
76 stx %g3, [%g2]
77
78/************************************************************
79 Hot Reset
80 ************************************************************/
81Set_Detect_Quiet:
82 ! set bit to remain in Detect.Quiet state
83 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
84 ldx [%g3], %g4
85 mov 0x100, %g5
86 orcc %g5, %g4, %g5 ! OR in bit 8 == 1
87 stx %g5, [%g3]
88 ldx [%g3], %g4
89
90Set_RESET_ASSERT:
91 ! set RESET.ASSERT bit to 1
92 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g1, %g2 ! 0x680000
93 ldx [%g2], %g4
94 or %g4,0x001, %l0 ! OR in the RESET.ASSERT bit
95
96 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3 ! 0x680000
97 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g4 ! 0x681018
98 ldx [%g4], %l4 ! read the PEU Other Event Status Clear Reg
99 stx %l4, [%g4] ! clear the PEU Other Event Status Clear Reg
100 mov 25, %l1 ! loop timeout count
101 setx 0x0000020000000200, %g1, %g5 ! mask for Link Down Primary & Secondary events
102
103 stx %l0, [%g2] ! set RESET.ASSERT
104
105! Wait for Link Down primary or secondary event before doing a Warm Reset
106Wait4LinkDown:
107 ldx [%g2], %l2 ! read the Link Control reg to see if RESET.ASSERT is still set
108 ldx [%g3 + 8], %l3 ! read the PEU Status Reg
109 ldx [%g4], %l4 ! read the PEU Other Event Status Clear Reg
110 andcc %l4, %g5, %l5
111 bne %xcc, do_WARM_RESET
112 nop
113 dec %l1
114 brnz %l1, Wait4LinkDown
115 nop
116 b test_failed
117 nop
118
119/************************************************************
120 Now do WARM RESET
121 ************************************************************/
122do_WARM_RESET:
123 stx %l4, [%g4] ! clear the PEU Other Event Status Clear Reg
124
125#ifdef PCIE_USE_SSYS_RESET
126 setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg
127 mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data
128 stx %g7, [%g5] ! Subsystem Reset
129
130 mov 255, %l0 ! loop timeout count
131
132Wait4SsysReset:
133 ldx [%g5], %l7 ! check if reset bit has cleared
134 brz %l7, redo_link_training
135 nop
136 dec %l0
137 brnz %l0, Wait4SsysReset
138 nop
139 ba test_failed ! Subsystem reset should have completed
140 nop
141/************************************************************
142 Now redo link training...
143 ************************************************************/
144redo_link_training:
145 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3
146 ldx [%g3], %g4
147 mov 0x0010, %g5 ! FAST LINK MODE, for simulation.
148 or %g4, %g5, %g5
149 stx %g5, [%g3]
150
151 ! clear bit 8, to not remain in Detect.Quiet state
152 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
153 mov 0x001, %l4
154 stx %l4, [%g3]
155
156 ! enable bypass in IOMMU
157 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
158 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
159 stx %g3, [%g2]
160
161! wait for the "Link Up" status bit to get set in the PEU
162! (this code copied from peu_init.h)
163
164 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
165 ldx [%g3], %l4
166 stx %l4, [%g3] ! clear any status bits that are set
167 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
168 mov 255, %l0
169 mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1
170
171LinkTrainingLoop2:
172 ldx [%g3], %l4 ! bit 8 is Link Up primary event
173 ldx [%g4], %l5 ! bits 48:44 are the LTSSM state
174 andcc %l1, %l4, %l4
175 bne After_Warm_Reset
176 nop
177
178 dec %l0
179 brnz %l0, LinkTrainingLoop2
180 nop
181 b test_failed
182 nop
183
184#else
185 setx RST_RESET_GEN, %g1, %g5 ! warm reset reg
186 mov RST_RESET_GEN__WMR_GEN, %g7 ! warm reset reg data
187 mov 25, %l0 ! loop timeout count
188
189 stx %g7, [%g5] ! Warm Reset
190 ldx [%g5], %g7
191
192Wait4WarmReset:
193 dec %l0
194 brnz %l0, Wait4WarmReset
195 nop
196 ba test_failed ! Warm reset should have happened
197 nop
198#endif
199
200/*********************************************************************
201 Do a couple of PIOs and DMAs to verify that the link is working fine.
202 *********************************************************************/
203After_Warm_Reset:
204 nop
205 nop
206! $EV trig_pc_d(1, @VA(.MAIN.After_Warm_Reset)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR2, "64'h40", 1 )
207After_Warm_Reset2:
208 nop
209 nop
210! $EV trig_pc_d(1, @VA(.MAIN.After_Warm_Reset2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR4, "64'h40", 1 )
211
212 ! Do PIOs to IO address space
213 ! load byte - all byte offsets within an octlet
214 setx IO_RD_ADDR, %g1, %g2
215 ldub [%g2 + 1*8 + 0], %l0
216 ldub [%g2 + 2*8 + 1], %l1
217 ldub [%g2 + 3*8 + 2], %l2
218 ldub [%g2 + 4*8 + 3], %l3
219 ldub [%g2 + 5*8 + 4], %l4
220 ldub [%g2 + 6*8 + 5], %l5
221 ldub [%g2 + 7*8 + 6], %l6
222 ldub [%g2 + 8*8 + 7], %l7
223
224test_passed:
225 EXIT_GOOD
226
227test_failed:
228 EXIT_BAD
229
230
231/************************************************************************
232 Test case data start
233************************************************************************/
234 .align 64
235test_entered:
236 .xword 0
237
238
239SECTION .PIODATA DATA_VA=IO_RD_ADDR
240attr_data {
241 Name = .PIODATA,
242 hypervisor,
243 compressimage
244}
245
246.data
247 .xword 0xdeadbeefdeadbeef
248
249 .xword 0x1101010101010101
250 .xword 0x0122010101010101
251 .xword 0x0101330101010101
252 .xword 0x0101014401010101
253 .xword 0x0101010155010101
254 .xword 0x0101010101660101
255 .xword 0x0101010101017701
256 .xword 0x0101010101010188
257
258 .xword 0x1122010101010101
259 .xword 0x0101334401010101
260 .xword 0x0101010155660101
261 .xword 0x0101010101017788
262
263 .xword 0x1122334401010101
264 .xword 0x0101010155667788
265
266 .xword 0xdeadbeefdeadbeef
267
268/************************************************************************/
269
270SECTION .DMADATA DATA_VA=DMA_DATA_ADDR
271attr_data {
272 Name = .DMADATA,
273 hypervisor,
274 compressimage
275}
276
277.data
278 init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004)
Full OpenSPARC design & verification tarball including full HDL.