[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeIgrHPeDrainState.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeIgrHPeDrainState.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING    
#define MAIN_PAGE_HV_ALSO

#ifndef PCIE_USE_SSYS_RESET
#define RESET_STAT_CHECK
#define RESET_CHECK_REG
#define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler
#endif

#define H_HT0_Data_access_error_0x32
#define SUN_H_HT0_Data_access_error_0x32 \
	inc     %l4; \
	done;

#include "hboot.s"
#include "peu_defines.h"
#include "dmu_peu_regs.h"
#include "rst_defines.h"

#define MEM_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
#define DMA_DATA_ADDR   	0x0000000123456000
#define DMARD_ADDR1		0xfffc000123456000
#define DMARD_ADDR2		0xfffc000123457000
#define DMARD_ADDR3		0xfffc000123458000
#define DMARD_ADDR4		0xfffc000123459000

/*
Test case code start
*/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

/************************************************************
 Check if this is the first time thru here
 ************************************************************/
	setx	test_entered, %g1, %g2
	ldx	[%g2], %g3
	brnz	%g3, After_Warm_Reset
	nop
	
! First time thru, Store a non-zero value there 
	dec	%g3
	stx	%g3, [%g2]
	
/************************************************************
 make sure the detect.quiet bit is set
 ************************************************************/
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
	ldx	[%g3], %g4
	mov	0x100, %g5
        orcc    %g5, %g4, %g5	! OR in bit 8 == 1
	stx	%g5, [%g3]
	ldx	[%g3], %g4
	
/************************************************************
 Fire off some PIOs and DMA Reads, then bring down the link.
 ************************************************************/
Start_PIOs_and_DMARDs:
	setx	MEM_WR_ADDR, %g1, %g2
	setx	0x3335373992828384, %g1, %l0
	stb	%l0, [%g2]
	sth	%l0, [%g2 + 4]
	stw	%l0, [%g2 + 8]
	ldx	[%g2], %l1

! here is where we force an error
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
        ldx	[%g3], %l3
        stx	%l3, [%g3]	! clear any OE status bits

! This user event will force the next PIO to NOT to call expectPCIE().
! $EV trig_pc_d(1,@VA(.MAIN.Check_drain_state)) -> EnablePCIeIgCmd("PIO_NOEXP",0,0,0,1)
	
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_ADDR, %g1, %g4
	best_set_reg( 0x00000f20, %g1, %l4 )
Setup_IHB_Err_Inject:
	nop
        stx	%l4, [%g4]	! set the IHP error injection triggers
	mov	0, %l4
	
	ldx	[%g2 + 16], %l0		! PIO read ===> should get the IHP error
	
	dec	%l4			! an interrupt should have occured
	brnz    %l4, test_failed
	

! now wait for the "Igress hdr buffer Parity Error" primary or secondary status to be set
	setx	FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR, %g1, %g3
	mov	10, %l0
        setx	0x0000001000000010, %g1, %l1	! mask for IHP Primary and Secondary Events

Wait_for_IHP:
        ldx	[%g3], %l3
        andcc   %l1, %l3, %l4
        bne     %xcc, Check_drain_state
	nop
	dec	%l0
	brnz	%l0, Wait_for_IHP
	nop
	b       test_failed
	nop
	
/****************************************************************
 check that drain.state bit is NOT set in the PEU Status Register
 ****************************************************************/
Check_drain_state:
	mov	0, %g1
	stx	%g1, [%g4]	! clear the EDP error injection triggers
	
! This user event will force the next PIO to NOT to call expectPCIE().
! $EV trig_pc_d(1,@VA(.MAIN.Check_drain_state)) -> EnablePCIeIgCmd("PIO_NOEXP",0,0,0,1)
	
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR, %g1, %g3
	ldx	[%g3], %g4
	mov	0x100, %g5
	andcc   %g4, %g5, %l0
	bnz	test_failed		! branch if drain state IS set
	nop	
	
	! issue PIO read request(s) - these should complete with Bus Error
	mov	0, %l4
	setx	MEM_WR_ADDR, %g1, %g4
PioBusErr:
	ldx	[%g4], %l3		! ==> this should get a bus error

	dec	%l4			! <== only one interrupt expected
	brnz    %l4, test_failed
	
	! insure that no outstanding DMA read requests are outstanding
	! by checking that there are no entries on the Transaction Scoreboard
	setx	FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR, %g1, %g5
	mov	0, %l0
	dec	%l0
	mov	0x01, %l1
	xor	%l1, %l0, %l1
Wait_for_dma_read_clear:
	ldx	[%g5], %l4
	andcc	%l4, %l1, %l2
	bnz     Wait_for_dma_read_clear
	
	! clear the IHP err bit
	setx	FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR, %g1, %g3
        ldx	[%g3], %l3
	stx	%l3, [%g3]		! RW1C
        ldx	[%g3], %l1
	brnz	%l1, test_failed	! branch if IHP err is not cleared
	nop
	
	! clear the drain bit - its also a RW1C bit
	mov	0x100, %g5
	stx	%g5, [%g3]		! RW1C
	ldx	[%g3], %g4
	andcc   %g4, %g5, %g4
	bnz	test_failed		! branch if drain state is not cleared
	nop
	
/************************************************************
 do the warm reset
 ************************************************************/
do_WARM_RESET:
! xxx trig_pc_d(1,@VA(.MAIN.do_WARM_RESET)) -> EnablePCIeIgCmd("SOFTRESET",0,0,0,1)
	
#ifdef PCIE_USE_SSYS_RESET
        setx    RST_SSYS_RESET, %g1, %g5	! subsystem reset reg
        mov	RST_SSYS_RESET__DMU_PEU, %g7	! subsystem reset reg data
        stx     %g7, [%g5]			! Subsystem Reset
	
	mov	10, %l0				! loop timeout count
	
Wait4SsysReset:
	ldx     [%g5], %l7		!  check if reset bit has cleared
	brz	%l7, redo_link_training
	nop
	dec	%l0
	brnz	%l0, Wait4SsysReset
	nop
	ba	test_failed		! Subsystem reset should have completed
	nop
/************************************************************
 Now redo link training...
 ************************************************************/
redo_link_training:
        setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3
	ldx	[%g3], %g4
        mov     0x0010, %g5	! FAST LINK MODE, for simulation.
	or	%g4, %g5, %g5
        stx     %g5, [%g3]

	! clear bit 8, to not remain in Detect.Quiet state
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
	mov	0x001, %l4
	stx	%l4, [%g3]

	! enable bypass in IOMMU
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
	setx	FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
	stx	%g3, [%g2]

! wait for the "Link Up" status bit to get set in the PEU
! (this code copied from peu_init.h)
	
        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
        ldx	[%g3], %l4
        stx	%l4, [%g3]		! clear any status bits that are set
        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
	mov	255, %l0
        mov	FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1

LinkTrainingLoop2:
        ldx	[%g3], %l4		! bit 8 is Link Up primary event
        ldx	[%g4], %l5		! bits 48:44 are the LTSSM state
        andcc   %l1, %l4, %l4
        bne     After_Warm_Reset
	nop

	dec	%l0
	brnz	%l0, LinkTrainingLoop2
	nop
	b       test_failed
	nop

#else
        setx    RST_RESET_GEN, %g1, %g5	! warm reset reg
        mov	RST_RESET_GEN__WMR_GEN, %g7	! warm reset reg data
	mov	255, %l0		! loop timeout count
	
        stx     %g7, [%g5]		! Warm Reset
        ldx     [%g5], %g7
	
Wait4WarmReset:
	dec	%l0
	brnz	%l0, Wait4WarmReset
	nop
	ba	test_failed		! Warm reset should have happened
	nop
#endif	

/********************************************************************
 Do a couple of PIOs and DMAs to verify that the PCIe link is working.
 ********************************************************************/
After_Warm_Reset:
	nop
	! clear any error bits from from the DLPL Status reg
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
	ldx	[%g6], %l7
	stx	%l7, [%g6]		! RW1C
	ldx	[%g6], %l7
	brnz	%l7, test_failed	! branch if it is not cleared
	nop
	
DmaRd5:	nop
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd5)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR2,DMARD_ADDR2,"64'h40",1)
	setx	MEM_WR_ADDR, %g1, %g5
	mov	0, %l4
	stx	%g3, [%g5]		! 3 PIO Writes
	stx	%g4, [%g5+8]
	stx	%g5, [%g5+16]
DmaRd6:	nop
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd6)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR3,DMARD_ADDR3,"64'h40",1)
	ldx	[%g5], %l0		! 3 PIO Reads
	ldx	[%g5+8], %l1
	ldx	[%g5+16], %l2
	
DmaRd7:	nop
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd7)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR4,DMARD_ADDR4,"64'h40",1)
        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
        ldx	[%g3], %l5		! bit 8 is Link Up primary event
	
        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
        ldx	[%g4], %l6		! bits 48:44 are the LTSSM state
	
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
	ldx	[%g6], %l7		! dlpl status
	
	brnz    %l4, test_failed	! no interrupts were expected
	nop
	nop
		
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
 Test case data start
 ************************************************************************/
	.align 64
test_entered:
	.xword 0


SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}
.data
	init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004)
/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeIgrHPeDrainState.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#ifndef PCIE_USE_SSYS_RESET
	42	#define RESET_STAT_CHECK
	43	#define RESET_CHECK_REG
	44	#define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler
	45	#endif
	46
	47	#define H_HT0_Data_access_error_0x32
	48	#define SUN_H_HT0_Data_access_error_0x32 \
	49	inc %l4; \
	50	done;
	51
	52	#include "hboot.s"
	53	#include "peu_defines.h"
	54	#include "dmu_peu_regs.h"
	55	#include "rst_defines.h"
	56
	57	#define MEM_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	58	#define DMA_DATA_ADDR 0x0000000123456000
	59	#define DMARD_ADDR1 0xfffc000123456000
	60	#define DMARD_ADDR2 0xfffc000123457000
	61	#define DMARD_ADDR3 0xfffc000123458000
	62	#define DMARD_ADDR4 0xfffc000123459000
	63
	64	/*
65	Test case code start
66	*/
67	.text
68	.global main
69
70	main:
71	ta T_CHANGE_HPRIV
72	nop
73
74	/************************************************************
75	Check if this is the first time thru here
76	************************************************************/
77	setx test_entered, %g1, %g2
78	ldx [%g2], %g3
79	brnz %g3, After_Warm_Reset
80	nop
81
82	! First time thru, Store a non-zero value there
83	dec %g3
84	stx %g3, [%g2]
85
86	/************************************************************
87	make sure the detect.quiet bit is set
88	************************************************************/
89	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
90	ldx [%g3], %g4
91	mov 0x100, %g5
92	orcc %g5, %g4, %g5 ! OR in bit 8 == 1
93	stx %g5, [%g3]
94	ldx [%g3], %g4
95
96	/************************************************************
97	Fire off some PIOs and DMA Reads, then bring down the link.
98	************************************************************/
99	Start_PIOs_and_DMARDs:
100	setx MEM_WR_ADDR, %g1, %g2
101	setx 0x3335373992828384, %g1, %l0
102	stb %l0, [%g2]
103	sth %l0, [%g2 + 4]
104	stw %l0, [%g2 + 8]
105	ldx [%g2], %l1
106
107	! here is where we force an error
108	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
109	ldx [%g3], %l3
110	stx %l3, [%g3] ! clear any OE status bits
111
112	! This user event will force the next PIO to NOT to call expectPCIE().
113	! $EV trig_pc_d(1,@VA(.MAIN.Check_drain_state)) -> EnablePCIeIgCmd("PIO_NOEXP",0,0,0,1)
114
115	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_ADDR, %g1, %g4
116	best_set_reg( 0x00000f20, %g1, %l4 )
117	Setup_IHB_Err_Inject:
118	nop
119	stx %l4, [%g4] ! set the IHP error injection triggers
120	mov 0, %l4
121
122	ldx [%g2 + 16], %l0 ! PIO read ===> should get the IHP error
123
124	dec %l4 ! an interrupt should have occured
125	brnz %l4, test_failed
126
127
128	! now wait for the "Igress hdr buffer Parity Error" primary or secondary status to be set
129	setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR, %g1, %g3
130	mov 10, %l0
131	setx 0x0000001000000010, %g1, %l1 ! mask for IHP Primary and Secondary Events
132
133	Wait_for_IHP:
134	ldx [%g3], %l3
135	andcc %l1, %l3, %l4
136	bne %xcc, Check_drain_state
137	nop
138	dec %l0
139	brnz %l0, Wait_for_IHP
140	nop
141	b test_failed
142	nop
143
144	/****************************************************************
145	check that drain.state bit is NOT set in the PEU Status Register
146	****************************************************************/
147	Check_drain_state:
148	mov 0, %g1
149	stx %g1, [%g4] ! clear the EDP error injection triggers
150
151	! This user event will force the next PIO to NOT to call expectPCIE().
152	! $EV trig_pc_d(1,@VA(.MAIN.Check_drain_state)) -> EnablePCIeIgCmd("PIO_NOEXP",0,0,0,1)
153
154	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR, %g1, %g3
155	ldx [%g3], %g4
156	mov 0x100, %g5
157	andcc %g4, %g5, %l0
158	bnz test_failed ! branch if drain state IS set
159	nop
160
161	! issue PIO read request(s) - these should complete with Bus Error
162	mov 0, %l4
163	setx MEM_WR_ADDR, %g1, %g4
164	PioBusErr:
165	ldx [%g4], %l3 ! ==> this should get a bus error
166
167	dec %l4 ! <== only one interrupt expected
168	brnz %l4, test_failed
169
170	! insure that no outstanding DMA read requests are outstanding
171	! by checking that there are no entries on the Transaction Scoreboard
172	setx FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR, %g1, %g5
173	mov 0, %l0
174	dec %l0
175	mov 0x01, %l1
176	xor %l1, %l0, %l1
177	Wait_for_dma_read_clear:
178	ldx [%g5], %l4
179	andcc %l4, %l1, %l2
180	bnz Wait_for_dma_read_clear
181
182	! clear the IHP err bit
183	setx FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR, %g1, %g3
184	ldx [%g3], %l3
185	stx %l3, [%g3] ! RW1C
186	ldx [%g3], %l1
187	brnz %l1, test_failed ! branch if IHP err is not cleared
188	nop
189
190	! clear the drain bit - its also a RW1C bit
191	mov 0x100, %g5
192	stx %g5, [%g3] ! RW1C
193	ldx [%g3], %g4
194	andcc %g4, %g5, %g4
195	bnz test_failed ! branch if drain state is not cleared
196	nop
197
198	/************************************************************
199	do the warm reset
200	************************************************************/
201	do_WARM_RESET:
202	! xxx trig_pc_d(1,@VA(.MAIN.do_WARM_RESET)) -> EnablePCIeIgCmd("SOFTRESET",0,0,0,1)
203
204	#ifdef PCIE_USE_SSYS_RESET
205	setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg
206	mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data
207	stx %g7, [%g5] ! Subsystem Reset
208
209	mov 10, %l0 ! loop timeout count
210
211	Wait4SsysReset:
212	ldx [%g5], %l7 ! check if reset bit has cleared
213	brz %l7, redo_link_training
214	nop
215	dec %l0
216	brnz %l0, Wait4SsysReset
217	nop
218	ba test_failed ! Subsystem reset should have completed
219	nop
220	/************************************************************
221	Now redo link training...
222	************************************************************/
223	redo_link_training:
224	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3
225	ldx [%g3], %g4
226	mov 0x0010, %g5 ! FAST LINK MODE, for simulation.
227	or %g4, %g5, %g5
228	stx %g5, [%g3]
229
230	! clear bit 8, to not remain in Detect.Quiet state
231	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
232	mov 0x001, %l4
233	stx %l4, [%g3]
234
235	! enable bypass in IOMMU
236	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
237	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
238	stx %g3, [%g2]
239
240	! wait for the "Link Up" status bit to get set in the PEU
241	! (this code copied from peu_init.h)
242
243	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
244	ldx [%g3], %l4
245	stx %l4, [%g3] ! clear any status bits that are set
246	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
247	mov 255, %l0
248	mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1
249
250	LinkTrainingLoop2:
251	ldx [%g3], %l4 ! bit 8 is Link Up primary event
252	ldx [%g4], %l5 ! bits 48:44 are the LTSSM state
253	andcc %l1, %l4, %l4
254	bne After_Warm_Reset
255	nop
256
257	dec %l0
258	brnz %l0, LinkTrainingLoop2
259	nop
260	b test_failed
261	nop
262
263	#else
264	setx RST_RESET_GEN, %g1, %g5 ! warm reset reg
265	mov RST_RESET_GEN__WMR_GEN, %g7 ! warm reset reg data
266	mov 255, %l0 ! loop timeout count
267
268	stx %g7, [%g5] ! Warm Reset
269	ldx [%g5], %g7
270
271	Wait4WarmReset:
272	dec %l0
273	brnz %l0, Wait4WarmReset
274	nop
275	ba test_failed ! Warm reset should have happened
276	nop
277	#endif
278
279	/********************************************************************
280	Do a couple of PIOs and DMAs to verify that the PCIe link is working.
281	********************************************************************/
282	After_Warm_Reset:
283	nop
284	! clear any error bits from from the DLPL Status reg
285	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
286	ldx [%g6], %l7
287	stx %l7, [%g6] ! RW1C
288	ldx [%g6], %l7
289	brnz %l7, test_failed ! branch if it is not cleared
290	nop
291
292	DmaRd5: nop
293	! $EV trig_pc_d(1, @VA(.MAIN.DmaRd5)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR2,DMARD_ADDR2,"64'h40",1)
294	setx MEM_WR_ADDR, %g1, %g5
295	mov 0, %l4
296	stx %g3, [%g5] ! 3 PIO Writes
297	stx %g4, [%g5+8]
298	stx %g5, [%g5+16]
299	DmaRd6: nop
300	! $EV trig_pc_d(1, @VA(.MAIN.DmaRd6)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR3,DMARD_ADDR3,"64'h40",1)
301	ldx [%g5], %l0 ! 3 PIO Reads
302	ldx [%g5+8], %l1
303	ldx [%g5+16], %l2
304
305	DmaRd7: nop
306	! $EV trig_pc_d(1, @VA(.MAIN.DmaRd7)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR4,DMARD_ADDR4,"64'h40",1)
307	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
308	ldx [%g3], %l5 ! bit 8 is Link Up primary event
309
310	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
311	ldx [%g4], %l6 ! bits 48:44 are the LTSSM state
312
313	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
314	ldx [%g6], %l7 ! dlpl status
315
316	brnz %l4, test_failed ! no interrupts were expected
317	nop
318	nop
319
320	test_passed:
321	EXIT_GOOD
322
323	test_failed:
324	EXIT_BAD
325
326
327	/************************************************************************
328	Test case data start
329	************************************************************************/
330	.align 64
331	test_entered:
332	.xword 0
333
334
335	SECTION .DATA DATA_VA=DMA_DATA_ADDR
336	attr_data {
337	Name = .DATA,
338	hypervisor,
339	compressimage
340	}
341	.data
342	init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004)
343	/************************************************************************/