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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeIntx.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeIntx.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
40#define MAIN_PAGE_HV_ALSO
41
42#include "hboot.s"
43#include "peu_defines.h"
44
45/************************************************************************
46 Test case code start
47 ************************************************************************/
48.text
49.global main
50
51main:
52 ta T_CHANGE_HPRIV
53 nop
54
55INTA_ASSERT_Evnt:
56 ! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1 )
57
58 ! now poll for INTA ASSERT
59
60 setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2
61 setx 0x008, %g1, %g3
62 setx 0x020, %g1, %g4
63
64delay_loop1:
65 ldx [%g2], %g5
66 cmp %g3,%g5
67 be INTA_DEASSERT_Evnt
68 nop
69 dec %g4
70 brnz %g4, delay_loop1
71 nop
72 b test_failed
73 nop
74
75INTA_DEASSERT_Evnt:
76 ! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 1 )
77
78 ! now poll for INTA DEASSERT
79
80 setx 0x000, %g1, %g3
81 setx 0x020, %g1, %g4
82
83delay_loop2:
84 ldx [%g2], %g5
85 cmp %g3,%g5
86 be INTB_ASSERT_Evnt
87 nop
88 dec %g4
89 brnz %g4, delay_loop2
90 nop
91 b test_failed
92 nop
93
94INTB_ASSERT_Evnt:
95 ! $EV trig_pc_d(1, @VA(.MAIN.INTB_ASSERT_Evnt)) -> EnablePCIeIgCmd ("INTB", 0, 0, "ASSERT", 1 )
96
97 ! now poll for INTB ASSERT
98
99 setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2
100 setx 0x004, %g1, %g3
101 setx 0x020, %g1, %g4
102
103delay_loop3:
104 ldx [%g2], %g5
105 cmp %g3,%g5
106 be INTB_DEASSERT_Evnt
107 nop
108 dec %g4
109 brnz %g4, delay_loop3
110 nop
111 b test_failed
112 nop
113
114INTB_DEASSERT_Evnt:
115 ! $EV trig_pc_d(1, @VA(.MAIN.INTB_DEASSERT_Evnt)) -> EnablePCIeIgCmd ("INTB", 0, 0, "DEASSERT", 1 )
116
117 ! now poll for INTB DEASSERT
118
119 setx 0x000, %g1, %g3
120 setx 0x020, %g1, %g4
121
122delay_loop4:
123 ldx [%g2], %g5
124 cmp %g3,%g5
125 be INTC_ASSERT_Evnt
126 nop
127 dec %g4
128 brnz %g4, delay_loop4
129 nop
130 b test_failed
131 nop
132
133INTC_ASSERT_Evnt:
134 ! $EV trig_pc_d(1, @VA(.MAIN.INTC_ASSERT_Evnt)) -> EnablePCIeIgCmd ("INTC", 0, 0, "ASSERT", 1 )
135
136 ! now poll for INTC ASSERT
137
138 setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2
139 setx 0x002, %g1, %g3
140 setx 0x020, %g1, %g4
141
142delay_loop5:
143 ldx [%g2], %g5
144 cmp %g3,%g5
145 be INTC_DEASSERT_Evnt
146 nop
147 dec %g4
148 brnz %g4, delay_loop5
149 nop
150 b test_failed
151 nop
152
153INTC_DEASSERT_Evnt:
154 ! $EV trig_pc_d(1, @VA(.MAIN.INTC_DEASSERT_Evnt)) -> EnablePCIeIgCmd ("INTC", 0, 0, "DEASSERT", 1 )
155
156 ! now poll for INTC DEASSERT
157
158 setx 0x000, %g1, %g3
159 setx 0x020, %g1, %g4
160
161delay_loop6:
162 ldx [%g2], %g5
163 cmp %g3,%g5
164 be INTD_ASSERT_Evnt
165 nop
166 dec %g4
167 brnz %g4, delay_loop6
168 nop
169 b test_failed
170 nop
171
172INTD_ASSERT_Evnt:
173 ! $EV trig_pc_d(1, @VA(.MAIN.INTD_ASSERT_Evnt)) -> EnablePCIeIgCmd ("INTD", 0, 0, "ASSERT", 1 )
174
175 ! now poll for INTD ASSERT
176
177 setx FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR, %g1, %g2
178 setx 0x001, %g1, %g3
179 setx 0x020, %g1, %g4
180
181delay_loop7:
182 ldx [%g2], %g5
183 cmp %g3,%g5
184 be INTD_DEASSERT_Evnt
185 nop
186 dec %g4
187 brnz %g4, delay_loop7
188 nop
189 b test_failed
190 nop
191
192INTD_DEASSERT_Evnt:
193 ! $EV trig_pc_d(1, @VA(.MAIN.INTD_DEASSERT_Evnt)) -> EnablePCIeIgCmd ("INTD", 0, 0, "DEASSERT", 1 )
194
195 ! now poll for INTD DEASSERT
196
197 setx 0x000, %g1, %g3
198 setx 0x020, %g1, %g4
199
200delay_loop8:
201 ldx [%g2], %g5
202 cmp %g3,%g5
203 be test_passed
204 nop
205 dec %g4
206 brnz %g4, delay_loop8
207 nop
208 b test_failed
209 nop
210
211test_passed:
212 EXIT_GOOD
213
214test_failed:
215 EXIT_BAD
216
217
Full OpenSPARC design & verification tarball including full HDL.