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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: PCIeIommu4V256mTr.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | #define ENABLE_PCIE_MPS_512 | |
40 | #define MAIN_PAGE_HV_ALSO | |
41 | ||
42 | #define H_HT0_Interrupt_0x60 | |
43 | #define My_HT0_Interrupt_0x60 \ | |
44 | call my_trap_code; \ | |
45 | nop; \ | |
46 | retry; \ | |
47 | nop; | |
48 | ||
49 | #include "hboot.s" | |
50 | #include "peu_defines.h" | |
51 | #include "ncu_defines.h" | |
52 | ||
53 | #define MEM32_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA) | |
54 | ||
55 | #define DMA_DATA_ADDR 0x01F000000 | |
56 | ||
57 | #define IOMMU_TTE_ADDR 0x008000000 | |
58 | ||
59 | ! Bits 6:4 = Page Size: 0=8KB, 1=64KB, 3=4MB, 5=256MB; Bits 3:0 = TSB Table size: 2=4k entries | |
60 | #define IOTSBDESC_1_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (5 << 4) | 0x2) | |
61 | ||
62 | ||
63 | /************************************************************************ | |
64 | Test case code start | |
65 | ************************************************************************/ | |
66 | .text | |
67 | .global main | |
68 | ||
69 | main: | |
70 | ta T_CHANGE_HPRIV | |
71 | nop | |
72 | ||
73 | ! enable interrupts & provide basic handler | |
74 | #include "piu_rupt_enable.s" | |
75 | ||
76 | ! enable SUN4U translation in the IOMMU | |
77 | ||
78 | write_mmu_ctl_reg: | |
79 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
80 | setx 0x00307, %g1, %g3 ! 9:8 11 = Cache enabled, | |
81 | ! 3: 1 = Busid Select, 1 = use busid[5:0] for DEV2IOTSB index | |
82 | ! 2: 1 = SUN4V enabled, | |
83 | ! 1: 1 = bypass enabled, | |
84 | ! 0: 1 = translation enabled | |
85 | stx %g3, [%g2] | |
86 | ldx [%g2], %g3 | |
87 | ||
88 | ! setup the DEV2IOTSB - the all busids map to IOTSBDESC ram entry 1 | |
89 | ! (currently it looks like the denali transactor (or vera wrapper) is generating | |
90 | ! a random busid, so map them all to IOTSB 1. | |
91 | ||
92 | write_dev2iotsb: | |
93 | setx FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR, %g1, %g2 | |
94 | setx 0x0101010101010101, %g1, %g3 | |
95 | stx %g3, [%g2 + 0x00] | |
96 | stx %g3, [%g2 + 0x08] | |
97 | stx %g3, [%g2 + 0x10] | |
98 | stx %g3, [%g2 + 0x18] | |
99 | stx %g3, [%g2 + 0x20] | |
100 | stx %g3, [%g2 + 0x28] | |
101 | stx %g3, [%g2 + 0x30] | |
102 | stx %g3, [%g2 + 0x38] | |
103 | stx %g3, [%g2 + 0x40] | |
104 | stx %g3, [%g2 + 0x48] | |
105 | stx %g3, [%g2 + 0x50] | |
106 | stx %g3, [%g2 + 0x58] | |
107 | stx %g3, [%g2 + 0x60] | |
108 | stx %g3, [%g2 + 0x68] | |
109 | stx %g3, [%g2 + 0x70] | |
110 | stx %g3, [%g2 + 0x78] | |
111 | ||
112 | ! setup entry 1 of the IOTSBDESC ram | |
113 | ||
114 | write_iotsbdesc: | |
115 | setx FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR, %g1, %g2 | |
116 | setx IOTSBDESC_1_DATA, %g1, %g3 | |
117 | stx %g3, [%g2 + 8] | |
118 | ldx [%g2], %g3 | |
119 | ||
120 | ||
121 | ! Trigger some DMA Reads of various lengths | |
122 | ||
123 | ! Created 09/19/2005 15:18:40 by /home/somePerson/bin/genDMAs.pl | |
124 | setx 0x1F000000, %g1, %g2 ! DMA start address | |
125 | setx 0x1F000000, %g1, %g3 ! page size | |
126 | #define DMA_ADDR_01 mpeval(0x001F000000 + 0,16,16) | |
127 | #define DMA_ADDR_02 mpeval(0x001F000000 + 64,16,16) | |
128 | #define DMA_ADDR_03 mpeval(0x801F000000 + 128,16,16) | |
129 | DMA0: nop | |
130 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA0)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_01, DMA_ADDR_02, "64'h100",1) | |
131 | stx %g2, [%g2] | |
132 | ldx [%g2 + 64], %g4 | |
133 | ldx [%g2 + 128], %g5 | |
134 | ldx [%g2 + 192], %g6 | |
135 | add %g2, %g3, %g2 | |
136 | #define DMA_ADDR_11 mpeval(0x002F000000 + 0,16,16) | |
137 | #define DMA_ADDR_12 mpeval(0x002F000000 + 64,16,16) | |
138 | #define DMA_ADDR_13 mpeval(0x802F000000 + 128,16,16) | |
139 | DMA1: nop | |
140 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA1)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_11, DMA_ADDR_12, "64'h100",1) | |
141 | stx %g2, [%g2] | |
142 | ldx [%g2 + 64], %g4 | |
143 | ldx [%g2 + 128], %g5 | |
144 | ldx [%g2 + 192], %g6 | |
145 | add %g2, %g3, %g2 | |
146 | #define DMA_ADDR_21 mpeval(0x003F000000 + 0,16,16) | |
147 | #define DMA_ADDR_22 mpeval(0x003F000000 + 64,16,16) | |
148 | #define DMA_ADDR_23 mpeval(0x803F000000 + 128,16,16) | |
149 | DMA2: nop | |
150 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA2)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_21, DMA_ADDR_22, "64'h100",1) | |
151 | stx %g2, [%g2] | |
152 | ldx [%g2 + 64], %g4 | |
153 | ldx [%g2 + 128], %g5 | |
154 | ldx [%g2 + 192], %g6 | |
155 | add %g2, %g3, %g2 | |
156 | #define DMA_ADDR_31 mpeval(0x004F000000 + 0,16,16) | |
157 | #define DMA_ADDR_32 mpeval(0x004F000000 + 64,16,16) | |
158 | #define DMA_ADDR_33 mpeval(0x804F000000 + 128,16,16) | |
159 | DMA3: nop | |
160 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA3)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_31, DMA_ADDR_32, "64'h100",1) | |
161 | stx %g2, [%g2] | |
162 | ldx [%g2 + 64], %g4 | |
163 | ldx [%g2 + 128], %g5 | |
164 | ldx [%g2 + 192], %g6 | |
165 | add %g2, %g3, %g2 | |
166 | #define DMA_ADDR_41 mpeval(0x005F000000 + 0,16,16) | |
167 | #define DMA_ADDR_42 mpeval(0x005F000000 + 64,16,16) | |
168 | #define DMA_ADDR_43 mpeval(0x805F000000 + 128,16,16) | |
169 | DMA4: nop | |
170 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA4)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_41, DMA_ADDR_42, "64'h100",1) | |
171 | stx %g2, [%g2] | |
172 | ldx [%g2 + 64], %g4 | |
173 | ldx [%g2 + 128], %g5 | |
174 | ldx [%g2 + 192], %g6 | |
175 | add %g2, %g3, %g2 | |
176 | #define DMA_ADDR_51 mpeval(0x006F000000 + 0,16,16) | |
177 | #define DMA_ADDR_52 mpeval(0x006F000000 + 64,16,16) | |
178 | #define DMA_ADDR_53 mpeval(0x806F000000 + 128,16,16) | |
179 | DMA5: nop | |
180 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA5)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_51, DMA_ADDR_52, "64'h100",1) | |
181 | stx %g2, [%g2] | |
182 | ldx [%g2 + 64], %g4 | |
183 | ldx [%g2 + 128], %g5 | |
184 | ldx [%g2 + 192], %g6 | |
185 | add %g2, %g3, %g2 | |
186 | #define DMA_ADDR_61 mpeval(0x007F000000 + 0,16,16) | |
187 | #define DMA_ADDR_62 mpeval(0x007F000000 + 64,16,16) | |
188 | #define DMA_ADDR_63 mpeval(0x807F000000 + 128,16,16) | |
189 | DMA6: nop | |
190 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA6)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_61, DMA_ADDR_62, "64'h100",1) | |
191 | stx %g2, [%g2] | |
192 | ldx [%g2 + 64], %g4 | |
193 | ldx [%g2 + 128], %g5 | |
194 | ldx [%g2 + 192], %g6 | |
195 | add %g2, %g3, %g2 | |
196 | #define DMA_ADDR_71 mpeval(0x008F000000 + 0,16,16) | |
197 | #define DMA_ADDR_72 mpeval(0x008F000000 + 64,16,16) | |
198 | #define DMA_ADDR_73 mpeval(0x808F000000 + 128,16,16) | |
199 | DMA7: nop | |
200 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA7)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_71, DMA_ADDR_72, "64'h100",1) | |
201 | stx %g2, [%g2] | |
202 | ldx [%g2 + 64], %g4 | |
203 | ldx [%g2 + 128], %g5 | |
204 | ldx [%g2 + 192], %g6 | |
205 | add %g2, %g3, %g2 | |
206 | #define DMA_ADDR_81 mpeval(0x009F000000 + 0,16,16) | |
207 | #define DMA_ADDR_82 mpeval(0x009F000000 + 64,16,16) | |
208 | #define DMA_ADDR_83 mpeval(0x809F000000 + 128,16,16) | |
209 | DMA8: nop | |
210 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA8)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_81, DMA_ADDR_82, "64'h100",1) | |
211 | stx %g2, [%g2] | |
212 | ldx [%g2 + 64], %g4 | |
213 | ldx [%g2 + 128], %g5 | |
214 | ldx [%g2 + 192], %g6 | |
215 | add %g2, %g3, %g2 | |
216 | #define DMA_ADDR_91 mpeval(0x00aF000000 + 0,16,16) | |
217 | #define DMA_ADDR_92 mpeval(0x00aF000000 + 64,16,16) | |
218 | #define DMA_ADDR_93 mpeval(0x80aF000000 + 128,16,16) | |
219 | DMA9: nop | |
220 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA9)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_91, DMA_ADDR_92, "64'h100",1) | |
221 | stx %g2, [%g2] | |
222 | ldx [%g2 + 64], %g4 | |
223 | ldx [%g2 + 128], %g5 | |
224 | ldx [%g2 + 192], %g6 | |
225 | add %g2, %g3, %g2 | |
226 | #define DMA_ADDR_101 mpeval(0x00bF000000 + 0,16,16) | |
227 | #define DMA_ADDR_102 mpeval(0x00bF000000 + 64,16,16) | |
228 | #define DMA_ADDR_103 mpeval(0x80bF000000 + 128,16,16) | |
229 | DMA10: nop | |
230 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA10)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_101, DMA_ADDR_102, "64'h100",1) | |
231 | stx %g2, [%g2] | |
232 | ldx [%g2 + 64], %g4 | |
233 | ldx [%g2 + 128], %g5 | |
234 | ldx [%g2 + 192], %g6 | |
235 | add %g2, %g3, %g2 | |
236 | #define DMA_ADDR_111 mpeval(0x00cF000000 + 0,16,16) | |
237 | #define DMA_ADDR_112 mpeval(0x00cF000000 + 64,16,16) | |
238 | #define DMA_ADDR_113 mpeval(0x80cF000000 + 128,16,16) | |
239 | DMA11: nop | |
240 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA11)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_111, DMA_ADDR_112, "64'h100",1) | |
241 | stx %g2, [%g2] | |
242 | ldx [%g2 + 64], %g4 | |
243 | ldx [%g2 + 128], %g5 | |
244 | ldx [%g2 + 192], %g6 | |
245 | add %g2, %g3, %g2 | |
246 | #define DMA_ADDR_121 mpeval(0x00dF000000 + 0,16,16) | |
247 | #define DMA_ADDR_122 mpeval(0x00dF000000 + 64,16,16) | |
248 | #define DMA_ADDR_123 mpeval(0x80dF000000 + 128,16,16) | |
249 | DMA12: nop | |
250 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA12)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_121, DMA_ADDR_122, "64'h100",1) | |
251 | stx %g2, [%g2] | |
252 | ldx [%g2 + 64], %g4 | |
253 | ldx [%g2 + 128], %g5 | |
254 | ldx [%g2 + 192], %g6 | |
255 | add %g2, %g3, %g2 | |
256 | #define DMA_ADDR_131 mpeval(0x00eF000000 + 0,16,16) | |
257 | #define DMA_ADDR_132 mpeval(0x00eF000000 + 64,16,16) | |
258 | #define DMA_ADDR_133 mpeval(0x80eF000000 + 128,16,16) | |
259 | DMA13: nop | |
260 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA13)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_131, DMA_ADDR_132, "64'h100",1) | |
261 | stx %g2, [%g2] | |
262 | ldx [%g2 + 64], %g4 | |
263 | ldx [%g2 + 128], %g5 | |
264 | ldx [%g2 + 192], %g6 | |
265 | add %g2, %g3, %g2 | |
266 | #define DMA_ADDR_141 mpeval(0x00fF000000 + 0,16,16) | |
267 | #define DMA_ADDR_142 mpeval(0x00fF000000 + 64,16,16) | |
268 | #define DMA_ADDR_143 mpeval(0x80fF000000 + 128,16,16) | |
269 | DMA14: nop | |
270 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA14)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_141, DMA_ADDR_142, "64'h100",1) | |
271 | stx %g2, [%g2] | |
272 | ldx [%g2 + 64], %g4 | |
273 | ldx [%g2 + 128], %g5 | |
274 | ldx [%g2 + 192], %g6 | |
275 | add %g2, %g3, %g2 | |
276 | #define DMA_ADDR_151 mpeval(0x010F000000 + 0,16,16) | |
277 | #define DMA_ADDR_152 mpeval(0x010F000000 + 64,16,16) | |
278 | #define DMA_ADDR_153 mpeval(0x810F000000 + 128,16,16) | |
279 | DMA15: nop | |
280 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA15)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_151, DMA_ADDR_152, "64'h100",1) | |
281 | stx %g2, [%g2] | |
282 | ldx [%g2 + 64], %g4 | |
283 | ldx [%g2 + 128], %g5 | |
284 | ldx [%g2 + 192], %g6 | |
285 | add %g2, %g3, %g2 | |
286 | #define DMA_ADDR_161 mpeval(0x011F000000 + 0,16,16) | |
287 | #define DMA_ADDR_162 mpeval(0x011F000000 + 64,16,16) | |
288 | #define DMA_ADDR_163 mpeval(0x811F000000 + 128,16,16) | |
289 | DMA16: nop | |
290 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA16)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_161, DMA_ADDR_162, "64'h100",1) | |
291 | stx %g2, [%g2] | |
292 | ldx [%g2 + 64], %g4 | |
293 | ldx [%g2 + 128], %g5 | |
294 | ldx [%g2 + 192], %g6 | |
295 | add %g2, %g3, %g2 | |
296 | #define DMA_ADDR_171 mpeval(0x012F000000 + 0,16,16) | |
297 | #define DMA_ADDR_172 mpeval(0x012F000000 + 64,16,16) | |
298 | #define DMA_ADDR_173 mpeval(0x812F000000 + 128,16,16) | |
299 | DMA17: nop | |
300 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA17)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_171, DMA_ADDR_172, "64'h100",1) | |
301 | stx %g2, [%g2] | |
302 | ldx [%g2 + 64], %g4 | |
303 | ldx [%g2 + 128], %g5 | |
304 | ldx [%g2 + 192], %g6 | |
305 | add %g2, %g3, %g2 | |
306 | #define DMA_ADDR_181 mpeval(0x013F000000 + 0,16,16) | |
307 | #define DMA_ADDR_182 mpeval(0x013F000000 + 64,16,16) | |
308 | #define DMA_ADDR_183 mpeval(0x813F000000 + 128,16,16) | |
309 | DMA18: nop | |
310 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA18)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_181, DMA_ADDR_182, "64'h100",1) | |
311 | stx %g2, [%g2] | |
312 | ldx [%g2 + 64], %g4 | |
313 | ldx [%g2 + 128], %g5 | |
314 | ldx [%g2 + 192], %g6 | |
315 | add %g2, %g3, %g2 | |
316 | #define DMA_ADDR_191 mpeval(0x014F000000 + 0,16,16) | |
317 | #define DMA_ADDR_192 mpeval(0x014F000000 + 64,16,16) | |
318 | #define DMA_ADDR_193 mpeval(0x814F000000 + 128,16,16) | |
319 | DMA19: nop | |
320 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA19)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_191, DMA_ADDR_192, "64'h100",1) | |
321 | stx %g2, [%g2] | |
322 | ldx [%g2 + 64], %g4 | |
323 | ldx [%g2 + 128], %g5 | |
324 | ldx [%g2 + 192], %g6 | |
325 | add %g2, %g3, %g2 | |
326 | #define DMA_ADDR_201 mpeval(0x015F000000 + 0,16,16) | |
327 | #define DMA_ADDR_202 mpeval(0x015F000000 + 64,16,16) | |
328 | #define DMA_ADDR_203 mpeval(0x815F000000 + 128,16,16) | |
329 | DMA20: nop | |
330 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA20)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_201, DMA_ADDR_202, "64'h100",1) | |
331 | stx %g2, [%g2] | |
332 | ldx [%g2 + 64], %g4 | |
333 | ldx [%g2 + 128], %g5 | |
334 | ldx [%g2 + 192], %g6 | |
335 | add %g2, %g3, %g2 | |
336 | #define DMA_ADDR_211 mpeval(0x016F000000 + 0,16,16) | |
337 | #define DMA_ADDR_212 mpeval(0x016F000000 + 64,16,16) | |
338 | #define DMA_ADDR_213 mpeval(0x816F000000 + 128,16,16) | |
339 | DMA21: nop | |
340 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA21)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_211, DMA_ADDR_212, "64'h100",1) | |
341 | stx %g2, [%g2] | |
342 | ldx [%g2 + 64], %g4 | |
343 | ldx [%g2 + 128], %g5 | |
344 | ldx [%g2 + 192], %g6 | |
345 | add %g2, %g3, %g2 | |
346 | #define DMA_ADDR_221 mpeval(0x017F000000 + 0,16,16) | |
347 | #define DMA_ADDR_222 mpeval(0x017F000000 + 64,16,16) | |
348 | #define DMA_ADDR_223 mpeval(0x817F000000 + 128,16,16) | |
349 | DMA22: nop | |
350 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA22)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_221, DMA_ADDR_222, "64'h100",1) | |
351 | stx %g2, [%g2] | |
352 | ldx [%g2 + 64], %g4 | |
353 | ldx [%g2 + 128], %g5 | |
354 | ldx [%g2 + 192], %g6 | |
355 | add %g2, %g3, %g2 | |
356 | #define DMA_ADDR_231 mpeval(0x018F000000 + 0,16,16) | |
357 | #define DMA_ADDR_232 mpeval(0x018F000000 + 64,16,16) | |
358 | #define DMA_ADDR_233 mpeval(0x818F000000 + 128,16,16) | |
359 | DMA23: nop | |
360 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA23)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_231, DMA_ADDR_232, "64'h100",1) | |
361 | stx %g2, [%g2] | |
362 | ldx [%g2 + 64], %g4 | |
363 | ldx [%g2 + 128], %g5 | |
364 | ldx [%g2 + 192], %g6 | |
365 | add %g2, %g3, %g2 | |
366 | #define DMA_ADDR_241 mpeval(0x019F000000 + 0,16,16) | |
367 | #define DMA_ADDR_242 mpeval(0x019F000000 + 64,16,16) | |
368 | #define DMA_ADDR_243 mpeval(0x819F000000 + 128,16,16) | |
369 | DMA24: nop | |
370 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA24)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_241, DMA_ADDR_242, "64'h100",1) | |
371 | stx %g2, [%g2] | |
372 | ldx [%g2 + 64], %g4 | |
373 | ldx [%g2 + 128], %g5 | |
374 | ldx [%g2 + 192], %g6 | |
375 | add %g2, %g3, %g2 | |
376 | #define DMA_ADDR_251 mpeval(0x01aF000000 + 0,16,16) | |
377 | #define DMA_ADDR_252 mpeval(0x01aF000000 + 64,16,16) | |
378 | #define DMA_ADDR_253 mpeval(0x81aF000000 + 128,16,16) | |
379 | DMA25: nop | |
380 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA25)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_251, DMA_ADDR_252, "64'h100",1) | |
381 | stx %g2, [%g2] | |
382 | ldx [%g2 + 64], %g4 | |
383 | ldx [%g2 + 128], %g5 | |
384 | ldx [%g2 + 192], %g6 | |
385 | add %g2, %g3, %g2 | |
386 | #define DMA_ADDR_261 mpeval(0x01bF000000 + 0,16,16) | |
387 | #define DMA_ADDR_262 mpeval(0x01bF000000 + 64,16,16) | |
388 | #define DMA_ADDR_263 mpeval(0x81bF000000 + 128,16,16) | |
389 | DMA26: nop | |
390 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA26)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_261, DMA_ADDR_262, "64'h100",1) | |
391 | stx %g2, [%g2] | |
392 | ldx [%g2 + 64], %g4 | |
393 | ldx [%g2 + 128], %g5 | |
394 | ldx [%g2 + 192], %g6 | |
395 | add %g2, %g3, %g2 | |
396 | #define DMA_ADDR_271 mpeval(0x01cF000000 + 0,16,16) | |
397 | #define DMA_ADDR_272 mpeval(0x01cF000000 + 64,16,16) | |
398 | #define DMA_ADDR_273 mpeval(0x81cF000000 + 128,16,16) | |
399 | DMA27: nop | |
400 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA27)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_271, DMA_ADDR_272, "64'h100",1) | |
401 | stx %g2, [%g2] | |
402 | ldx [%g2 + 64], %g4 | |
403 | ldx [%g2 + 128], %g5 | |
404 | ldx [%g2 + 192], %g6 | |
405 | add %g2, %g3, %g2 | |
406 | #define DMA_ADDR_281 mpeval(0x01dF000000 + 0,16,16) | |
407 | #define DMA_ADDR_282 mpeval(0x01dF000000 + 64,16,16) | |
408 | #define DMA_ADDR_283 mpeval(0x81dF000000 + 128,16,16) | |
409 | DMA28: nop | |
410 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA28)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_281, DMA_ADDR_282, "64'h100",1) | |
411 | stx %g2, [%g2] | |
412 | ldx [%g2 + 64], %g4 | |
413 | ldx [%g2 + 128], %g5 | |
414 | ldx [%g2 + 192], %g6 | |
415 | add %g2, %g3, %g2 | |
416 | #define DMA_ADDR_291 mpeval(0x01eF000000 + 0,16,16) | |
417 | #define DMA_ADDR_292 mpeval(0x01eF000000 + 64,16,16) | |
418 | #define DMA_ADDR_293 mpeval(0x81eF000000 + 128,16,16) | |
419 | DMA29: nop | |
420 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA29)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_291, DMA_ADDR_292, "64'h100",1) | |
421 | stx %g2, [%g2] | |
422 | ldx [%g2 + 64], %g4 | |
423 | ldx [%g2 + 128], %g5 | |
424 | ldx [%g2 + 192], %g6 | |
425 | add %g2, %g3, %g2 | |
426 | #define DMA_ADDR_301 mpeval(0x01fF000000 + 0,16,16) | |
427 | #define DMA_ADDR_302 mpeval(0x01fF000000 + 64,16,16) | |
428 | #define DMA_ADDR_303 mpeval(0x81fF000000 + 128,16,16) | |
429 | DMA30: nop | |
430 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA30)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_301, DMA_ADDR_302, "64'h100",1) | |
431 | stx %g2, [%g2] | |
432 | ldx [%g2 + 64], %g4 | |
433 | ldx [%g2 + 128], %g5 | |
434 | ldx [%g2 + 192], %g6 | |
435 | add %g2, %g3, %g2 | |
436 | #define DMA_ADDR_311 mpeval(0x020F000000 + 0,16,16) | |
437 | #define DMA_ADDR_312 mpeval(0x020F000000 + 64,16,16) | |
438 | #define DMA_ADDR_313 mpeval(0x820F000000 + 128,16,16) | |
439 | DMA31: nop | |
440 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA31)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_311, DMA_ADDR_312, "64'h100",1) | |
441 | stx %g2, [%g2] | |
442 | ldx [%g2 + 64], %g4 | |
443 | ldx [%g2 + 128], %g5 | |
444 | ldx [%g2 + 192], %g6 | |
445 | add %g2, %g3, %g2 | |
446 | #define DMA_ADDR_321 mpeval(0x021F000000 + 0,16,16) | |
447 | #define DMA_ADDR_322 mpeval(0x021F000000 + 64,16,16) | |
448 | #define DMA_ADDR_323 mpeval(0x821F000000 + 128,16,16) | |
449 | DMA32: nop | |
450 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA32)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_321, DMA_ADDR_322, "64'h100",1) | |
451 | stx %g2, [%g2] | |
452 | ldx [%g2 + 64], %g4 | |
453 | ldx [%g2 + 128], %g5 | |
454 | ldx [%g2 + 192], %g6 | |
455 | add %g2, %g3, %g2 | |
456 | #define DMA_ADDR_331 mpeval(0x022F000000 + 0,16,16) | |
457 | #define DMA_ADDR_332 mpeval(0x022F000000 + 64,16,16) | |
458 | #define DMA_ADDR_333 mpeval(0x822F000000 + 128,16,16) | |
459 | DMA33: nop | |
460 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA33)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_331, DMA_ADDR_332, "64'h100",1) | |
461 | stx %g2, [%g2] | |
462 | ldx [%g2 + 64], %g4 | |
463 | ldx [%g2 + 128], %g5 | |
464 | ldx [%g2 + 192], %g6 | |
465 | add %g2, %g3, %g2 | |
466 | #define DMA_ADDR_341 mpeval(0x023F000000 + 0,16,16) | |
467 | #define DMA_ADDR_342 mpeval(0x023F000000 + 64,16,16) | |
468 | #define DMA_ADDR_343 mpeval(0x823F000000 + 128,16,16) | |
469 | DMA34: nop | |
470 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA34)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_341, DMA_ADDR_342, "64'h100",1) | |
471 | stx %g2, [%g2] | |
472 | ldx [%g2 + 64], %g4 | |
473 | ldx [%g2 + 128], %g5 | |
474 | ldx [%g2 + 192], %g6 | |
475 | add %g2, %g3, %g2 | |
476 | #define DMA_ADDR_351 mpeval(0x024F000000 + 0,16,16) | |
477 | #define DMA_ADDR_352 mpeval(0x024F000000 + 64,16,16) | |
478 | #define DMA_ADDR_353 mpeval(0x824F000000 + 128,16,16) | |
479 | DMA35: nop | |
480 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA35)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_351, DMA_ADDR_352, "64'h100",1) | |
481 | stx %g2, [%g2] | |
482 | ldx [%g2 + 64], %g4 | |
483 | ldx [%g2 + 128], %g5 | |
484 | ldx [%g2 + 192], %g6 | |
485 | add %g2, %g3, %g2 | |
486 | #define DMA_ADDR_361 mpeval(0x025F000000 + 0,16,16) | |
487 | #define DMA_ADDR_362 mpeval(0x025F000000 + 64,16,16) | |
488 | #define DMA_ADDR_363 mpeval(0x825F000000 + 128,16,16) | |
489 | DMA36: nop | |
490 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA36)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_361, DMA_ADDR_362, "64'h100",1) | |
491 | stx %g2, [%g2] | |
492 | ldx [%g2 + 64], %g4 | |
493 | ldx [%g2 + 128], %g5 | |
494 | ldx [%g2 + 192], %g6 | |
495 | add %g2, %g3, %g2 | |
496 | #define DMA_ADDR_371 mpeval(0x026F000000 + 0,16,16) | |
497 | #define DMA_ADDR_372 mpeval(0x026F000000 + 64,16,16) | |
498 | #define DMA_ADDR_373 mpeval(0x826F000000 + 128,16,16) | |
499 | DMA37: nop | |
500 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA37)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_371, DMA_ADDR_372, "64'h100",1) | |
501 | stx %g2, [%g2] | |
502 | ldx [%g2 + 64], %g4 | |
503 | ldx [%g2 + 128], %g5 | |
504 | ldx [%g2 + 192], %g6 | |
505 | add %g2, %g3, %g2 | |
506 | #define DMA_ADDR_381 mpeval(0x027F000000 + 0,16,16) | |
507 | #define DMA_ADDR_382 mpeval(0x027F000000 + 64,16,16) | |
508 | #define DMA_ADDR_383 mpeval(0x827F000000 + 128,16,16) | |
509 | DMA38: nop | |
510 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA38)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_381, DMA_ADDR_382, "64'h100",1) | |
511 | stx %g2, [%g2] | |
512 | ldx [%g2 + 64], %g4 | |
513 | ldx [%g2 + 128], %g5 | |
514 | ldx [%g2 + 192], %g6 | |
515 | add %g2, %g3, %g2 | |
516 | #define DMA_ADDR_391 mpeval(0x028F000000 + 0,16,16) | |
517 | #define DMA_ADDR_392 mpeval(0x028F000000 + 64,16,16) | |
518 | #define DMA_ADDR_393 mpeval(0x828F000000 + 128,16,16) | |
519 | DMA39: nop | |
520 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA39)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_391, DMA_ADDR_392, "64'h100",1) | |
521 | stx %g2, [%g2] | |
522 | ldx [%g2 + 64], %g4 | |
523 | ldx [%g2 + 128], %g5 | |
524 | ldx [%g2 + 192], %g6 | |
525 | add %g2, %g3, %g2 | |
526 | #define DMA_ADDR_401 mpeval(0x029F000000 + 0,16,16) | |
527 | #define DMA_ADDR_402 mpeval(0x029F000000 + 64,16,16) | |
528 | #define DMA_ADDR_403 mpeval(0x829F000000 + 128,16,16) | |
529 | DMA40: nop | |
530 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA40)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_401, DMA_ADDR_402, "64'h100",1) | |
531 | stx %g2, [%g2] | |
532 | ldx [%g2 + 64], %g4 | |
533 | ldx [%g2 + 128], %g5 | |
534 | ldx [%g2 + 192], %g6 | |
535 | add %g2, %g3, %g2 | |
536 | #define DMA_ADDR_411 mpeval(0x02aF000000 + 0,16,16) | |
537 | #define DMA_ADDR_412 mpeval(0x02aF000000 + 64,16,16) | |
538 | #define DMA_ADDR_413 mpeval(0x82aF000000 + 128,16,16) | |
539 | DMA41: nop | |
540 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA41)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_411, DMA_ADDR_412, "64'h100",1) | |
541 | stx %g2, [%g2] | |
542 | ldx [%g2 + 64], %g4 | |
543 | ldx [%g2 + 128], %g5 | |
544 | ldx [%g2 + 192], %g6 | |
545 | add %g2, %g3, %g2 | |
546 | #define DMA_ADDR_421 mpeval(0x02bF000000 + 0,16,16) | |
547 | #define DMA_ADDR_422 mpeval(0x02bF000000 + 64,16,16) | |
548 | #define DMA_ADDR_423 mpeval(0x82bF000000 + 128,16,16) | |
549 | DMA42: nop | |
550 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA42)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_421, DMA_ADDR_422, "64'h100",1) | |
551 | stx %g2, [%g2] | |
552 | ldx [%g2 + 64], %g4 | |
553 | ldx [%g2 + 128], %g5 | |
554 | ldx [%g2 + 192], %g6 | |
555 | add %g2, %g3, %g2 | |
556 | #define DMA_ADDR_431 mpeval(0x02cF000000 + 0,16,16) | |
557 | #define DMA_ADDR_432 mpeval(0x02cF000000 + 64,16,16) | |
558 | #define DMA_ADDR_433 mpeval(0x82cF000000 + 128,16,16) | |
559 | DMA43: nop | |
560 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA43)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_431, DMA_ADDR_432, "64'h100",1) | |
561 | stx %g2, [%g2] | |
562 | ldx [%g2 + 64], %g4 | |
563 | ldx [%g2 + 128], %g5 | |
564 | ldx [%g2 + 192], %g6 | |
565 | add %g2, %g3, %g2 | |
566 | #define DMA_ADDR_441 mpeval(0x02dF000000 + 0,16,16) | |
567 | #define DMA_ADDR_442 mpeval(0x02dF000000 + 64,16,16) | |
568 | #define DMA_ADDR_443 mpeval(0x82dF000000 + 128,16,16) | |
569 | DMA44: nop | |
570 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA44)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_441, DMA_ADDR_442, "64'h100",1) | |
571 | stx %g2, [%g2] | |
572 | ldx [%g2 + 64], %g4 | |
573 | ldx [%g2 + 128], %g5 | |
574 | ldx [%g2 + 192], %g6 | |
575 | add %g2, %g3, %g2 | |
576 | #define DMA_ADDR_451 mpeval(0x02eF000000 + 0,16,16) | |
577 | #define DMA_ADDR_452 mpeval(0x02eF000000 + 64,16,16) | |
578 | #define DMA_ADDR_453 mpeval(0x82eF000000 + 128,16,16) | |
579 | DMA45: nop | |
580 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA45)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_451, DMA_ADDR_452, "64'h100",1) | |
581 | stx %g2, [%g2] | |
582 | ldx [%g2 + 64], %g4 | |
583 | ldx [%g2 + 128], %g5 | |
584 | ldx [%g2 + 192], %g6 | |
585 | add %g2, %g3, %g2 | |
586 | #define DMA_ADDR_461 mpeval(0x02fF000000 + 0,16,16) | |
587 | #define DMA_ADDR_462 mpeval(0x02fF000000 + 64,16,16) | |
588 | #define DMA_ADDR_463 mpeval(0x82fF000000 + 128,16,16) | |
589 | DMA46: nop | |
590 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA46)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_461, DMA_ADDR_462, "64'h100",1) | |
591 | stx %g2, [%g2] | |
592 | ldx [%g2 + 64], %g4 | |
593 | ldx [%g2 + 128], %g5 | |
594 | ldx [%g2 + 192], %g6 | |
595 | add %g2, %g3, %g2 | |
596 | #define DMA_ADDR_471 mpeval(0x030F000000 + 0,16,16) | |
597 | #define DMA_ADDR_472 mpeval(0x030F000000 + 64,16,16) | |
598 | #define DMA_ADDR_473 mpeval(0x830F000000 + 128,16,16) | |
599 | DMA47: nop | |
600 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA47)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_471, DMA_ADDR_472, "64'h100",1) | |
601 | stx %g2, [%g2] | |
602 | ldx [%g2 + 64], %g4 | |
603 | ldx [%g2 + 128], %g5 | |
604 | ldx [%g2 + 192], %g6 | |
605 | add %g2, %g3, %g2 | |
606 | #define DMA_ADDR_481 mpeval(0x031F000000 + 0,16,16) | |
607 | #define DMA_ADDR_482 mpeval(0x031F000000 + 64,16,16) | |
608 | #define DMA_ADDR_483 mpeval(0x831F000000 + 128,16,16) | |
609 | DMA48: nop | |
610 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA48)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_481, DMA_ADDR_482, "64'h100",1) | |
611 | stx %g2, [%g2] | |
612 | ldx [%g2 + 64], %g4 | |
613 | ldx [%g2 + 128], %g5 | |
614 | ldx [%g2 + 192], %g6 | |
615 | add %g2, %g3, %g2 | |
616 | #define DMA_ADDR_491 mpeval(0x032F000000 + 0,16,16) | |
617 | #define DMA_ADDR_492 mpeval(0x032F000000 + 64,16,16) | |
618 | #define DMA_ADDR_493 mpeval(0x832F000000 + 128,16,16) | |
619 | DMA49: nop | |
620 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA49)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_491, DMA_ADDR_492, "64'h100",1) | |
621 | stx %g2, [%g2] | |
622 | ldx [%g2 + 64], %g4 | |
623 | ldx [%g2 + 128], %g5 | |
624 | ldx [%g2 + 192], %g6 | |
625 | add %g2, %g3, %g2 | |
626 | #define DMA_ADDR_501 mpeval(0x033F000000 + 0,16,16) | |
627 | #define DMA_ADDR_502 mpeval(0x033F000000 + 64,16,16) | |
628 | #define DMA_ADDR_503 mpeval(0x833F000000 + 128,16,16) | |
629 | DMA50: nop | |
630 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA50)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_501, DMA_ADDR_502, "64'h100",1) | |
631 | stx %g2, [%g2] | |
632 | ldx [%g2 + 64], %g4 | |
633 | ldx [%g2 + 128], %g5 | |
634 | ldx [%g2 + 192], %g6 | |
635 | add %g2, %g3, %g2 | |
636 | #define DMA_ADDR_511 mpeval(0x034F000000 + 0,16,16) | |
637 | #define DMA_ADDR_512 mpeval(0x034F000000 + 64,16,16) | |
638 | #define DMA_ADDR_513 mpeval(0x834F000000 + 128,16,16) | |
639 | DMA51: nop | |
640 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA51)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_511, DMA_ADDR_512, "64'h100",1) | |
641 | stx %g2, [%g2] | |
642 | ldx [%g2 + 64], %g4 | |
643 | ldx [%g2 + 128], %g5 | |
644 | ldx [%g2 + 192], %g6 | |
645 | add %g2, %g3, %g2 | |
646 | #define DMA_ADDR_521 mpeval(0x035F000000 + 0,16,16) | |
647 | #define DMA_ADDR_522 mpeval(0x035F000000 + 64,16,16) | |
648 | #define DMA_ADDR_523 mpeval(0x835F000000 + 128,16,16) | |
649 | DMA52: nop | |
650 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA52)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_521, DMA_ADDR_522, "64'h100",1) | |
651 | stx %g2, [%g2] | |
652 | ldx [%g2 + 64], %g4 | |
653 | ldx [%g2 + 128], %g5 | |
654 | ldx [%g2 + 192], %g6 | |
655 | add %g2, %g3, %g2 | |
656 | #define DMA_ADDR_531 mpeval(0x036F000000 + 0,16,16) | |
657 | #define DMA_ADDR_532 mpeval(0x036F000000 + 64,16,16) | |
658 | #define DMA_ADDR_533 mpeval(0x836F000000 + 128,16,16) | |
659 | DMA53: nop | |
660 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA53)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_531, DMA_ADDR_532, "64'h100",1) | |
661 | stx %g2, [%g2] | |
662 | ldx [%g2 + 64], %g4 | |
663 | ldx [%g2 + 128], %g5 | |
664 | ldx [%g2 + 192], %g6 | |
665 | add %g2, %g3, %g2 | |
666 | #define DMA_ADDR_541 mpeval(0x037F000000 + 0,16,16) | |
667 | #define DMA_ADDR_542 mpeval(0x037F000000 + 64,16,16) | |
668 | #define DMA_ADDR_543 mpeval(0x837F000000 + 128,16,16) | |
669 | DMA54: nop | |
670 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA54)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_541, DMA_ADDR_542, "64'h100",1) | |
671 | stx %g2, [%g2] | |
672 | ldx [%g2 + 64], %g4 | |
673 | ldx [%g2 + 128], %g5 | |
674 | ldx [%g2 + 192], %g6 | |
675 | add %g2, %g3, %g2 | |
676 | #define DMA_ADDR_551 mpeval(0x038F000000 + 0,16,16) | |
677 | #define DMA_ADDR_552 mpeval(0x038F000000 + 64,16,16) | |
678 | #define DMA_ADDR_553 mpeval(0x838F000000 + 128,16,16) | |
679 | DMA55: nop | |
680 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA55)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_551, DMA_ADDR_552, "64'h100",1) | |
681 | stx %g2, [%g2] | |
682 | ldx [%g2 + 64], %g4 | |
683 | ldx [%g2 + 128], %g5 | |
684 | ldx [%g2 + 192], %g6 | |
685 | add %g2, %g3, %g2 | |
686 | #define DMA_ADDR_561 mpeval(0x039F000000 + 0,16,16) | |
687 | #define DMA_ADDR_562 mpeval(0x039F000000 + 64,16,16) | |
688 | #define DMA_ADDR_563 mpeval(0x839F000000 + 128,16,16) | |
689 | DMA56: nop | |
690 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA56)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_561, DMA_ADDR_562, "64'h100",1) | |
691 | stx %g2, [%g2] | |
692 | ldx [%g2 + 64], %g4 | |
693 | ldx [%g2 + 128], %g5 | |
694 | ldx [%g2 + 192], %g6 | |
695 | add %g2, %g3, %g2 | |
696 | #define DMA_ADDR_571 mpeval(0x03aF000000 + 0,16,16) | |
697 | #define DMA_ADDR_572 mpeval(0x03aF000000 + 64,16,16) | |
698 | #define DMA_ADDR_573 mpeval(0x83aF000000 + 128,16,16) | |
699 | DMA57: nop | |
700 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA57)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_571, DMA_ADDR_572, "64'h100",1) | |
701 | stx %g2, [%g2] | |
702 | ldx [%g2 + 64], %g4 | |
703 | ldx [%g2 + 128], %g5 | |
704 | ldx [%g2 + 192], %g6 | |
705 | add %g2, %g3, %g2 | |
706 | #define DMA_ADDR_581 mpeval(0x03bF000000 + 0,16,16) | |
707 | #define DMA_ADDR_582 mpeval(0x03bF000000 + 64,16,16) | |
708 | #define DMA_ADDR_583 mpeval(0x83bF000000 + 128,16,16) | |
709 | DMA58: nop | |
710 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA58)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_581, DMA_ADDR_582, "64'h100",1) | |
711 | stx %g2, [%g2] | |
712 | ldx [%g2 + 64], %g4 | |
713 | ldx [%g2 + 128], %g5 | |
714 | ldx [%g2 + 192], %g6 | |
715 | add %g2, %g3, %g2 | |
716 | #define DMA_ADDR_591 mpeval(0x03cF000000 + 0,16,16) | |
717 | #define DMA_ADDR_592 mpeval(0x03cF000000 + 64,16,16) | |
718 | #define DMA_ADDR_593 mpeval(0x83cF000000 + 128,16,16) | |
719 | DMA59: nop | |
720 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA59)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_591, DMA_ADDR_592, "64'h100",1) | |
721 | stx %g2, [%g2] | |
722 | ldx [%g2 + 64], %g4 | |
723 | ldx [%g2 + 128], %g5 | |
724 | ldx [%g2 + 192], %g6 | |
725 | add %g2, %g3, %g2 | |
726 | #define DMA_ADDR_601 mpeval(0x03dF000000 + 0,16,16) | |
727 | #define DMA_ADDR_602 mpeval(0x03dF000000 + 64,16,16) | |
728 | #define DMA_ADDR_603 mpeval(0x83dF000000 + 128,16,16) | |
729 | DMA60: nop | |
730 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA60)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_601, DMA_ADDR_602, "64'h100",1) | |
731 | stx %g2, [%g2] | |
732 | ldx [%g2 + 64], %g4 | |
733 | ldx [%g2 + 128], %g5 | |
734 | ldx [%g2 + 192], %g6 | |
735 | add %g2, %g3, %g2 | |
736 | #define DMA_ADDR_611 mpeval(0x03eF000000 + 0,16,16) | |
737 | #define DMA_ADDR_612 mpeval(0x03eF000000 + 64,16,16) | |
738 | #define DMA_ADDR_613 mpeval(0x83eF000000 + 128,16,16) | |
739 | DMA61: nop | |
740 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA61)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_611, DMA_ADDR_612, "64'h100",1) | |
741 | stx %g2, [%g2] | |
742 | ldx [%g2 + 64], %g4 | |
743 | ldx [%g2 + 128], %g5 | |
744 | ldx [%g2 + 192], %g6 | |
745 | add %g2, %g3, %g2 | |
746 | #define DMA_ADDR_621 mpeval(0x03fF000000 + 0,16,16) | |
747 | #define DMA_ADDR_622 mpeval(0x03fF000000 + 64,16,16) | |
748 | #define DMA_ADDR_623 mpeval(0x83fF000000 + 128,16,16) | |
749 | DMA62: nop | |
750 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA62)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_621, DMA_ADDR_622, "64'h100",1) | |
751 | stx %g2, [%g2] | |
752 | ldx [%g2 + 64], %g4 | |
753 | ldx [%g2 + 128], %g5 | |
754 | ldx [%g2 + 192], %g6 | |
755 | add %g2, %g3, %g2 | |
756 | #define DMA_ADDR_631 mpeval(0x040F000000 + 0,16,16) | |
757 | #define DMA_ADDR_632 mpeval(0x040F000000 + 64,16,16) | |
758 | #define DMA_ADDR_633 mpeval(0x840F000000 + 128,16,16) | |
759 | DMA63: nop | |
760 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA63)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_631, DMA_ADDR_632, "64'h100",1) | |
761 | stx %g2, [%g2] | |
762 | ldx [%g2 + 64], %g4 | |
763 | ldx [%g2 + 128], %g5 | |
764 | ldx [%g2 + 192], %g6 | |
765 | add %g2, %g3, %g2 | |
766 | ||
767 | !! These start/end addresses will assure that VA[39] is set | |
768 | #define DMA_ADDR_731 mpeval(0x801F000000,16,16) | |
769 | #define DMA_ADDR_732 mpeval(0xffffffffff,16,16) | |
770 | DMA128: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA128) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_731, DMA_ADDR_732, "64'h80",1) | |
771 | ||
772 | DMA129: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA129) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_731, DMA_ADDR_732, "64'h80",1) | |
773 | ||
774 | DMA130: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA130) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_731, DMA_ADDR_732, "64'h80",1) | |
775 | ||
776 | ||
777 | DMA64: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA64) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_02, DMA_ADDR_03, "64'h80",1) | |
778 | DMA65: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA65) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_12, DMA_ADDR_13, "64'h80",1) | |
779 | DMA66: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA66) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_22, DMA_ADDR_23, "64'h80",1) | |
780 | DMA67: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA67) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_32, DMA_ADDR_33, "64'h80",1) | |
781 | DMA68: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA68) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_42, DMA_ADDR_43, "64'h80",1) | |
782 | DMA69: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA69) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_52, DMA_ADDR_53, "64'h80",1) | |
783 | DMA70: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA70) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_62, DMA_ADDR_63, "64'h80",1) | |
784 | DMA71: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA71) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_72, DMA_ADDR_73, "64'h80",1) | |
785 | DMA72: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA72) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_82, DMA_ADDR_83, "64'h80",1) | |
786 | DMA73: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA73) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_92, DMA_ADDR_93, "64'h80",1) | |
787 | DMA74: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA74) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_102, DMA_ADDR_103, "64'h80",1) | |
788 | DMA75: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA75) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_112, DMA_ADDR_113, "64'h80",1) | |
789 | DMA76: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA76) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_122, DMA_ADDR_123, "64'h80",1) | |
790 | DMA77: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA77) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_132, DMA_ADDR_133, "64'h80",1) | |
791 | DMA78: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA78) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_142, DMA_ADDR_143, "64'h80",1) | |
792 | DMA79: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA79) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_152, DMA_ADDR_153, "64'h80",1) | |
793 | DMA80: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA80) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_162, DMA_ADDR_163, "64'h80",1) | |
794 | DMA81: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA81) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_172, DMA_ADDR_173, "64'h80",1) | |
795 | DMA82: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA82) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_182, DMA_ADDR_183, "64'h80",1) | |
796 | DMA83: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA83) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_192, DMA_ADDR_193, "64'h80",1) | |
797 | DMA84: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA84) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_202, DMA_ADDR_203, "64'h80",1) | |
798 | DMA85: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA85) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_212, DMA_ADDR_213, "64'h80",1) | |
799 | DMA86: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA86) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_222, DMA_ADDR_223, "64'h80",1) | |
800 | DMA87: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA87) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_232, DMA_ADDR_233, "64'h80",1) | |
801 | DMA88: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA88) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_242, DMA_ADDR_243, "64'h80",1) | |
802 | DMA89: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA89) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_252, DMA_ADDR_253, "64'h80",1) | |
803 | DMA90: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA90) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_262, DMA_ADDR_263, "64'h80",1) | |
804 | DMA91: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA91) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_272, DMA_ADDR_273, "64'h80",1) | |
805 | DMA92: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA92) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_282, DMA_ADDR_283, "64'h80",1) | |
806 | DMA93: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA93) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_292, DMA_ADDR_293, "64'h80",1) | |
807 | DMA94: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA94) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_302, DMA_ADDR_303, "64'h80",1) | |
808 | DMA95: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA95) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_312, DMA_ADDR_313, "64'h80",1) | |
809 | DMA96: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA96) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_322, DMA_ADDR_323, "64'h80",1) | |
810 | DMA97: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA97) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_332, DMA_ADDR_333, "64'h80",1) | |
811 | DMA98: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA98) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_342, DMA_ADDR_343, "64'h80",1) | |
812 | DMA99: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA99) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_352, DMA_ADDR_353, "64'h80",1) | |
813 | DMA100: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA100) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_362, DMA_ADDR_363, "64'h80",1) | |
814 | DMA101: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA101) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_372, DMA_ADDR_373, "64'h80",1) | |
815 | DMA102: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA102) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_382, DMA_ADDR_383, "64'h80",1) | |
816 | DMA103: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA103) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_392, DMA_ADDR_393, "64'h80",1) | |
817 | DMA104: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA104) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_402, DMA_ADDR_403, "64'h80",1) | |
818 | DMA105: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA105) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_412, DMA_ADDR_413, "64'h80",1) | |
819 | DMA106: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA106) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_422, DMA_ADDR_423, "64'h80",1) | |
820 | DMA107: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA107) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_432, DMA_ADDR_433, "64'h80",1) | |
821 | DMA108: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA108) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_442, DMA_ADDR_443, "64'h80",1) | |
822 | DMA109: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA109) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_452, DMA_ADDR_453, "64'h80",1) | |
823 | DMA110: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA110) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_462, DMA_ADDR_463, "64'h80",1) | |
824 | DMA111: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA111) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_472, DMA_ADDR_473, "64'h80",1) | |
825 | DMA112: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA112) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_482, DMA_ADDR_483, "64'h80",1) | |
826 | DMA113: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA113) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_492, DMA_ADDR_493, "64'h80",1) | |
827 | DMA114: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA114) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_502, DMA_ADDR_503, "64'h80",1) | |
828 | DMA115: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA115) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_512, DMA_ADDR_513, "64'h80",1) | |
829 | DMA116: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA116) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_522, DMA_ADDR_523, "64'h80",1) | |
830 | DMA117: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA117) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_532, DMA_ADDR_533, "64'h80",1) | |
831 | DMA118: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA118) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_542, DMA_ADDR_543, "64'h80",1) | |
832 | DMA119: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA119) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_552, DMA_ADDR_553, "64'h80",1) | |
833 | DMA120: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA120) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_562, DMA_ADDR_563, "64'h80",1) | |
834 | DMA121: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA121) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_572, DMA_ADDR_573, "64'h80",1) | |
835 | DMA122: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA122) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_582, DMA_ADDR_583, "64'h80",1) | |
836 | DMA123: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA123) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_592, DMA_ADDR_593, "64'h80",1) | |
837 | DMA124: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA124) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_602, DMA_ADDR_603, "64'h80",1) | |
838 | DMA125: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA125) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_612, DMA_ADDR_613, "64'h80",1) | |
839 | DMA126: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA126) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_622, DMA_ADDR_623, "64'h80",1) | |
840 | DMA127: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA127) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_632, DMA_ADDR_633, "64'h80",1) | |
841 | ||
842 | ||
843 | ||
844 | ! select a MEM32 address in PCI address range and transmit the command to NCU | |
845 | ||
846 | setx MEM32_WR_ADDR, %g1, %g2 | |
847 | set 5, %g4 ! loop 5 times | |
848 | ||
849 | delay_loop: | |
850 | stx %g2, [%g2] ! MEM32 PIO Write | |
851 | ldx [%g2], %l0 ! MEM32 PIO READ | |
852 | add %g2, 8, %g2 ! increment PIO address | |
853 | ||
854 | dec %g4 ! decrement counter | |
855 | brnz %g4, delay_loop ! loop if not zero | |
856 | nop | |
857 | ||
858 | ||
859 | test_passed: | |
860 | EXIT_GOOD | |
861 | ||
862 | test_failed: | |
863 | EXIT_BAD | |
864 | ||
865 | ||
866 | /************************************************************************ | |
867 | Test case data start. Need to set up known data to check on DMA completions | |
868 | ************************************************************************/ | |
869 | ||
870 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
871 | attr_data { | |
872 | Name = .DATA, | |
873 | hypervisor, | |
874 | compressimage | |
875 | } | |
876 | .data | |
877 | init_mem(0x0101010201030104, 64, 8, +, 0, +, 0x0004000400040004) | |
878 | ||
879 | ||
880 | /************************************************************************ | |
881 | IOMMU TTE start | |
882 | TTE Format: | |
883 | 63: 48 DEV KEY - set to 0 | |
884 | 47: 39 reserved - set to 0 | |
885 | 38: 13 DATA PA - set to VA for VA=RA | |
886 | 12: 7 DATA_SOFT - set to 0 | |
887 | 6: 5 reserved - set to 0 | |
888 | 5: 3 FNM MASK - set to 0 | |
889 | 2: 2 KEY VALID - set to 0 | |
890 | 1: 1 DATA_W - set to 1 | |
891 | 0: 0 DATA_V - set to 1 | |
892 | ************************************************************************/ | |
893 | ||
894 | SECTION .DATA2 DATA_VA=IOMMU_TTE_ADDR | |
895 | attr_data { | |
896 | Name = .DATA2, | |
897 | hypervisor, | |
898 | compressimage | |
899 | } | |
900 | ||
901 | .data | |
902 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
903 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
904 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
905 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
906 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
907 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
908 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
909 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
910 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
911 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
912 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
913 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
914 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
915 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
916 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
917 | init_mem(0x0000000000000003, 256, 8, +, 0, +, 0x0000000010000000) | |
918 | ||
919 | /************************************************************************/ |