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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: PCIeIommu4V8kTr.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | #define ENABLE_PCIE_MPS_512 | |
40 | #define MAIN_PAGE_HV_ALSO | |
41 | ||
42 | #define H_HT0_Interrupt_0x60 | |
43 | #define My_HT0_Interrupt_0x60 \ | |
44 | call my_trap_code; \ | |
45 | nop; \ | |
46 | retry; \ | |
47 | nop; | |
48 | ||
49 | #include "hboot.s" | |
50 | #include "peu_defines.h" | |
51 | #include "ncu_defines.h" | |
52 | ||
53 | #define MEM32_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA) | |
54 | ||
55 | #define DMA_DATA_ADDR 0xf8000000 | |
56 | ||
57 | #define IOMMU_TTE_ADDR 0x40000000 | |
58 | ||
59 | ! Bits 6:4 = Page Size: 0=8KB, 1=64KB, 3=4MB, 6=256MB; Bits 3:0 = TSB Table size: 6=64k entries | |
60 | #define IOTSBDESC_1_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (0 << 4) | 0xf) | |
61 | ||
62 | ||
63 | /************************************************************************ | |
64 | Test case code start | |
65 | ************************************************************************/ | |
66 | .text | |
67 | .global main | |
68 | ||
69 | main: | |
70 | ta T_CHANGE_HPRIV | |
71 | nop | |
72 | ||
73 | ! enable interrupts & provide basic handler | |
74 | #include "piu_rupt_enable.s" | |
75 | ||
76 | ! enable SUN4V translation in the IOMMU | |
77 | ||
78 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
79 | setx 0x00307, %g1, %g3 ! 9:8 11 = Cache enabled, | |
80 | ! 3: 1 = Busid Select, 1 = use busid[5:0] for DEV2IOTSB index | |
81 | ! 2: 1 = SUN4V enabled, | |
82 | ! 1: 1 = bypass enabled, | |
83 | ! 0: 1 = translation enabled | |
84 | stx %g3, [%g2] | |
85 | ldx [%g2], %g3 | |
86 | ||
87 | ! setup the DEV2IOTSB - the first 8 busids map to IOTSBDESC ram entry 1 | |
88 | ! (currently it looks like the denali transactor (or vera wrapper) is generating | |
89 | ! a random busid, so map them all to IOTSB 1. | |
90 | ||
91 | setx FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR, %g1, %g2 | |
92 | setx 0x0101010101010101, %g1, %g3 | |
93 | stx %g3, [%g2 + 0x00] | |
94 | stx %g3, [%g2 + 0x08] | |
95 | stx %g3, [%g2 + 0x10] | |
96 | stx %g3, [%g2 + 0x18] | |
97 | stx %g3, [%g2 + 0x20] | |
98 | stx %g3, [%g2 + 0x28] | |
99 | stx %g3, [%g2 + 0x30] | |
100 | stx %g3, [%g2 + 0x38] | |
101 | stx %g3, [%g2 + 0x40] | |
102 | stx %g3, [%g2 + 0x48] | |
103 | stx %g3, [%g2 + 0x50] | |
104 | stx %g3, [%g2 + 0x58] | |
105 | stx %g3, [%g2 + 0x60] | |
106 | stx %g3, [%g2 + 0x68] | |
107 | stx %g3, [%g2 + 0x70] | |
108 | stx %g3, [%g2 + 0x78] | |
109 | ||
110 | ! setup entry 1 of the IOTSBDESC ram | |
111 | ||
112 | setx FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR, %g1, %g2 | |
113 | setx IOTSBDESC_1_DATA, %g1, %g3 | |
114 | stx %g3, [%g2 + 8] | |
115 | ldx [%g2], %g3 | |
116 | ||
117 | ! Trigger some DMA Reads of various lengths | |
118 | ||
119 | ! Created 09/11/2005 17:24:41 by /home/somePerson/bin/genDMAs.pl | |
120 | setx 0xf8000000, %g1, %g2 ! DMA start address | |
121 | setx 0x00002000, %g1, %g3 ! page size | |
122 | #define DMA_ADDR_01 mpeval(0xf8000000 + 0,16,16) | |
123 | #define DMA_ADDR_02 mpeval(0xf8000000 + 64,16,16) | |
124 | #define DMA_ADDR_03 mpeval(0xf8000000 + 128,16,16) | |
125 | DMA0: nop | |
126 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA0)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_01, DMA_ADDR_02, "64'h100",1) | |
127 | stx %g2, [%g2] | |
128 | ldx [%g2 + 64], %g4 | |
129 | ldx [%g2 + 128], %g5 | |
130 | ldx [%g2 + 192], %g6 | |
131 | add %g2, %g3, %g2 | |
132 | #define DMA_ADDR_11 mpeval(0xf8002000 + 0,16,16) | |
133 | #define DMA_ADDR_12 mpeval(0xf8002000 + 64,16,16) | |
134 | #define DMA_ADDR_13 mpeval(0xf8002000 + 128,16,16) | |
135 | DMA1: nop | |
136 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA1)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_11, DMA_ADDR_12, "64'h100",1) | |
137 | stx %g2, [%g2] | |
138 | ldx [%g2 + 64], %g4 | |
139 | ldx [%g2 + 128], %g5 | |
140 | ldx [%g2 + 192], %g6 | |
141 | add %g2, %g3, %g2 | |
142 | #define DMA_ADDR_21 mpeval(0xf8004000 + 0,16,16) | |
143 | #define DMA_ADDR_22 mpeval(0xf8004000 + 64,16,16) | |
144 | #define DMA_ADDR_23 mpeval(0xf8004000 + 128,16,16) | |
145 | DMA2: nop | |
146 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA2)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_21, DMA_ADDR_22, "64'h100",1) | |
147 | stx %g2, [%g2] | |
148 | ldx [%g2 + 64], %g4 | |
149 | ldx [%g2 + 128], %g5 | |
150 | ldx [%g2 + 192], %g6 | |
151 | add %g2, %g3, %g2 | |
152 | #define DMA_ADDR_31 mpeval(0xf8006000 + 0,16,16) | |
153 | #define DMA_ADDR_32 mpeval(0xf8006000 + 64,16,16) | |
154 | #define DMA_ADDR_33 mpeval(0xf8006000 + 128,16,16) | |
155 | DMA3: nop | |
156 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA3)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_31, DMA_ADDR_32, "64'h100",1) | |
157 | stx %g2, [%g2] | |
158 | ldx [%g2 + 64], %g4 | |
159 | ldx [%g2 + 128], %g5 | |
160 | ldx [%g2 + 192], %g6 | |
161 | add %g2, %g3, %g2 | |
162 | #define DMA_ADDR_41 mpeval(0xf8008000 + 0,16,16) | |
163 | #define DMA_ADDR_42 mpeval(0xf8008000 + 64,16,16) | |
164 | #define DMA_ADDR_43 mpeval(0xf8008000 + 128,16,16) | |
165 | DMA4: nop | |
166 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA4)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_41, DMA_ADDR_42, "64'h100",1) | |
167 | stx %g2, [%g2] | |
168 | ldx [%g2 + 64], %g4 | |
169 | ldx [%g2 + 128], %g5 | |
170 | ldx [%g2 + 192], %g6 | |
171 | add %g2, %g3, %g2 | |
172 | #define DMA_ADDR_51 mpeval(0xf800a000 + 0,16,16) | |
173 | #define DMA_ADDR_52 mpeval(0xf800a000 + 64,16,16) | |
174 | #define DMA_ADDR_53 mpeval(0xf800a000 + 128,16,16) | |
175 | DMA5: nop | |
176 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA5)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_51, DMA_ADDR_52, "64'h100",1) | |
177 | stx %g2, [%g2] | |
178 | ldx [%g2 + 64], %g4 | |
179 | ldx [%g2 + 128], %g5 | |
180 | ldx [%g2 + 192], %g6 | |
181 | add %g2, %g3, %g2 | |
182 | #define DMA_ADDR_61 mpeval(0xf800c000 + 0,16,16) | |
183 | #define DMA_ADDR_62 mpeval(0xf800c000 + 64,16,16) | |
184 | #define DMA_ADDR_63 mpeval(0xf800c000 + 128,16,16) | |
185 | DMA6: nop | |
186 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA6)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_61, DMA_ADDR_62, "64'h100",1) | |
187 | stx %g2, [%g2] | |
188 | ldx [%g2 + 64], %g4 | |
189 | ldx [%g2 + 128], %g5 | |
190 | ldx [%g2 + 192], %g6 | |
191 | add %g2, %g3, %g2 | |
192 | #define DMA_ADDR_71 mpeval(0xf800e000 + 0,16,16) | |
193 | #define DMA_ADDR_72 mpeval(0xf800e000 + 64,16,16) | |
194 | #define DMA_ADDR_73 mpeval(0xf800e000 + 128,16,16) | |
195 | DMA7: nop | |
196 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA7)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_71, DMA_ADDR_72, "64'h100",1) | |
197 | stx %g2, [%g2] | |
198 | ldx [%g2 + 64], %g4 | |
199 | ldx [%g2 + 128], %g5 | |
200 | ldx [%g2 + 192], %g6 | |
201 | add %g2, %g3, %g2 | |
202 | #define DMA_ADDR_81 mpeval(0xf8010000 + 0,16,16) | |
203 | #define DMA_ADDR_82 mpeval(0xf8010000 + 64,16,16) | |
204 | #define DMA_ADDR_83 mpeval(0xf8010000 + 128,16,16) | |
205 | DMA8: nop | |
206 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA8)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_81, DMA_ADDR_82, "64'h100",1) | |
207 | stx %g2, [%g2] | |
208 | ldx [%g2 + 64], %g4 | |
209 | ldx [%g2 + 128], %g5 | |
210 | ldx [%g2 + 192], %g6 | |
211 | add %g2, %g3, %g2 | |
212 | #define DMA_ADDR_91 mpeval(0xf8012000 + 0,16,16) | |
213 | #define DMA_ADDR_92 mpeval(0xf8012000 + 64,16,16) | |
214 | #define DMA_ADDR_93 mpeval(0xf8012000 + 128,16,16) | |
215 | DMA9: nop | |
216 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA9)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_91, DMA_ADDR_92, "64'h100",1) | |
217 | stx %g2, [%g2] | |
218 | ldx [%g2 + 64], %g4 | |
219 | ldx [%g2 + 128], %g5 | |
220 | ldx [%g2 + 192], %g6 | |
221 | add %g2, %g3, %g2 | |
222 | #define DMA_ADDR_101 mpeval(0xf8014000 + 0,16,16) | |
223 | #define DMA_ADDR_102 mpeval(0xf8014000 + 64,16,16) | |
224 | #define DMA_ADDR_103 mpeval(0xf8014000 + 128,16,16) | |
225 | DMA10: nop | |
226 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA10)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_101, DMA_ADDR_102, "64'h100",1) | |
227 | stx %g2, [%g2] | |
228 | ldx [%g2 + 64], %g4 | |
229 | ldx [%g2 + 128], %g5 | |
230 | ldx [%g2 + 192], %g6 | |
231 | add %g2, %g3, %g2 | |
232 | #define DMA_ADDR_111 mpeval(0xf8016000 + 0,16,16) | |
233 | #define DMA_ADDR_112 mpeval(0xf8016000 + 64,16,16) | |
234 | #define DMA_ADDR_113 mpeval(0xf8016000 + 128,16,16) | |
235 | DMA11: nop | |
236 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA11)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_111, DMA_ADDR_112, "64'h100",1) | |
237 | stx %g2, [%g2] | |
238 | ldx [%g2 + 64], %g4 | |
239 | ldx [%g2 + 128], %g5 | |
240 | ldx [%g2 + 192], %g6 | |
241 | add %g2, %g3, %g2 | |
242 | #define DMA_ADDR_121 mpeval(0xf8018000 + 0,16,16) | |
243 | #define DMA_ADDR_122 mpeval(0xf8018000 + 64,16,16) | |
244 | #define DMA_ADDR_123 mpeval(0xf8018000 + 128,16,16) | |
245 | DMA12: nop | |
246 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA12)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_121, DMA_ADDR_122, "64'h100",1) | |
247 | stx %g2, [%g2] | |
248 | ldx [%g2 + 64], %g4 | |
249 | ldx [%g2 + 128], %g5 | |
250 | ldx [%g2 + 192], %g6 | |
251 | add %g2, %g3, %g2 | |
252 | #define DMA_ADDR_131 mpeval(0xf801a000 + 0,16,16) | |
253 | #define DMA_ADDR_132 mpeval(0xf801a000 + 64,16,16) | |
254 | #define DMA_ADDR_133 mpeval(0xf801a000 + 128,16,16) | |
255 | DMA13: nop | |
256 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA13)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_131, DMA_ADDR_132, "64'h100",1) | |
257 | stx %g2, [%g2] | |
258 | ldx [%g2 + 64], %g4 | |
259 | ldx [%g2 + 128], %g5 | |
260 | ldx [%g2 + 192], %g6 | |
261 | add %g2, %g3, %g2 | |
262 | #define DMA_ADDR_141 mpeval(0xf801c000 + 0,16,16) | |
263 | #define DMA_ADDR_142 mpeval(0xf801c000 + 64,16,16) | |
264 | #define DMA_ADDR_143 mpeval(0xf801c000 + 128,16,16) | |
265 | DMA14: nop | |
266 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA14)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_141, DMA_ADDR_142, "64'h100",1) | |
267 | stx %g2, [%g2] | |
268 | ldx [%g2 + 64], %g4 | |
269 | ldx [%g2 + 128], %g5 | |
270 | ldx [%g2 + 192], %g6 | |
271 | add %g2, %g3, %g2 | |
272 | #define DMA_ADDR_151 mpeval(0xf801e000 + 0,16,16) | |
273 | #define DMA_ADDR_152 mpeval(0xf801e000 + 64,16,16) | |
274 | #define DMA_ADDR_153 mpeval(0xf801e000 + 128,16,16) | |
275 | DMA15: nop | |
276 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA15)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_151, DMA_ADDR_152, "64'h100",1) | |
277 | stx %g2, [%g2] | |
278 | ldx [%g2 + 64], %g4 | |
279 | ldx [%g2 + 128], %g5 | |
280 | ldx [%g2 + 192], %g6 | |
281 | add %g2, %g3, %g2 | |
282 | #define DMA_ADDR_161 mpeval(0xf8020000 + 0,16,16) | |
283 | #define DMA_ADDR_162 mpeval(0xf8020000 + 64,16,16) | |
284 | #define DMA_ADDR_163 mpeval(0xf8020000 + 128,16,16) | |
285 | DMA16: nop | |
286 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA16)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_161, DMA_ADDR_162, "64'h100",1) | |
287 | stx %g2, [%g2] | |
288 | ldx [%g2 + 64], %g4 | |
289 | ldx [%g2 + 128], %g5 | |
290 | ldx [%g2 + 192], %g6 | |
291 | add %g2, %g3, %g2 | |
292 | #define DMA_ADDR_171 mpeval(0xf8022000 + 0,16,16) | |
293 | #define DMA_ADDR_172 mpeval(0xf8022000 + 64,16,16) | |
294 | #define DMA_ADDR_173 mpeval(0xf8022000 + 128,16,16) | |
295 | DMA17: nop | |
296 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA17)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_171, DMA_ADDR_172, "64'h100",1) | |
297 | stx %g2, [%g2] | |
298 | ldx [%g2 + 64], %g4 | |
299 | ldx [%g2 + 128], %g5 | |
300 | ldx [%g2 + 192], %g6 | |
301 | add %g2, %g3, %g2 | |
302 | #define DMA_ADDR_181 mpeval(0xf8024000 + 0,16,16) | |
303 | #define DMA_ADDR_182 mpeval(0xf8024000 + 64,16,16) | |
304 | #define DMA_ADDR_183 mpeval(0xf8024000 + 128,16,16) | |
305 | DMA18: nop | |
306 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA18)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_181, DMA_ADDR_182, "64'h100",1) | |
307 | stx %g2, [%g2] | |
308 | ldx [%g2 + 64], %g4 | |
309 | ldx [%g2 + 128], %g5 | |
310 | ldx [%g2 + 192], %g6 | |
311 | add %g2, %g3, %g2 | |
312 | #define DMA_ADDR_191 mpeval(0xf8026000 + 0,16,16) | |
313 | #define DMA_ADDR_192 mpeval(0xf8026000 + 64,16,16) | |
314 | #define DMA_ADDR_193 mpeval(0xf8026000 + 128,16,16) | |
315 | DMA19: nop | |
316 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA19)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_191, DMA_ADDR_192, "64'h100",1) | |
317 | stx %g2, [%g2] | |
318 | ldx [%g2 + 64], %g4 | |
319 | ldx [%g2 + 128], %g5 | |
320 | ldx [%g2 + 192], %g6 | |
321 | add %g2, %g3, %g2 | |
322 | #define DMA_ADDR_201 mpeval(0xf8028000 + 0,16,16) | |
323 | #define DMA_ADDR_202 mpeval(0xf8028000 + 64,16,16) | |
324 | #define DMA_ADDR_203 mpeval(0xf8028000 + 128,16,16) | |
325 | DMA20: nop | |
326 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA20)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_201, DMA_ADDR_202, "64'h100",1) | |
327 | stx %g2, [%g2] | |
328 | ldx [%g2 + 64], %g4 | |
329 | ldx [%g2 + 128], %g5 | |
330 | ldx [%g2 + 192], %g6 | |
331 | add %g2, %g3, %g2 | |
332 | #define DMA_ADDR_211 mpeval(0xf802a000 + 0,16,16) | |
333 | #define DMA_ADDR_212 mpeval(0xf802a000 + 64,16,16) | |
334 | #define DMA_ADDR_213 mpeval(0xf802a000 + 128,16,16) | |
335 | DMA21: nop | |
336 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA21)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_211, DMA_ADDR_212, "64'h100",1) | |
337 | stx %g2, [%g2] | |
338 | ldx [%g2 + 64], %g4 | |
339 | ldx [%g2 + 128], %g5 | |
340 | ldx [%g2 + 192], %g6 | |
341 | add %g2, %g3, %g2 | |
342 | #define DMA_ADDR_221 mpeval(0xf802c000 + 0,16,16) | |
343 | #define DMA_ADDR_222 mpeval(0xf802c000 + 64,16,16) | |
344 | #define DMA_ADDR_223 mpeval(0xf802c000 + 128,16,16) | |
345 | DMA22: nop | |
346 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA22)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_221, DMA_ADDR_222, "64'h100",1) | |
347 | stx %g2, [%g2] | |
348 | ldx [%g2 + 64], %g4 | |
349 | ldx [%g2 + 128], %g5 | |
350 | ldx [%g2 + 192], %g6 | |
351 | add %g2, %g3, %g2 | |
352 | #define DMA_ADDR_231 mpeval(0xf802e000 + 0,16,16) | |
353 | #define DMA_ADDR_232 mpeval(0xf802e000 + 64,16,16) | |
354 | #define DMA_ADDR_233 mpeval(0xf802e000 + 128,16,16) | |
355 | DMA23: nop | |
356 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA23)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_231, DMA_ADDR_232, "64'h100",1) | |
357 | stx %g2, [%g2] | |
358 | ldx [%g2 + 64], %g4 | |
359 | ldx [%g2 + 128], %g5 | |
360 | ldx [%g2 + 192], %g6 | |
361 | add %g2, %g3, %g2 | |
362 | #define DMA_ADDR_241 mpeval(0xf8030000 + 0,16,16) | |
363 | #define DMA_ADDR_242 mpeval(0xf8030000 + 64,16,16) | |
364 | #define DMA_ADDR_243 mpeval(0xf8030000 + 128,16,16) | |
365 | DMA24: nop | |
366 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA24)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_241, DMA_ADDR_242, "64'h100",1) | |
367 | stx %g2, [%g2] | |
368 | ldx [%g2 + 64], %g4 | |
369 | ldx [%g2 + 128], %g5 | |
370 | ldx [%g2 + 192], %g6 | |
371 | add %g2, %g3, %g2 | |
372 | #define DMA_ADDR_251 mpeval(0xf8032000 + 0,16,16) | |
373 | #define DMA_ADDR_252 mpeval(0xf8032000 + 64,16,16) | |
374 | #define DMA_ADDR_253 mpeval(0xf8032000 + 128,16,16) | |
375 | DMA25: nop | |
376 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA25)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_251, DMA_ADDR_252, "64'h100",1) | |
377 | stx %g2, [%g2] | |
378 | ldx [%g2 + 64], %g4 | |
379 | ldx [%g2 + 128], %g5 | |
380 | ldx [%g2 + 192], %g6 | |
381 | add %g2, %g3, %g2 | |
382 | #define DMA_ADDR_261 mpeval(0xf8034000 + 0,16,16) | |
383 | #define DMA_ADDR_262 mpeval(0xf8034000 + 64,16,16) | |
384 | #define DMA_ADDR_263 mpeval(0xf8034000 + 128,16,16) | |
385 | DMA26: nop | |
386 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA26)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_261, DMA_ADDR_262, "64'h100",1) | |
387 | stx %g2, [%g2] | |
388 | ldx [%g2 + 64], %g4 | |
389 | ldx [%g2 + 128], %g5 | |
390 | ldx [%g2 + 192], %g6 | |
391 | add %g2, %g3, %g2 | |
392 | #define DMA_ADDR_271 mpeval(0xf8036000 + 0,16,16) | |
393 | #define DMA_ADDR_272 mpeval(0xf8036000 + 64,16,16) | |
394 | #define DMA_ADDR_273 mpeval(0xf8036000 + 128,16,16) | |
395 | DMA27: nop | |
396 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA27)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_271, DMA_ADDR_272, "64'h100",1) | |
397 | stx %g2, [%g2] | |
398 | ldx [%g2 + 64], %g4 | |
399 | ldx [%g2 + 128], %g5 | |
400 | ldx [%g2 + 192], %g6 | |
401 | add %g2, %g3, %g2 | |
402 | #define DMA_ADDR_281 mpeval(0xf8038000 + 0,16,16) | |
403 | #define DMA_ADDR_282 mpeval(0xf8038000 + 64,16,16) | |
404 | #define DMA_ADDR_283 mpeval(0xf8038000 + 128,16,16) | |
405 | DMA28: nop | |
406 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA28)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_281, DMA_ADDR_282, "64'h100",1) | |
407 | stx %g2, [%g2] | |
408 | ldx [%g2 + 64], %g4 | |
409 | ldx [%g2 + 128], %g5 | |
410 | ldx [%g2 + 192], %g6 | |
411 | add %g2, %g3, %g2 | |
412 | #define DMA_ADDR_291 mpeval(0xf803a000 + 0,16,16) | |
413 | #define DMA_ADDR_292 mpeval(0xf803a000 + 64,16,16) | |
414 | #define DMA_ADDR_293 mpeval(0xf803a000 + 128,16,16) | |
415 | DMA29: nop | |
416 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA29)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_291, DMA_ADDR_292, "64'h100",1) | |
417 | stx %g2, [%g2] | |
418 | ldx [%g2 + 64], %g4 | |
419 | ldx [%g2 + 128], %g5 | |
420 | ldx [%g2 + 192], %g6 | |
421 | add %g2, %g3, %g2 | |
422 | #define DMA_ADDR_301 mpeval(0xf803c000 + 0,16,16) | |
423 | #define DMA_ADDR_302 mpeval(0xf803c000 + 64,16,16) | |
424 | #define DMA_ADDR_303 mpeval(0xf803c000 + 128,16,16) | |
425 | DMA30: nop | |
426 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA30)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_301, DMA_ADDR_302, "64'h100",1) | |
427 | stx %g2, [%g2] | |
428 | ldx [%g2 + 64], %g4 | |
429 | ldx [%g2 + 128], %g5 | |
430 | ldx [%g2 + 192], %g6 | |
431 | add %g2, %g3, %g2 | |
432 | #define DMA_ADDR_311 mpeval(0xf803e000 + 0,16,16) | |
433 | #define DMA_ADDR_312 mpeval(0xf803e000 + 64,16,16) | |
434 | #define DMA_ADDR_313 mpeval(0xf803e000 + 128,16,16) | |
435 | DMA31: nop | |
436 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA31)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_311, DMA_ADDR_312, "64'h100",1) | |
437 | stx %g2, [%g2] | |
438 | ldx [%g2 + 64], %g4 | |
439 | ldx [%g2 + 128], %g5 | |
440 | ldx [%g2 + 192], %g6 | |
441 | add %g2, %g3, %g2 | |
442 | #define DMA_ADDR_321 mpeval(0xf8040000 + 0,16,16) | |
443 | #define DMA_ADDR_322 mpeval(0xf8040000 + 64,16,16) | |
444 | #define DMA_ADDR_323 mpeval(0xf8040000 + 128,16,16) | |
445 | DMA32: nop | |
446 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA32)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_321, DMA_ADDR_322, "64'h100",1) | |
447 | stx %g2, [%g2] | |
448 | ldx [%g2 + 64], %g4 | |
449 | ldx [%g2 + 128], %g5 | |
450 | ldx [%g2 + 192], %g6 | |
451 | add %g2, %g3, %g2 | |
452 | #define DMA_ADDR_331 mpeval(0xf8042000 + 0,16,16) | |
453 | #define DMA_ADDR_332 mpeval(0xf8042000 + 64,16,16) | |
454 | #define DMA_ADDR_333 mpeval(0xf8042000 + 128,16,16) | |
455 | DMA33: nop | |
456 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA33)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_331, DMA_ADDR_332, "64'h100",1) | |
457 | stx %g2, [%g2] | |
458 | ldx [%g2 + 64], %g4 | |
459 | ldx [%g2 + 128], %g5 | |
460 | ldx [%g2 + 192], %g6 | |
461 | add %g2, %g3, %g2 | |
462 | #define DMA_ADDR_341 mpeval(0xf8044000 + 0,16,16) | |
463 | #define DMA_ADDR_342 mpeval(0xf8044000 + 64,16,16) | |
464 | #define DMA_ADDR_343 mpeval(0xf8044000 + 128,16,16) | |
465 | DMA34: nop | |
466 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA34)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_341, DMA_ADDR_342, "64'h100",1) | |
467 | stx %g2, [%g2] | |
468 | ldx [%g2 + 64], %g4 | |
469 | ldx [%g2 + 128], %g5 | |
470 | ldx [%g2 + 192], %g6 | |
471 | add %g2, %g3, %g2 | |
472 | #define DMA_ADDR_351 mpeval(0xf8046000 + 0,16,16) | |
473 | #define DMA_ADDR_352 mpeval(0xf8046000 + 64,16,16) | |
474 | #define DMA_ADDR_353 mpeval(0xf8046000 + 128,16,16) | |
475 | DMA35: nop | |
476 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA35)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_351, DMA_ADDR_352, "64'h100",1) | |
477 | stx %g2, [%g2] | |
478 | ldx [%g2 + 64], %g4 | |
479 | ldx [%g2 + 128], %g5 | |
480 | ldx [%g2 + 192], %g6 | |
481 | add %g2, %g3, %g2 | |
482 | #define DMA_ADDR_361 mpeval(0xf8048000 + 0,16,16) | |
483 | #define DMA_ADDR_362 mpeval(0xf8048000 + 64,16,16) | |
484 | #define DMA_ADDR_363 mpeval(0xf8048000 + 128,16,16) | |
485 | DMA36: nop | |
486 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA36)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_361, DMA_ADDR_362, "64'h100",1) | |
487 | stx %g2, [%g2] | |
488 | ldx [%g2 + 64], %g4 | |
489 | ldx [%g2 + 128], %g5 | |
490 | ldx [%g2 + 192], %g6 | |
491 | add %g2, %g3, %g2 | |
492 | #define DMA_ADDR_371 mpeval(0xf804a000 + 0,16,16) | |
493 | #define DMA_ADDR_372 mpeval(0xf804a000 + 64,16,16) | |
494 | #define DMA_ADDR_373 mpeval(0xf804a000 + 128,16,16) | |
495 | DMA37: nop | |
496 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA37)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_371, DMA_ADDR_372, "64'h100",1) | |
497 | stx %g2, [%g2] | |
498 | ldx [%g2 + 64], %g4 | |
499 | ldx [%g2 + 128], %g5 | |
500 | ldx [%g2 + 192], %g6 | |
501 | add %g2, %g3, %g2 | |
502 | #define DMA_ADDR_381 mpeval(0xf804c000 + 0,16,16) | |
503 | #define DMA_ADDR_382 mpeval(0xf804c000 + 64,16,16) | |
504 | #define DMA_ADDR_383 mpeval(0xf804c000 + 128,16,16) | |
505 | DMA38: nop | |
506 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA38)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_381, DMA_ADDR_382, "64'h100",1) | |
507 | stx %g2, [%g2] | |
508 | ldx [%g2 + 64], %g4 | |
509 | ldx [%g2 + 128], %g5 | |
510 | ldx [%g2 + 192], %g6 | |
511 | add %g2, %g3, %g2 | |
512 | #define DMA_ADDR_391 mpeval(0xf804e000 + 0,16,16) | |
513 | #define DMA_ADDR_392 mpeval(0xf804e000 + 64,16,16) | |
514 | #define DMA_ADDR_393 mpeval(0xf804e000 + 128,16,16) | |
515 | DMA39: nop | |
516 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA39)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_391, DMA_ADDR_392, "64'h100",1) | |
517 | stx %g2, [%g2] | |
518 | ldx [%g2 + 64], %g4 | |
519 | ldx [%g2 + 128], %g5 | |
520 | ldx [%g2 + 192], %g6 | |
521 | add %g2, %g3, %g2 | |
522 | #define DMA_ADDR_401 mpeval(0xf8050000 + 0,16,16) | |
523 | #define DMA_ADDR_402 mpeval(0xf8050000 + 64,16,16) | |
524 | #define DMA_ADDR_403 mpeval(0xf8050000 + 128,16,16) | |
525 | DMA40: nop | |
526 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA40)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_401, DMA_ADDR_402, "64'h100",1) | |
527 | stx %g2, [%g2] | |
528 | ldx [%g2 + 64], %g4 | |
529 | ldx [%g2 + 128], %g5 | |
530 | ldx [%g2 + 192], %g6 | |
531 | add %g2, %g3, %g2 | |
532 | #define DMA_ADDR_411 mpeval(0xf8052000 + 0,16,16) | |
533 | #define DMA_ADDR_412 mpeval(0xf8052000 + 64,16,16) | |
534 | #define DMA_ADDR_413 mpeval(0xf8052000 + 128,16,16) | |
535 | DMA41: nop | |
536 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA41)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_411, DMA_ADDR_412, "64'h100",1) | |
537 | stx %g2, [%g2] | |
538 | ldx [%g2 + 64], %g4 | |
539 | ldx [%g2 + 128], %g5 | |
540 | ldx [%g2 + 192], %g6 | |
541 | add %g2, %g3, %g2 | |
542 | #define DMA_ADDR_421 mpeval(0xf8054000 + 0,16,16) | |
543 | #define DMA_ADDR_422 mpeval(0xf8054000 + 64,16,16) | |
544 | #define DMA_ADDR_423 mpeval(0xf8054000 + 128,16,16) | |
545 | DMA42: nop | |
546 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA42)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_421, DMA_ADDR_422, "64'h100",1) | |
547 | stx %g2, [%g2] | |
548 | ldx [%g2 + 64], %g4 | |
549 | ldx [%g2 + 128], %g5 | |
550 | ldx [%g2 + 192], %g6 | |
551 | add %g2, %g3, %g2 | |
552 | #define DMA_ADDR_431 mpeval(0xf8056000 + 0,16,16) | |
553 | #define DMA_ADDR_432 mpeval(0xf8056000 + 64,16,16) | |
554 | #define DMA_ADDR_433 mpeval(0xf8056000 + 128,16,16) | |
555 | DMA43: nop | |
556 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA43)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_431, DMA_ADDR_432, "64'h100",1) | |
557 | stx %g2, [%g2] | |
558 | ldx [%g2 + 64], %g4 | |
559 | ldx [%g2 + 128], %g5 | |
560 | ldx [%g2 + 192], %g6 | |
561 | add %g2, %g3, %g2 | |
562 | #define DMA_ADDR_441 mpeval(0xf8058000 + 0,16,16) | |
563 | #define DMA_ADDR_442 mpeval(0xf8058000 + 64,16,16) | |
564 | #define DMA_ADDR_443 mpeval(0xf8058000 + 128,16,16) | |
565 | DMA44: nop | |
566 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA44)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_441, DMA_ADDR_442, "64'h100",1) | |
567 | stx %g2, [%g2] | |
568 | ldx [%g2 + 64], %g4 | |
569 | ldx [%g2 + 128], %g5 | |
570 | ldx [%g2 + 192], %g6 | |
571 | add %g2, %g3, %g2 | |
572 | #define DMA_ADDR_451 mpeval(0xf805a000 + 0,16,16) | |
573 | #define DMA_ADDR_452 mpeval(0xf805a000 + 64,16,16) | |
574 | #define DMA_ADDR_453 mpeval(0xf805a000 + 128,16,16) | |
575 | DMA45: nop | |
576 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA45)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_451, DMA_ADDR_452, "64'h100",1) | |
577 | stx %g2, [%g2] | |
578 | ldx [%g2 + 64], %g4 | |
579 | ldx [%g2 + 128], %g5 | |
580 | ldx [%g2 + 192], %g6 | |
581 | add %g2, %g3, %g2 | |
582 | #define DMA_ADDR_461 mpeval(0xf805c000 + 0,16,16) | |
583 | #define DMA_ADDR_462 mpeval(0xf805c000 + 64,16,16) | |
584 | #define DMA_ADDR_463 mpeval(0xf805c000 + 128,16,16) | |
585 | DMA46: nop | |
586 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA46)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_461, DMA_ADDR_462, "64'h100",1) | |
587 | stx %g2, [%g2] | |
588 | ldx [%g2 + 64], %g4 | |
589 | ldx [%g2 + 128], %g5 | |
590 | ldx [%g2 + 192], %g6 | |
591 | add %g2, %g3, %g2 | |
592 | #define DMA_ADDR_471 mpeval(0xf805e000 + 0,16,16) | |
593 | #define DMA_ADDR_472 mpeval(0xf805e000 + 64,16,16) | |
594 | #define DMA_ADDR_473 mpeval(0xf805e000 + 128,16,16) | |
595 | DMA47: nop | |
596 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA47)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_471, DMA_ADDR_472, "64'h100",1) | |
597 | stx %g2, [%g2] | |
598 | ldx [%g2 + 64], %g4 | |
599 | ldx [%g2 + 128], %g5 | |
600 | ldx [%g2 + 192], %g6 | |
601 | add %g2, %g3, %g2 | |
602 | #define DMA_ADDR_481 mpeval(0xf8060000 + 0,16,16) | |
603 | #define DMA_ADDR_482 mpeval(0xf8060000 + 64,16,16) | |
604 | #define DMA_ADDR_483 mpeval(0xf8060000 + 128,16,16) | |
605 | DMA48: nop | |
606 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA48)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_481, DMA_ADDR_482, "64'h100",1) | |
607 | stx %g2, [%g2] | |
608 | ldx [%g2 + 64], %g4 | |
609 | ldx [%g2 + 128], %g5 | |
610 | ldx [%g2 + 192], %g6 | |
611 | add %g2, %g3, %g2 | |
612 | #define DMA_ADDR_491 mpeval(0xf8062000 + 0,16,16) | |
613 | #define DMA_ADDR_492 mpeval(0xf8062000 + 64,16,16) | |
614 | #define DMA_ADDR_493 mpeval(0xf8062000 + 128,16,16) | |
615 | DMA49: nop | |
616 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA49)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_491, DMA_ADDR_492, "64'h100",1) | |
617 | stx %g2, [%g2] | |
618 | ldx [%g2 + 64], %g4 | |
619 | ldx [%g2 + 128], %g5 | |
620 | ldx [%g2 + 192], %g6 | |
621 | add %g2, %g3, %g2 | |
622 | #define DMA_ADDR_501 mpeval(0xf8064000 + 0,16,16) | |
623 | #define DMA_ADDR_502 mpeval(0xf8064000 + 64,16,16) | |
624 | #define DMA_ADDR_503 mpeval(0xf8064000 + 128,16,16) | |
625 | DMA50: nop | |
626 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA50)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_501, DMA_ADDR_502, "64'h100",1) | |
627 | stx %g2, [%g2] | |
628 | ldx [%g2 + 64], %g4 | |
629 | ldx [%g2 + 128], %g5 | |
630 | ldx [%g2 + 192], %g6 | |
631 | add %g2, %g3, %g2 | |
632 | #define DMA_ADDR_511 mpeval(0xf8066000 + 0,16,16) | |
633 | #define DMA_ADDR_512 mpeval(0xf8066000 + 64,16,16) | |
634 | #define DMA_ADDR_513 mpeval(0xf8066000 + 128,16,16) | |
635 | DMA51: nop | |
636 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA51)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_511, DMA_ADDR_512, "64'h100",1) | |
637 | stx %g2, [%g2] | |
638 | ldx [%g2 + 64], %g4 | |
639 | ldx [%g2 + 128], %g5 | |
640 | ldx [%g2 + 192], %g6 | |
641 | add %g2, %g3, %g2 | |
642 | #define DMA_ADDR_521 mpeval(0xf8068000 + 0,16,16) | |
643 | #define DMA_ADDR_522 mpeval(0xf8068000 + 64,16,16) | |
644 | #define DMA_ADDR_523 mpeval(0xf8068000 + 128,16,16) | |
645 | DMA52: nop | |
646 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA52)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_521, DMA_ADDR_522, "64'h100",1) | |
647 | stx %g2, [%g2] | |
648 | ldx [%g2 + 64], %g4 | |
649 | ldx [%g2 + 128], %g5 | |
650 | ldx [%g2 + 192], %g6 | |
651 | add %g2, %g3, %g2 | |
652 | #define DMA_ADDR_531 mpeval(0xf806a000 + 0,16,16) | |
653 | #define DMA_ADDR_532 mpeval(0xf806a000 + 64,16,16) | |
654 | #define DMA_ADDR_533 mpeval(0xf806a000 + 128,16,16) | |
655 | DMA53: nop | |
656 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA53)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_531, DMA_ADDR_532, "64'h100",1) | |
657 | stx %g2, [%g2] | |
658 | ldx [%g2 + 64], %g4 | |
659 | ldx [%g2 + 128], %g5 | |
660 | ldx [%g2 + 192], %g6 | |
661 | add %g2, %g3, %g2 | |
662 | #define DMA_ADDR_541 mpeval(0xf806c000 + 0,16,16) | |
663 | #define DMA_ADDR_542 mpeval(0xf806c000 + 64,16,16) | |
664 | #define DMA_ADDR_543 mpeval(0xf806c000 + 128,16,16) | |
665 | DMA54: nop | |
666 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA54)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_541, DMA_ADDR_542, "64'h100",1) | |
667 | stx %g2, [%g2] | |
668 | ldx [%g2 + 64], %g4 | |
669 | ldx [%g2 + 128], %g5 | |
670 | ldx [%g2 + 192], %g6 | |
671 | add %g2, %g3, %g2 | |
672 | #define DMA_ADDR_551 mpeval(0xf806e000 + 0,16,16) | |
673 | #define DMA_ADDR_552 mpeval(0xf806e000 + 64,16,16) | |
674 | #define DMA_ADDR_553 mpeval(0xf806e000 + 128,16,16) | |
675 | DMA55: nop | |
676 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA55)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_551, DMA_ADDR_552, "64'h100",1) | |
677 | stx %g2, [%g2] | |
678 | ldx [%g2 + 64], %g4 | |
679 | ldx [%g2 + 128], %g5 | |
680 | ldx [%g2 + 192], %g6 | |
681 | add %g2, %g3, %g2 | |
682 | #define DMA_ADDR_561 mpeval(0xf8070000 + 0,16,16) | |
683 | #define DMA_ADDR_562 mpeval(0xf8070000 + 64,16,16) | |
684 | #define DMA_ADDR_563 mpeval(0xf8070000 + 128,16,16) | |
685 | DMA56: nop | |
686 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA56)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_561, DMA_ADDR_562, "64'h100",1) | |
687 | stx %g2, [%g2] | |
688 | ldx [%g2 + 64], %g4 | |
689 | ldx [%g2 + 128], %g5 | |
690 | ldx [%g2 + 192], %g6 | |
691 | add %g2, %g3, %g2 | |
692 | #define DMA_ADDR_571 mpeval(0xf8072000 + 0,16,16) | |
693 | #define DMA_ADDR_572 mpeval(0xf8072000 + 64,16,16) | |
694 | #define DMA_ADDR_573 mpeval(0xf8072000 + 128,16,16) | |
695 | DMA57: nop | |
696 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA57)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_571, DMA_ADDR_572, "64'h100",1) | |
697 | stx %g2, [%g2] | |
698 | ldx [%g2 + 64], %g4 | |
699 | ldx [%g2 + 128], %g5 | |
700 | ldx [%g2 + 192], %g6 | |
701 | add %g2, %g3, %g2 | |
702 | #define DMA_ADDR_581 mpeval(0xf8074000 + 0,16,16) | |
703 | #define DMA_ADDR_582 mpeval(0xf8074000 + 64,16,16) | |
704 | #define DMA_ADDR_583 mpeval(0xf8074000 + 128,16,16) | |
705 | DMA58: nop | |
706 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA58)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_581, DMA_ADDR_582, "64'h100",1) | |
707 | stx %g2, [%g2] | |
708 | ldx [%g2 + 64], %g4 | |
709 | ldx [%g2 + 128], %g5 | |
710 | ldx [%g2 + 192], %g6 | |
711 | add %g2, %g3, %g2 | |
712 | #define DMA_ADDR_591 mpeval(0xf8076000 + 0,16,16) | |
713 | #define DMA_ADDR_592 mpeval(0xf8076000 + 64,16,16) | |
714 | #define DMA_ADDR_593 mpeval(0xf8076000 + 128,16,16) | |
715 | DMA59: nop | |
716 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA59)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_591, DMA_ADDR_592, "64'h100",1) | |
717 | stx %g2, [%g2] | |
718 | ldx [%g2 + 64], %g4 | |
719 | ldx [%g2 + 128], %g5 | |
720 | ldx [%g2 + 192], %g6 | |
721 | add %g2, %g3, %g2 | |
722 | #define DMA_ADDR_601 mpeval(0xf8078000 + 0,16,16) | |
723 | #define DMA_ADDR_602 mpeval(0xf8078000 + 64,16,16) | |
724 | #define DMA_ADDR_603 mpeval(0xf8078000 + 128,16,16) | |
725 | DMA60: nop | |
726 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA60)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_601, DMA_ADDR_602, "64'h100",1) | |
727 | stx %g2, [%g2] | |
728 | ldx [%g2 + 64], %g4 | |
729 | ldx [%g2 + 128], %g5 | |
730 | ldx [%g2 + 192], %g6 | |
731 | add %g2, %g3, %g2 | |
732 | #define DMA_ADDR_611 mpeval(0xf807a000 + 0,16,16) | |
733 | #define DMA_ADDR_612 mpeval(0xf807a000 + 64,16,16) | |
734 | #define DMA_ADDR_613 mpeval(0xf807a000 + 128,16,16) | |
735 | DMA61: nop | |
736 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA61)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_611, DMA_ADDR_612, "64'h100",1) | |
737 | stx %g2, [%g2] | |
738 | ldx [%g2 + 64], %g4 | |
739 | ldx [%g2 + 128], %g5 | |
740 | ldx [%g2 + 192], %g6 | |
741 | add %g2, %g3, %g2 | |
742 | #define DMA_ADDR_621 mpeval(0xf807c000 + 0,16,16) | |
743 | #define DMA_ADDR_622 mpeval(0xf807c000 + 64,16,16) | |
744 | #define DMA_ADDR_623 mpeval(0xf807c000 + 128,16,16) | |
745 | DMA62: nop | |
746 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA62)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_621, DMA_ADDR_622, "64'h100",1) | |
747 | stx %g2, [%g2] | |
748 | ldx [%g2 + 64], %g4 | |
749 | ldx [%g2 + 128], %g5 | |
750 | ldx [%g2 + 192], %g6 | |
751 | add %g2, %g3, %g2 | |
752 | #define DMA_ADDR_631 mpeval(0xf807e000 + 0,16,16) | |
753 | #define DMA_ADDR_632 mpeval(0xf807e000 + 64,16,16) | |
754 | #define DMA_ADDR_633 mpeval(0xf807e000 + 128,16,16) | |
755 | DMA63: nop | |
756 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA63)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_631, DMA_ADDR_632, "64'h100",1) | |
757 | stx %g2, [%g2] | |
758 | ldx [%g2 + 64], %g4 | |
759 | ldx [%g2 + 128], %g5 | |
760 | ldx [%g2 + 192], %g6 | |
761 | add %g2, %g3, %g2 | |
762 | DMA64: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA64) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_02, DMA_ADDR_03, "64'h80",1) | |
763 | DMA65: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA65) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_12, DMA_ADDR_13, "64'h80",1) | |
764 | DMA66: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA66) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_22, DMA_ADDR_23, "64'h80",1) | |
765 | DMA67: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA67) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_32, DMA_ADDR_33, "64'h80",1) | |
766 | DMA68: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA68) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_42, DMA_ADDR_43, "64'h80",1) | |
767 | DMA69: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA69) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_52, DMA_ADDR_53, "64'h80",1) | |
768 | DMA70: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA70) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_62, DMA_ADDR_63, "64'h80",1) | |
769 | DMA71: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA71) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_72, DMA_ADDR_73, "64'h80",1) | |
770 | DMA72: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA72) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_82, DMA_ADDR_83, "64'h80",1) | |
771 | DMA73: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA73) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_92, DMA_ADDR_93, "64'h80",1) | |
772 | DMA74: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA74) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_102, DMA_ADDR_103, "64'h80",1) | |
773 | DMA75: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA75) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_112, DMA_ADDR_113, "64'h80",1) | |
774 | DMA76: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA76) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_122, DMA_ADDR_123, "64'h80",1) | |
775 | DMA77: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA77) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_132, DMA_ADDR_133, "64'h80",1) | |
776 | DMA78: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA78) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_142, DMA_ADDR_143, "64'h80",1) | |
777 | DMA79: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA79) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_152, DMA_ADDR_153, "64'h80",1) | |
778 | DMA80: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA80) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_162, DMA_ADDR_163, "64'h80",1) | |
779 | DMA81: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA81) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_172, DMA_ADDR_173, "64'h80",1) | |
780 | DMA82: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA82) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_182, DMA_ADDR_183, "64'h80",1) | |
781 | DMA83: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA83) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_192, DMA_ADDR_193, "64'h80",1) | |
782 | DMA84: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA84) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_202, DMA_ADDR_203, "64'h80",1) | |
783 | DMA85: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA85) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_212, DMA_ADDR_213, "64'h80",1) | |
784 | DMA86: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA86) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_222, DMA_ADDR_223, "64'h80",1) | |
785 | DMA87: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA87) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_232, DMA_ADDR_233, "64'h80",1) | |
786 | DMA88: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA88) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_242, DMA_ADDR_243, "64'h80",1) | |
787 | DMA89: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA89) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_252, DMA_ADDR_253, "64'h80",1) | |
788 | DMA90: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA90) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_262, DMA_ADDR_263, "64'h80",1) | |
789 | DMA91: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA91) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_272, DMA_ADDR_273, "64'h80",1) | |
790 | DMA92: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA92) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_282, DMA_ADDR_283, "64'h80",1) | |
791 | DMA93: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA93) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_292, DMA_ADDR_293, "64'h80",1) | |
792 | DMA94: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA94) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_302, DMA_ADDR_303, "64'h80",1) | |
793 | DMA95: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA95) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_312, DMA_ADDR_313, "64'h80",1) | |
794 | DMA96: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA96) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_322, DMA_ADDR_323, "64'h80",1) | |
795 | DMA97: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA97) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_332, DMA_ADDR_333, "64'h80",1) | |
796 | DMA98: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA98) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_342, DMA_ADDR_343, "64'h80",1) | |
797 | DMA99: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA99) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_352, DMA_ADDR_353, "64'h80",1) | |
798 | DMA100: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA100) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_362, DMA_ADDR_363, "64'h80",1) | |
799 | DMA101: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA101) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_372, DMA_ADDR_373, "64'h80",1) | |
800 | DMA102: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA102) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_382, DMA_ADDR_383, "64'h80",1) | |
801 | DMA103: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA103) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_392, DMA_ADDR_393, "64'h80",1) | |
802 | DMA104: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA104) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_402, DMA_ADDR_403, "64'h80",1) | |
803 | DMA105: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA105) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_412, DMA_ADDR_413, "64'h80",1) | |
804 | DMA106: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA106) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_422, DMA_ADDR_423, "64'h80",1) | |
805 | DMA107: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA107) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_432, DMA_ADDR_433, "64'h80",1) | |
806 | DMA108: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA108) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_442, DMA_ADDR_443, "64'h80",1) | |
807 | DMA109: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA109) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_452, DMA_ADDR_453, "64'h80",1) | |
808 | DMA110: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA110) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_462, DMA_ADDR_463, "64'h80",1) | |
809 | DMA111: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA111) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_472, DMA_ADDR_473, "64'h80",1) | |
810 | DMA112: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA112) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_482, DMA_ADDR_483, "64'h80",1) | |
811 | DMA113: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA113) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_492, DMA_ADDR_493, "64'h80",1) | |
812 | DMA114: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA114) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_502, DMA_ADDR_503, "64'h80",1) | |
813 | DMA115: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA115) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_512, DMA_ADDR_513, "64'h80",1) | |
814 | DMA116: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA116) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_522, DMA_ADDR_523, "64'h80",1) | |
815 | DMA117: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA117) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_532, DMA_ADDR_533, "64'h80",1) | |
816 | DMA118: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA118) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_542, DMA_ADDR_543, "64'h80",1) | |
817 | DMA119: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA119) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_552, DMA_ADDR_553, "64'h80",1) | |
818 | DMA120: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA120) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_562, DMA_ADDR_563, "64'h80",1) | |
819 | DMA121: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA121) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_572, DMA_ADDR_573, "64'h80",1) | |
820 | DMA122: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA122) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_582, DMA_ADDR_583, "64'h80",1) | |
821 | DMA123: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA123) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_592, DMA_ADDR_593, "64'h80",1) | |
822 | DMA124: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA124) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_602, DMA_ADDR_603, "64'h80",1) | |
823 | DMA125: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA125) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_612, DMA_ADDR_613, "64'h80",1) | |
824 | DMA126: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA126) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_622, DMA_ADDR_623, "64'h80",1) | |
825 | DMA127: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA127) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_632, DMA_ADDR_633, "64'h80",1) | |
826 | ||
827 | ||
828 | ! select a MEM32 address in PCI address range and transmit the command to NCU | |
829 | ||
830 | setx MEM32_WR_ADDR, %g1, %g2 | |
831 | set 5, %g4 ! loop 5 times | |
832 | ||
833 | delay_loop: | |
834 | stx %g2, [%g2] ! MEM32 PIO Write | |
835 | ldx [%g2], %l0 ! MEM32 PIO READ | |
836 | add %g2, 8, %g2 ! increment PIO address | |
837 | ||
838 | dec %g4 ! decrement counter | |
839 | brnz %g4, delay_loop ! loop if not zero | |
840 | nop | |
841 | ||
842 | ||
843 | test_passed: | |
844 | EXIT_GOOD | |
845 | ||
846 | test_failed: | |
847 | EXIT_BAD | |
848 | ||
849 | ||
850 | /************************************************************************ | |
851 | Test case data start. Need to set up known data to check on DMA completions | |
852 | ************************************************************************/ | |
853 | ||
854 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
855 | attr_data { | |
856 | Name = .DATA, | |
857 | hypervisor, | |
858 | compressimage | |
859 | } | |
860 | .data | |
861 | init_mem(0x0101010201030104, 64, 8, +, 0, +, 0x0004000400040004) | |
862 | ||
863 | ||
864 | /************************************************************************ | |
865 | IOMMU TTE start | |
866 | TTE Format: | |
867 | 63: 48 DEV KEY - set to 0 | |
868 | 47: 39 reserved - set to 0 | |
869 | 38: 13 DATA PA - set to VA for VA=RA | |
870 | 12: 7 DATA_SOFT - set to 0 | |
871 | 6: 5 reserved - set to 0 | |
872 | 5: 3 FNM MASK - set to 0 | |
873 | 2: 2 KEY VALID - set to 0 | |
874 | 1: 1 DATA_W - set to 1 | |
875 | 0: 0 DATA_V - set to 1 | |
876 | ************************************************************************/ | |
877 | ||
878 | SECTION .DATA2 DATA_VA=IOMMU_TTE_ADDR | |
879 | attr_data { | |
880 | Name = .DATA2, | |
881 | hypervisor, | |
882 | compressimage | |
883 | } | |
884 | .data | |
885 | .skip 0x3e0000 !!! (0xf800_0000 / 0x2000) * 8 | |
886 | init_mem(0x00000000f8000003, 64, 8, +, 0, +, 0x0000000000002000) | |
887 | ||
888 | /************************************************************************/ |