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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeIommu4VBadTr2.s
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: PCIeIommu4VBadTr2.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
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31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39#define ENABLE_PCIE_MPS_512
40#define MAIN_PAGE_HV_ALSO
41
42#define H_HT0_Interrupt_0x60
43#define My_HT0_Interrupt_0x60 \
44 call iommu_trap_code; \
45 nop; \
46 retry; \
47 nop;
48
49#include "hboot.s"
50#include "peu_defines.h"
51#include "ncu_defines.h"
52
53#define MEM32_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
54
55#define DMA_DATA_ADDR 0x000000000
56
57#define IOMMU_TTE_ADDR 0x008000000
58
59! Bits 6:4 = Page Size: 0=8KB, 1=64KB, 3=4MB, 5=256MB, othere are invalid
60! Bits 3:0 = TSB Table size: 6=64k entries
61
62#define IOTSBDESC_1_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (0 << 4) | 0x2)
63#define IOTSBDESC_2_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (1 << 4) | 0x3)
64#define IOTSBDESC_3_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (2 << 4) | 0x4)
65#define IOTSBDESC_4_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (3 << 4) | 0x5)
66#define IOTSBDESC_5_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (4 << 4) | 0x6)
67#define IOTSBDESC_6_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (5 << 4) | 0x7)
68#define IOTSBDESC_7_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (6 << 4) | 0x8)
69#define IOTSBDESC_8_DATA mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (7 << 4) | 0x9)
70
71
72/************************************************************************
73 Test case code start
74 ************************************************************************/
75.text
76.global main
77
78main:
79 ta T_CHANGE_HPRIV
80 nop
81
82!
83! enable interrupts & provide basic handler (like piu_rupt_enable.s)
84!
85
86no_intr: ! Disable interrupts
87 rdpr %pstate, %g7
88 xor %g7, 0x2, %g7 ! Reset interrupt enable
89 wrpr %g7, %pstate
90
91 ! Initialize NCU's Mondo Interrupt Vector Register
92 ! VECTOR = 63
93
94ncu_mondo_int_vec:
95 set 63, %g1
96 setx MONDO_INT_VEC, %g2, %g3
97 stx %g1, [%g3]
98
99 ! Clear NCU's Mondo Interrupt Busy registers.
100
101ncu_mondo_int_busy:
102 setx MONDO_INT_ABUSY, %g1, %g2
103 stx %g0, [%g2]
104
105 ! Enable IOMMU errors.
106
107mmu_intr_enable_reg_init:
108 setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
109 set 0, %g4
110 dec %g4 ! all 1s
111 stx %g4, [%g2]
112
113 ! Enable IMU errors.
114
115imu_intr_enable_reg_init:
116 setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
117 stx %g4, [%g2]
118
119 ! Initialize Interrupt Mapping register for Mondos 62 and 63
120 ! Valid, thread ID 0, no interrupt controller
121
122dmu_intr_map_reg_init:
123 setx PCI_E_INT_MAP_ADDR, %g1, %g7
124 setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
125 add %g7, %g3, %g7
126 best_set_reg(0x80000040, %g1, %g6) ! valid = 1, thread id = 0
127 stx %g6, [%g7] ! interrupt controller = 1
128
129 add %g7, PCI_E_INT_MAP_STEP, %g7
130 best_set_reg(0x80000080, %g1, %g6) ! valid = 1, thread id = 0
131 stx %g6, [%g7] ! interrupt controller = 2
132
133yes_intr:
134 rdpr %pstate, %g7
135 or %g7, 0x2, %g7 ! Set interrupt enable
136 wrpr %g7, %pstate
137
138 ! Enable IMU, MMU interrupts in the DMU Core and Block
139 ! Interrupt Enable register.
140
141dmu_core_block_enable:
142 setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
143 stx %g4, [%g2]
144
145! enable SUN4U translation in the IOMMU
146
147write_mmu_ctl_reg:
148 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
149 setx 0x00307, %g1, %g3 ! 9:8 11 = Cache enabled,
150 ! 3: 1 = Busid Select, 1 = use busid[5:0] for DEV2IOTSB index
151 ! 2: 1 = SUN4V enabled,
152 ! 1: 1 = bypass enabled,
153 ! 0: 1 = translation enabled
154 stx %g3, [%g2]
155 ldx [%g2], %g3
156
157! setup the DEV2IOTSB - the all busids map to IOTSBDESC ram entry 1
158! (currently it looks like the denali transactor (or vera wrapper) is generating
159! a random busid, so map them all to IOTSB 1.
160
161write_dev2iotsb:
162 setx FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR, %g1, %g2
163 setx 0x0001020304050607, %g1, %g3
164 stx %g3, [%g2 + 0x00]
165 stx %g3, [%g2 + 0x08]
166 stx %g3, [%g2 + 0x10]
167 stx %g3, [%g2 + 0x18]
168 stx %g3, [%g2 + 0x20]
169 stx %g3, [%g2 + 0x28]
170 stx %g3, [%g2 + 0x30]
171 stx %g3, [%g2 + 0x38]
172
173 stx %g3, [%g2 + 0x40]
174 stx %g3, [%g2 + 0x48]
175 stx %g3, [%g2 + 0x50]
176 stx %g3, [%g2 + 0x58]
177 stx %g3, [%g2 + 0x60]
178 stx %g3, [%g2 + 0x68]
179 stx %g3, [%g2 + 0x70]
180 stx %g3, [%g2 + 0x78]
181
182! setup entry 1 of the IOTSBDESC ram
183
184write_iotsbdesc:
185 setx FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR, %g1, %g2
186 setx IOTSBDESC_1_DATA, %g1, %g3
187 setx IOTSBDESC_2_DATA, %g1, %g4
188 setx IOTSBDESC_3_DATA, %g1, %g5
189 setx IOTSBDESC_4_DATA, %g1, %g6
190 stx %g3, [%g2 + 0]
191 stx %g4, [%g2 + 8]
192 stx %g5, [%g2 + 16]
193 stx %g6, [%g2 + 24]
194 setx IOTSBDESC_5_DATA, %g1, %g3
195 setx IOTSBDESC_6_DATA, %g1, %g4
196 setx IOTSBDESC_7_DATA, %g1, %g5
197 setx IOTSBDESC_8_DATA, %g1, %g6
198 stx %g3, [%g2 + 32]
199 stx %g4, [%g2 + 40]
200 stx %g5, [%g2 + 48]
201 stx %g6, [%g2 + 56]
202 ldx [%g2], %g3
203
204! Trigger some DMA Writes which are not bypass addresses, because bits
205! 49:40 are not all 0.
206
207DMAWR1: nop
208! $EV trig_pc_d(1,@VA(.MAIN.DMAWR1)) -> EnablePCIeIgCmd("DMAWR", fffe000000000000, fffe0000ffffffff, "64'h100",1)
209
210DMAWR2: nop
211! $EV trig_pc_d(1,@VA(.MAIN.DMAWR2)) -> EnablePCIeIgCmd("DMAWR", fffd000000000000, fffd0000ffffffff, "64'h100",1)
212
213DMAWR3: nop
214! $EV trig_pc_d(1,@VA(.MAIN.DMAWR3)) -> EnablePCIeIgCmd("DMAWR", fffc800000000000, fffc8000ffffffff, "64'h100",1)
215
216DMAWR4: nop
217! $EV trig_pc_d(1,@VA(.MAIN.DMAWR4)) -> EnablePCIeIgCmd("DMAWR", fffc400000000000, fffc4000ffffffff, "64'h100",1)
218
219DMAWR5: nop
220! $EV trig_pc_d(1,@VA(.MAIN.DMAWR5)) -> EnablePCIeIgCmd("DMAWR", fffc200000000000, fffc2000ffffffff, "64'h100",1)
221
222DMAWR6: nop
223! $EV trig_pc_d(1,@VA(.MAIN.DMAWR6)) -> EnablePCIeIgCmd("DMAWR", fffc100000000000, fffc1000ffffffff, "64'h100",1)
224
225DMAWR7: nop
226! $EV trig_pc_d(1,@VA(.MAIN.DMAWR7)) -> EnablePCIeIgCmd("DMAWR", fffc080000000000, fffc0800ffffffff, "64'h100",1)
227
228DMAWR8: nop
229! $EV trig_pc_d(1,@VA(.MAIN.DMAWR8)) -> EnablePCIeIgCmd("DMAWR", fffc040000000000, fffc0400ffffffff, "64'h100",1)
230
231DMAWR9: nop
232! $EV trig_pc_d(1,@VA(.MAIN.DMAWR9)) -> EnablePCIeIgCmd("DMAWR", fffc020000000000, fffc0200ffffffff, "64'h100",1)
233
234DMAWRa: nop
235! $EV trig_pc_d(1,@VA(.MAIN.DMAWRa)) -> EnablePCIeIgCmd("DMAWR", fffc010000000000, fffc0100ffffffff, "64'h100",1)
236
237
238! Trigger some DMA Reads of various lengths
239
240 setx 0x00001F00, %g1, %g2 ! DMA start address
241 setx 0x00001F00, %g1, %g3 ! page size
242#define DMA_ADDR_01 mpeval(0x0000001F00 + 0,16,16)
243#define DMA_ADDR_02 mpeval(0x0000001F00 + 64,16,16)
244DMA0: nop
245! $EV trig_pc_d(1,@VA(.MAIN.DMA0)) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_01, DMA_ADDR_02, "64'h100",1)
246 !stx %g2, [%g2]
247 ldx [%g2 + 64], %g4
248 ldx [%g2 + 128], %g5
249 ldx [%g2 + 192], %g6
250 add %g2, %g3, %g2
251#define DMA_ADDR_11 mpeval(0x0000002F00 + 0,16,16)
252#define DMA_ADDR_12 mpeval(0x0000002F00 + 64,16,16)
253DMA1: nop
254! $EV trig_pc_d(1,@VA(.MAIN.DMA1)) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_11, DMA_ADDR_12, "64'h100",1)
255 !stx %g2, [%g2]
256 ldx [%g2 + 64], %g4
257 ldx [%g2 + 128], %g5
258 ldx [%g2 + 192], %g6
259 add %g2, %g3, %g2
260#define DMA_ADDR_21 mpeval(0x0000003F00 + 0,16,16)
261#define DMA_ADDR_22 mpeval(0x0000003F00 + 64,16,16)
262
263DMA2: nop
264! $EV trig_pc_d(1,@VA(.MAIN.DMA2)) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_21, DMA_ADDR_22, "64'h100",1)
265 !stx %g2, [%g2]
266 ldx [%g2 + 64], %g4
267 ldx [%g2 + 128], %g5
268 ldx [%g2 + 192], %g6
269 add %g2, %g3, %g2
270#define DMA_ADDR_31 mpeval(0x0000004F00 + 0,16,16)
271#define DMA_ADDR_32 mpeval(0x0000004F00 + 64,16,16)
272
273DMA3: nop
274! $EV trig_pc_d(1,@VA(.MAIN.DMA3)) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_31, DMA_ADDR_32, "64'h100",1)
275 !stx %g2, [%g2]
276 ldx [%g2 + 64], %g4
277 ldx [%g2 + 128], %g5
278 ldx [%g2 + 192], %g6
279 add %g2, %g3, %g2
280#define DMA_ADDR_41 mpeval(0x0000005F00 + 0,16,16)
281#define DMA_ADDR_42 mpeval(0x0000005F00 + 64,16,16)
282
283DMA4: nop
284! $EV trig_pc_d(1,@VA(.MAIN.DMA4)) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_41, DMA_ADDR_42, "64'h100",1)
285 !stx %g2, [%g2]
286 ldx [%g2 + 64], %g4
287 ldx [%g2 + 128], %g5
288 ldx [%g2 + 192], %g6
289 add %g2, %g3, %g2
290#define DMA_ADDR_51 mpeval(0x0000006F00 + 0,16,16)
291#define DMA_ADDR_52 mpeval(0x0000006F00 + 64,16,16)
292
293DMA5: nop
294! $EV trig_pc_d(1,@VA(.MAIN.DMA5)) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_51, DMA_ADDR_52, "64'h100",1)
295 !stx %g2, [%g2]
296 ldx [%g2 + 64], %g4
297 ldx [%g2 + 128], %g5
298 ldx [%g2 + 192], %g6
299 add %g2, %g3, %g2
300
301
302 ! select a MEM32 address in PCI address range and transmit the command to NCU
303
304 setx MEM32_WR_ADDR, %g1, %g2
305 set 5, %g4 ! loop 5 times
306
307delay_loop:
308 stx %g2, [%g2] ! MEM32 PIO Write
309 ldx [%g2], %l0 ! MEM32 PIO READ
310 add %g2, 8, %g2 ! increment PIO address
311
312 dec %g4 ! decrement counter
313 brnz %g4, delay_loop ! loop if not zero
314 nop
315
316
317test_passed:
318 EXIT_GOOD
319
320test_failed:
321 EXIT_BAD
322
323
324/**********************************************************************
325 Interrupt trap handler.
326 **********************************************************************/
327 .align 64
328.global iommu_trap_code
329iommu_trap_code:
330
331 ! read DMU error status registers
332
333 setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %g5 ! 631000
334 ldx [%g5+0x808], %l7 ! 631808 - DMU Core and Block Error Status Reg
335 cmp %l7, 0
336 bz test_failed ! if 0, must be a PEU interrupt
337 nop
338
339 and %l7, 0x2, %l6 ! test if the MMU has an interrupt
340 cmp %l6, 0
341 bnz read_mmu_error_regs
342 nop
343
344read_imu_error_regs:
345 ldx [%g5+0x10], %l3 ! 631010 - IMU Interrupt Status Reg
346 ldx [%g5+0x28], %l4 ! 631028 - IMU RDS Error Log Reg
347 ldx [%g5+0x30], %l5 ! 631030 - IMU SCS Error Log Reg
348 ldx [%g5+0x38], %l6 ! 631038 - IMU EQS Error Log Reg
349 ba test_failed ! No errors expected - go to bad trap
350 nop
351
352read_mmu_error_regs:
353 setx FIRE_DLC_MMU_CSR_A_LOG_ADDR, %g1, %g6 ! 641000
354 ldx [%g6+0x10], %l0 ! 641010 - MMU Interrupt Status Reg
355 stx %l0, [%g6+0x18] ! 641018 - MMU Status Clear Reg
356 ldx [%g6+0x28], %l1 ! 641028 - MMU Translation Fault Address Reg
357 ldx [%g6+0x30], %l2 ! 641030 - MMU Translation Fault Status Reg
358 !ba return_to_test
359 !nop
360
361return_to_test:
362 best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+PCI_E_INT_CLEAR_MONDO_62_OFFSET), %g1, %g6)
363 ldx [%g6], %g1 ! get mondo62 int state
364 stx %g0, [%g6] ! clear mondo 62 int state
365 ldx [%g6+8], %g1 ! get mondo63 int state
366 stx %g0, [%g6+8] ! clear mondo 63 int state
367
368clear_mondo_busy:
369 best_set_reg(MONDO_INT_ABUSY, %g1, %g7)
370 stx %g0, [%g7]
371
372 ldxa [%g0]ASI_SWVR_INTR_R, %l5
373
374 inc %o0
375 jmpl %o7 + 4, %g0
376 nop
377
378/************************************************************************
379 Test case data start.
380************************************************************************/
381
382
383/************************************************************************
384 IOMMU TTE start
385 TTE Format:
38663: 48 DEV KEY - set to 0
38747: 39 reserved - set to 0
38838: 13 DATA PA - set to VA for VA=RA
38912: 7 DATA_SOFT - set to 0
3906: 5 reserved - set to 0
3915: 3 FNM MASK - set to 0
3922: 2 KEY VALID - set to 0
3931: 1 DATA_W - set to 1
3940: 0 DATA_V - set to 1
395************************************************************************/
396
397SECTION .DATA2 DATA_VA=IOMMU_TTE_ADDR
398attr_data {
399 Name = .DATA2,
400 hypervisor,
401 compressimage
402}
403
404.data
405 init_mem(0x0000000000000003, 66, 8, +, 0, +, 0x0000000010000000)
406
407/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.