[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeIommu4VBypTrInv.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeIommu4VBypTrInv.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO

#define ENABLE_INTR0x60 1

#define INTR0x60_MONDO_IV 63

#define INTR0x60_MONDO_20_V 1
#define INTR0x60_MONDO_20_THREAD 0
#define INTR0x60_MONDO_20_CNTRL 0


#define INTR0x60_INTA_EXTRA_HANDLER \
    setx intr_count, %g4, %g3; \
    add  %g3, %g1, %g3; \
    ldub [%g3], %g4; \
    inc  %g4; \
    stb  %g4, [%g3]

#include "interrupt0x60_defines.h"

#include "hboot.s"
#include "peu_defines.h"
#include "ncu_defines.h"

#include "interrupt0x60_handler.s"

#define MEM32_WR_ADDR 		   mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)

#define DMA_DATA_ADDR		   0x00800000

#define IOMMU_TTE_ADDR		   0x40000000

! Bit 8 = Page Size: 0=8KB, 1=64KB;  Bits 3:0 = TSB Table size:	6=64k entries 
!!#define MMU_TSB_CNTRL_REG_DATA	   mpeval(IOMMU_TTE_ADDR | 0x100 | 6)
#define IOTSBDESC_1_DATA	   mpeval((1<<63)|(IOMMU_TTE_ADDR << 21) | (1 << 4) | 0x6)

#define	NCU_IOMMU_INVALIDATE_REG_ADDR	0x8000002030

/************************************************************************
   Test case code start
 ************************************************************************/
SECTION .MAIN
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

th_fork(th_main, %l0)

th_main_0:
! enable interrupts & provide basic handler
!#include "piu_rupt_enable.s"

! enable SUN4V translation in the IOMMU
	
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
	setx	0x00307, %g1, %g3	! 9:8 11 = Cache enabled, 
					! 3: 1 = Busid Select, 1 = use busid[5:0] for DEV2IOTSB index
					! 2: 1 = SUN4V enabled,
					! 1: 1 = bypass enabled, 
					! 0: 1 = translation enabled
	stx	%g3, [%g2]
	ldx	[%g2], %g3
	
! setup the DEV2IOTSB - the all busids map to IOTSBDESC ram entry 1
! (currently it looks like the denali transactor (or vera wrapper) is generating
! a random busid, so map them all to IOTSB 1.
	
write_dev2iotsb:
	setx	FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR, %g1, %g2
	setx    0x0101010101010101,  %g1, %g3
	stx	%g3, [%g2 + 0x00]
	stx	%g3, [%g2 + 0x08]
	stx	%g3, [%g2 + 0x10]
	stx	%g3, [%g2 + 0x18]
	stx	%g3, [%g2 + 0x20]
	stx	%g3, [%g2 + 0x28]
	stx	%g3, [%g2 + 0x30]
	stx	%g3, [%g2 + 0x38]
	stx	%g3, [%g2 + 0x40]
	stx	%g3, [%g2 + 0x48]
	stx	%g3, [%g2 + 0x50]
	stx	%g3, [%g2 + 0x58]
	stx	%g3, [%g2 + 0x60]
	stx	%g3, [%g2 + 0x68]
	stx	%g3, [%g2 + 0x70]
	stx	%g3, [%g2 + 0x78]
	
! setup entry 1 of the IOTSBDESC ram 
	
write_iotsbdesc:
	setx	FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR, %g1, %g2
	setx	IOTSBDESC_1_DATA, %g1, %g3
	stx	%g3, [%g2 + 8]
	ldx	[%g2], %g3

	
! Trigger some DMA Reads that will create IOMMU tlb entries
	
#define DMA_ADDR_1 mpeval(0x00800000,16,16)
DMA1: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA1)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_1, DMA_ADDR_1, "64'h40",1)
#define DMA_ADDR_2 mpeval(0x00810000,16,16)
DMA2: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA2)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_2, DMA_ADDR_2, "64'h40",1)
#define DMA_ADDR_3 mpeval(0x00820000,16,16)
DMA3: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA3)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_3, DMA_ADDR_3, "64'h40",1)
#define DMA_ADDR_4 mpeval(0x00830000,16,16)
DMA4: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA4)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_4, DMA_ADDR_4, "64'h40",1)
#define DMA_ADDR_5 mpeval(0x00840000,16,16)
DMA5: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA5)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_5, DMA_ADDR_5, "64'h40",1)
#define DMA_ADDR_6 mpeval(0x00850000,16,16)
DMA6: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA6)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_6, DMA_ADDR_6, "64'h40",1)
#define DMA_ADDR_7 mpeval(0x00860000,16,16)
DMA7: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA7)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_7, DMA_ADDR_7, "64'h40",1)
	
#define DMA_ADDR_8  mpeval(0x00870000,16,16)
#define DMA_ADDR_8d  mpeval(0x00870000)
DMA8: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA8)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_8, DMA_ADDR_8, "64'h40",1)


INTA_ASSERT_Evnt: nop
! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1 )

intr_wait_1:
    mov	 1, %g4
    setx intr_count, %l1, %g3
    best_set_reg(0x200, %l1, %g2)		! timeout count

intr_wait_loop_top_1:
    ldub  [%g3], %g5
    cmp  %g5, %g4
    be   INTA_DEASSERT_Evnt
    dec  %g2

    cmp  %g2, 0
    bne  intr_wait_loop_top_1
    nop

intr_timeout1:
!$EV trig_pc_d(1, @VA(.MAIN.intr_timeout1)) -> printf("ERROR: Timeout waiting for interrupt 1",*,1)
    EXIT_BAD
	

INTA_DEASSERT_Evnt: nop
! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 1 )

! wait for last DMA to be complete

	setx	DMA_ADDR_8d, %g1, %g2		! DMA tgt address
	ldx	[%g2], %g5			! get the last dma data area
	brnz	%g5, invalidate_the_TTE_in_memory
	nop
	b	test_failed
	nop
	
! now clear the VALID bit of the TTEs in memory

invalidate_the_TTE_in_memory:
	!setx	iommu_tte_addr, %g1, %g2	! TTE address
	
	setx	mpeval(IOMMU_TTE_ADDR+(8*0x80)), %g1, %g2 ! get the TTE address
	
	stb	%g0, [%g2 + 7]			! clear the last byte of the TTE
	add	%g2, 8, %g2			! address of next TTE
	stb	%g0, [%g2 + 7]			! clear the last byte of the TTE
	add	%g2, 8, %g2			! address of next TTE
	stb	%g0, [%g2 + 7]			! clear the last byte of the TTE
	add	%g2, 8, %g2			! address of next TTE
	stb	%g0, [%g2 + 7]			! clear the last byte of the TTE
	add	%g2, 8, %g2			! address of next TTE
	stb	%g0, [%g2 + 7]			! clear the last byte of the TTE
	add	%g2, 8, %g2			! address of next TTE
	stb	%g0, [%g2 + 7]			! clear the last byte of the TTE
	add	%g2, 8, %g2			! address of next TTE
	stb	%g0, [%g2 + 7]			! clear the last byte of the TTE
	add	%g2, 8, %g2			! address of next TTE
	stb	%g0, [%g2 + 7]			! clear the last byte of the TTE
	membar	0x40

! now do some more DMAs using the same TTEs

	
DMA65: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA65) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_1, DMA_ADDR_1, "64'h40",1)
DMA66: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA66) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_2, DMA_ADDR_2, "64'h40",1)
DMA67: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA67) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_3, DMA_ADDR_3, "64'h40",1)
DMA68: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA68) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_4, DMA_ADDR_4, "64'h40",1)
DMA69: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA69) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_5, DMA_ADDR_5, "64'h40",1)
DMA70: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA70) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_6, DMA_ADDR_6, "64'h40",1)
DMA71: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA71) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_7, DMA_ADDR_7, "64'h40",1)
DMA72: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA72) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_8, DMA_ADDR_8, "64'h40",1)

#define DMA_ADDR_9  mpeval(0x00880000,16,16)
#define DMA_ADDR_9d  mpeval(0x00880000)
DMA9: nop
! $EV trig_pc_d(1,@VA(.MAIN.DMA9)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_9, DMA_ADDR_9, "64'h40",1)

INTA_ASSERT_Evnt2: nop
! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1)

intr_wait_2:
    mov	 2, %g4
    setx intr_count, %l1, %g3
    best_set_reg(0x200, %l1, %g2)		! timeout count

intr_wait_loop_top_2:
    ldub  [%g3], %g5
    cmp  %g5, %g4
    be   INTA_DEASSERT_Evnt2
    dec  %g2

    cmp  %g2, 0
    bne  intr_wait_loop_top_2
    nop

intr_timeout2:
    !$EV trig_pc_d(1, @VA(.MAIN.intr_timeout2)) -> printf("ERROR: Timeout waiting for interrupt 2",*,1)
    EXIT_BAD
	
INTA_DEASSERT_Evnt2: nop
! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT",1 )

! wait for last DMA to be complete

	setx	DMA_ADDR_9d, %g1, %g2		! DMA tgt address
	ldx	[%g2], %g5			! get the last dma data area
	brnz	%g5, test_passed
	nop
	b	test_failed
	nop


/************************************************************************
   Threads 1 - 7 will issue the IOMMU INVALIDATES
************************************************************************/
th_main_1:
	setx	th_data_1, %g1, %g2
	b	th_1to7_join
	nop
th_main_2:
	setx	th_data_2, %g1, %g2
	b	th_1to7_join
	nop
th_main_3:
	setx	th_data_3, %g1, %g2
	b	th_1to7_join
	nop
th_main_4:
	setx	th_data_4, %g1, %g2
	b	th_1to7_join
	nop
th_main_5:
	setx	th_data_5, %g1, %g2
	b	th_1to7_join
	nop
th_main_6:
	setx	th_data_6, %g1, %g2
	b	th_1to7_join
	nop
th_main_7:
	setx	th_data_7, %g1, %g2
	b	th_1to7_join
	nop

th_1to7_join:
	set	64, %g3			! loop 64 times
	setx	NCU_IOMMU_INVALIDATE_REG_ADDR, %g1, %g4		! NCU register address

iommu_invalidate_loop:
	ldx	[%g2], %g5		! get an address
	stx	%g5, [%g4]		! issue an IOMMU INALIDATE 
	add	%g2, 8, %g2		! increment data   address
	
	dec	%g3			! decrement counter
	brnz	%g3, iommu_invalidate_loop	! loop if not zero
	nop
	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD
/************************************************************************
   Test case data start
************************************************************************/

.align  1024
.data
user_data_start:
intr_expect:
        .byte   0x1             ! expected interrupt count for thread 0
        .byte   0x0             ! expected interrupt count for thread 1
        .byte   0x1             ! expected interrupt count for thread 2
        .byte   0x0             ! expected interrupt count for thread 3
        .byte   0x1             ! expected interrupt count for thread 4
        .byte   0x0             ! expected interrupt count for thread 5
        .byte   0x1             ! expected interrupt count for thread 6
        .byte   0x0             ! expected interrupt count for thread 7
user_data_end:

/************************************************************************
   Test case INVALIDATE data start.  We don't want any values to match
   the IOMMU_TTE_ADDR being used, which is IOMMU_TTE_ADDR + 0x80
************************************************************************/
	.align 16
th_data_1:	
	init_mem(IOMMU_TTE_ADDR+0x0040, 64, 8, +, 0, +, 0x0004004004004040)
	
th_data_2:	
	init_mem(IOMMU_TTE_ADDR+0x0080, 64, 8, +, 0, +, 0x0000800800808080)
	
th_data_3:	
	init_mem(IOMMU_TTE_ADDR+0x0100, 64, 8, +, 0, +, 0x0000100100101101)
	
th_data_4:	
	init_mem(IOMMU_TTE_ADDR+0x0200, 64, 8, +, 0, +, 0x0002020202020202)
	
th_data_5:	
	init_mem(IOMMU_TTE_ADDR+0x0800, 64, 8, +, 0, +, 0x0004040404040404)
	
th_data_6:	
	init_mem(IOMMU_TTE_ADDR+0x1000, 64, 8, +, 0, +, 0x0008080808080808)
	
th_data_7:	
	init_mem(IOMMU_TTE_ADDR+0x2000, 64, 8, +, 0, +, 0x0001010101001010)
	
	
/************************************************************************
   Test case DMA data start.
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}
.data
	init_mem(0x0101010201030104, 8, 8, +, 0, +, 0x0004000400040004)
.skip 0x10000 - 64
	init_mem(0x0201020202030204, 8, 8, +, 0, +, 0x0004000400040004)
.skip 0x10000 - 64
	init_mem(0x0301030203030304, 8, 8, +, 0, +, 0x0004000400040004)
.skip 0x10000 - 64
	init_mem(0x0401040204030404, 8, 8, +, 0, +, 0x0004000400040004)
.skip 0x10000 - 64
	init_mem(0x0501050205030504, 8, 8, +, 0, +, 0x0004000400040004)
.skip 0x10000 - 64
	init_mem(0x0601060206030604, 8, 8, +, 0, +, 0x0004000400040004)
.skip 0x10000 - 64
	init_mem(0x0701070207030704, 8, 8, +, 0, +, 0x0004000400040004)

.skip 0x10000 - 64
	!! test expects this to be zero until DMA writes it
	init_mem(0x0000000000000000, 8, 8, +, 0, +, 0x0000000000000000)

.skip 0x10000 - 64
	!! test expects this to be zero until DMA writes it
	init_mem(0x0000000000000000, 8, 8, +, 0, +, 0x0000000000000000)


/************************************************************************
   IOMMU TTE start
	TTE Format:
63:	48 DEV KEY	- set to 0
47:	39 reserved	- set to 0
38:	13 DATA PA	- set to VA for VA=RA
12:	7  DATA_SOFT	- set to 0
6:	5  reserved	- set to 0
5:	3  FNM MASK	- set to 0
2:	2  KEY VALID	- set to 0
1:	1  DATA_W	- set to 1
0:	0  DATA_V	- set to 1
************************************************************************/

SECTION       .DATA2 DATA_VA=IOMMU_TTE_ADDR
attr_data {     
      Name = .DATA2,
      hypervisor,
      compressimage
}

.data
	.skip 8*0x80
	
	!!! we only need 8+1 TTEs for this test
iommu_tte_addr:	
	init_mem(0x0000000000800003, 9, 8, +, 0, +, 0x0000000000010000)
	
/************************************************************************/

SECTION .HTRAPS
.data
.global intr_count
intr_count:
        .byte   0x0             ! interrupt count for thread 0
        .byte   0x0             ! interrupt count for thread 1
        .byte   0x0             ! interrupt count for thread 2
        .byte   0x0             ! interrupt count for thread 3
        .byte   0x0             ! interrupt count for thread 4
        .byte   0x0             ! interrupt count for thread 5
        .byte   0x0             ! interrupt count for thread 6
        .byte   0x0             ! interrupt count for thread 7

.end

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeIommu4VBypTrInv.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define ENABLE_INTR0x60 1
	42
	43	#define INTR0x60_MONDO_IV 63
	44
	45	#define INTR0x60_MONDO_20_V 1
	46	#define INTR0x60_MONDO_20_THREAD 0
	47	#define INTR0x60_MONDO_20_CNTRL 0
	48
	49
	50	#define INTR0x60_INTA_EXTRA_HANDLER \
	51	setx intr_count, %g4, %g3; \
	52	add %g3, %g1, %g3; \
	53	ldub [%g3], %g4; \
	54	inc %g4; \
	55	stb %g4, [%g3]
	56
	57	#include "interrupt0x60_defines.h"
	58
	59	#include "hboot.s"
	60	#include "peu_defines.h"
	61	#include "ncu_defines.h"
	62
	63	#include "interrupt0x60_handler.s"
	64
65	#define MEM32_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
66
67	#define DMA_DATA_ADDR 0x00800000
68
69	#define IOMMU_TTE_ADDR 0x40000000
70
71	! Bit 8 = Page Size: 0=8KB, 1=64KB; Bits 3:0 = TSB Table size: 6=64k entries
72	!!#define MMU_TSB_CNTRL_REG_DATA mpeval(IOMMU_TTE_ADDR \| 0x100 \| 6)
73	#define IOTSBDESC_1_DATA mpeval((1<<63)\|(IOMMU_TTE_ADDR << 21) \| (1 << 4) \| 0x6)
74
75	#define NCU_IOMMU_INVALIDATE_REG_ADDR 0x8000002030
76
77	/************************************************************************
78	Test case code start
79	************************************************************************/
80	SECTION .MAIN
81	.text
82	.global main
83
84	main:
85	ta T_CHANGE_HPRIV
86	nop
87
88	th_fork(th_main, %l0)
89
90	th_main_0:
91	! enable interrupts & provide basic handler
92	!#include "piu_rupt_enable.s"
93
94	! enable SUN4V translation in the IOMMU
95
96	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
97	setx 0x00307, %g1, %g3 ! 9:8 11 = Cache enabled,
98	! 3: 1 = Busid Select, 1 = use busid[5:0] for DEV2IOTSB index
99	! 2: 1 = SUN4V enabled,
100	! 1: 1 = bypass enabled,
101	! 0: 1 = translation enabled
102	stx %g3, [%g2]
103	ldx [%g2], %g3
104
105	! setup the DEV2IOTSB - the all busids map to IOTSBDESC ram entry 1
106	! (currently it looks like the denali transactor (or vera wrapper) is generating
107	! a random busid, so map them all to IOTSB 1.
108
109	write_dev2iotsb:
110	setx FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR, %g1, %g2
111	setx 0x0101010101010101, %g1, %g3
112	stx %g3, [%g2 + 0x00]
113	stx %g3, [%g2 + 0x08]
114	stx %g3, [%g2 + 0x10]
115	stx %g3, [%g2 + 0x18]
116	stx %g3, [%g2 + 0x20]
117	stx %g3, [%g2 + 0x28]
118	stx %g3, [%g2 + 0x30]
119	stx %g3, [%g2 + 0x38]
120	stx %g3, [%g2 + 0x40]
121	stx %g3, [%g2 + 0x48]
122	stx %g3, [%g2 + 0x50]
123	stx %g3, [%g2 + 0x58]
124	stx %g3, [%g2 + 0x60]
125	stx %g3, [%g2 + 0x68]
126	stx %g3, [%g2 + 0x70]
127	stx %g3, [%g2 + 0x78]
128
129	! setup entry 1 of the IOTSBDESC ram
130
131	write_iotsbdesc:
132	setx FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR, %g1, %g2
133	setx IOTSBDESC_1_DATA, %g1, %g3
134	stx %g3, [%g2 + 8]
135	ldx [%g2], %g3
136
137
138	! Trigger some DMA Reads that will create IOMMU tlb entries
139
140	#define DMA_ADDR_1 mpeval(0x00800000,16,16)
141	DMA1: nop
142	! $EV trig_pc_d(1,@VA(.MAIN.DMA1)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_1, DMA_ADDR_1, "64'h40",1)
143	#define DMA_ADDR_2 mpeval(0x00810000,16,16)
144	DMA2: nop
145	! $EV trig_pc_d(1,@VA(.MAIN.DMA2)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_2, DMA_ADDR_2, "64'h40",1)
146	#define DMA_ADDR_3 mpeval(0x00820000,16,16)
147	DMA3: nop
148	! $EV trig_pc_d(1,@VA(.MAIN.DMA3)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_3, DMA_ADDR_3, "64'h40",1)
149	#define DMA_ADDR_4 mpeval(0x00830000,16,16)
150	DMA4: nop
151	! $EV trig_pc_d(1,@VA(.MAIN.DMA4)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_4, DMA_ADDR_4, "64'h40",1)
152	#define DMA_ADDR_5 mpeval(0x00840000,16,16)
153	DMA5: nop
154	! $EV trig_pc_d(1,@VA(.MAIN.DMA5)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_5, DMA_ADDR_5, "64'h40",1)
155	#define DMA_ADDR_6 mpeval(0x00850000,16,16)
156	DMA6: nop
157	! $EV trig_pc_d(1,@VA(.MAIN.DMA6)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_6, DMA_ADDR_6, "64'h40",1)
158	#define DMA_ADDR_7 mpeval(0x00860000,16,16)
159	DMA7: nop
160	! $EV trig_pc_d(1,@VA(.MAIN.DMA7)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_7, DMA_ADDR_7, "64'h40",1)
161
162	#define DMA_ADDR_8 mpeval(0x00870000,16,16)
163	#define DMA_ADDR_8d mpeval(0x00870000)
164	DMA8: nop
165	! $EV trig_pc_d(1,@VA(.MAIN.DMA8)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_8, DMA_ADDR_8, "64'h40",1)
166
167
168	INTA_ASSERT_Evnt: nop
169	! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1 )
170
171	intr_wait_1:
172	mov 1, %g4
173	setx intr_count, %l1, %g3
174	best_set_reg(0x200, %l1, %g2) ! timeout count
175
176	intr_wait_loop_top_1:
177	ldub [%g3], %g5
178	cmp %g5, %g4
179	be INTA_DEASSERT_Evnt
180	dec %g2
181
182	cmp %g2, 0
183	bne intr_wait_loop_top_1
184	nop
185
186	intr_timeout1:
187	!$EV trig_pc_d(1, @VA(.MAIN.intr_timeout1)) -> printf("ERROR: Timeout waiting for interrupt 1",*,1)
188	EXIT_BAD
189
190
191	INTA_DEASSERT_Evnt: nop
192	! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 1 )
193
194	! wait for last DMA to be complete
195
196	setx DMA_ADDR_8d, %g1, %g2 ! DMA tgt address
197	ldx [%g2], %g5 ! get the last dma data area
198	brnz %g5, invalidate_the_TTE_in_memory
199	nop
200	b test_failed
201	nop
202
203	! now clear the VALID bit of the TTEs in memory
204
205	invalidate_the_TTE_in_memory:
206	!setx iommu_tte_addr, %g1, %g2 ! TTE address
207
208	setx mpeval(IOMMU_TTE_ADDR+(8*0x80)), %g1, %g2 ! get the TTE address
209
210	stb %g0, [%g2 + 7] ! clear the last byte of the TTE
211	add %g2, 8, %g2 ! address of next TTE
212	stb %g0, [%g2 + 7] ! clear the last byte of the TTE
213	add %g2, 8, %g2 ! address of next TTE
214	stb %g0, [%g2 + 7] ! clear the last byte of the TTE
215	add %g2, 8, %g2 ! address of next TTE
216	stb %g0, [%g2 + 7] ! clear the last byte of the TTE
217	add %g2, 8, %g2 ! address of next TTE
218	stb %g0, [%g2 + 7] ! clear the last byte of the TTE
219	add %g2, 8, %g2 ! address of next TTE
220	stb %g0, [%g2 + 7] ! clear the last byte of the TTE
221	add %g2, 8, %g2 ! address of next TTE
222	stb %g0, [%g2 + 7] ! clear the last byte of the TTE
223	add %g2, 8, %g2 ! address of next TTE
224	stb %g0, [%g2 + 7] ! clear the last byte of the TTE
225	membar 0x40
226
227	! now do some more DMAs using the same TTEs
228
229
230	DMA65: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA65) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_1, DMA_ADDR_1, "64'h40",1)
231	DMA66: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA66) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_2, DMA_ADDR_2, "64'h40",1)
232	DMA67: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA67) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_3, DMA_ADDR_3, "64'h40",1)
233	DMA68: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA68) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_4, DMA_ADDR_4, "64'h40",1)
234	DMA69: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA69) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_5, DMA_ADDR_5, "64'h40",1)
235	DMA70: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA70) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_6, DMA_ADDR_6, "64'h40",1)
236	DMA71: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA71) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_7, DMA_ADDR_7, "64'h40",1)
237	DMA72: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA72) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_8, DMA_ADDR_8, "64'h40",1)
238
239	#define DMA_ADDR_9 mpeval(0x00880000,16,16)
240	#define DMA_ADDR_9d mpeval(0x00880000)
241	DMA9: nop
242	! $EV trig_pc_d(1,@VA(.MAIN.DMA9)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_9, DMA_ADDR_9, "64'h40",1)
243
244	INTA_ASSERT_Evnt2: nop
245	! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1)
246
247	intr_wait_2:
248	mov 2, %g4
249	setx intr_count, %l1, %g3
250	best_set_reg(0x200, %l1, %g2) ! timeout count
251
252	intr_wait_loop_top_2:
253	ldub [%g3], %g5
254	cmp %g5, %g4
255	be INTA_DEASSERT_Evnt2
256	dec %g2
257
258	cmp %g2, 0
259	bne intr_wait_loop_top_2
260	nop
261
262	intr_timeout2:
263	!$EV trig_pc_d(1, @VA(.MAIN.intr_timeout2)) -> printf("ERROR: Timeout waiting for interrupt 2",*,1)
264	EXIT_BAD
265
266	INTA_DEASSERT_Evnt2: nop
267	! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT",1 )
268
269	! wait for last DMA to be complete
270
271	setx DMA_ADDR_9d, %g1, %g2 ! DMA tgt address
272	ldx [%g2], %g5 ! get the last dma data area
273	brnz %g5, test_passed
274	nop
275	b test_failed
276	nop
277
278
279	/************************************************************************
280	Threads 1 - 7 will issue the IOMMU INVALIDATES
281	************************************************************************/
282	th_main_1:
283	setx th_data_1, %g1, %g2
284	b th_1to7_join
285	nop
286	th_main_2:
287	setx th_data_2, %g1, %g2
288	b th_1to7_join
289	nop
290	th_main_3:
291	setx th_data_3, %g1, %g2
292	b th_1to7_join
293	nop
294	th_main_4:
295	setx th_data_4, %g1, %g2
296	b th_1to7_join
297	nop
298	th_main_5:
299	setx th_data_5, %g1, %g2
300	b th_1to7_join
301	nop
302	th_main_6:
303	setx th_data_6, %g1, %g2
304	b th_1to7_join
305	nop
306	th_main_7:
307	setx th_data_7, %g1, %g2
308	b th_1to7_join
309	nop
310
311	th_1to7_join:
312	set 64, %g3 ! loop 64 times
313	setx NCU_IOMMU_INVALIDATE_REG_ADDR, %g1, %g4 ! NCU register address
314
315	iommu_invalidate_loop:
316	ldx [%g2], %g5 ! get an address
317	stx %g5, [%g4] ! issue an IOMMU INALIDATE
318	add %g2, 8, %g2 ! increment data address
319
320	dec %g3 ! decrement counter
321	brnz %g3, iommu_invalidate_loop ! loop if not zero
322	nop
323
324	test_passed:
325	EXIT_GOOD
326
327	test_failed:
328	EXIT_BAD
329	/************************************************************************
330	Test case data start
331	************************************************************************/
332
333	.align 1024
334	.data
335	user_data_start:
336	intr_expect:
337	.byte 0x1 ! expected interrupt count for thread 0
338	.byte 0x0 ! expected interrupt count for thread 1
339	.byte 0x1 ! expected interrupt count for thread 2
340	.byte 0x0 ! expected interrupt count for thread 3
341	.byte 0x1 ! expected interrupt count for thread 4
342	.byte 0x0 ! expected interrupt count for thread 5
343	.byte 0x1 ! expected interrupt count for thread 6
344	.byte 0x0 ! expected interrupt count for thread 7
345	user_data_end:
346
347	/************************************************************************
348	Test case INVALIDATE data start. We don't want any values to match
349	the IOMMU_TTE_ADDR being used, which is IOMMU_TTE_ADDR + 0x80
350	************************************************************************/
351	.align 16
352	th_data_1:
353	init_mem(IOMMU_TTE_ADDR+0x0040, 64, 8, +, 0, +, 0x0004004004004040)
354
355	th_data_2:
356	init_mem(IOMMU_TTE_ADDR+0x0080, 64, 8, +, 0, +, 0x0000800800808080)
357
358	th_data_3:
359	init_mem(IOMMU_TTE_ADDR+0x0100, 64, 8, +, 0, +, 0x0000100100101101)
360
361	th_data_4:
362	init_mem(IOMMU_TTE_ADDR+0x0200, 64, 8, +, 0, +, 0x0002020202020202)
363
364	th_data_5:
365	init_mem(IOMMU_TTE_ADDR+0x0800, 64, 8, +, 0, +, 0x0004040404040404)
366
367	th_data_6:
368	init_mem(IOMMU_TTE_ADDR+0x1000, 64, 8, +, 0, +, 0x0008080808080808)
369
370	th_data_7:
371	init_mem(IOMMU_TTE_ADDR+0x2000, 64, 8, +, 0, +, 0x0001010101001010)
372
373
374
375	/************************************************************************
376	Test case DMA data start.
377	************************************************************************/
378
379	SECTION .DATA DATA_VA=DMA_DATA_ADDR
380	attr_data {
381	Name = .DATA,
382	hypervisor,
383	compressimage
384	}
385	.data
386	init_mem(0x0101010201030104, 8, 8, +, 0, +, 0x0004000400040004)
387	.skip 0x10000 - 64
388	init_mem(0x0201020202030204, 8, 8, +, 0, +, 0x0004000400040004)
389	.skip 0x10000 - 64
390	init_mem(0x0301030203030304, 8, 8, +, 0, +, 0x0004000400040004)
391	.skip 0x10000 - 64
392	init_mem(0x0401040204030404, 8, 8, +, 0, +, 0x0004000400040004)
393	.skip 0x10000 - 64
394	init_mem(0x0501050205030504, 8, 8, +, 0, +, 0x0004000400040004)
395	.skip 0x10000 - 64
396	init_mem(0x0601060206030604, 8, 8, +, 0, +, 0x0004000400040004)
397	.skip 0x10000 - 64
398	init_mem(0x0701070207030704, 8, 8, +, 0, +, 0x0004000400040004)
399
400	.skip 0x10000 - 64
401	!! test expects this to be zero until DMA writes it
402	init_mem(0x0000000000000000, 8, 8, +, 0, +, 0x0000000000000000)
403
404	.skip 0x10000 - 64
405	!! test expects this to be zero until DMA writes it
406	init_mem(0x0000000000000000, 8, 8, +, 0, +, 0x0000000000000000)
407
408
409
410	/************************************************************************
411	IOMMU TTE start
412	TTE Format:
413	63: 48 DEV KEY - set to 0
414	47: 39 reserved - set to 0
415	38: 13 DATA PA - set to VA for VA=RA
416	12: 7 DATA_SOFT - set to 0
417	6: 5 reserved - set to 0
418	5: 3 FNM MASK - set to 0
419	2: 2 KEY VALID - set to 0
420	1: 1 DATA_W - set to 1
421	0: 0 DATA_V - set to 1
422	************************************************************************/
423
424	SECTION .DATA2 DATA_VA=IOMMU_TTE_ADDR
425	attr_data {
426	Name = .DATA2,
427	hypervisor,
428	compressimage
429	}
430
431	.data
432	.skip 8*0x80
433
434	!!! we only need 8+1 TTEs for this test
435	iommu_tte_addr:
436	init_mem(0x0000000000800003, 9, 8, +, 0, +, 0x0000000000010000)
437
438	/************************************************************************/
439
440	SECTION .HTRAPS
441	.data
442	.global intr_count
443	intr_count:
444	.byte 0x0 ! interrupt count for thread 0
445	.byte 0x0 ! interrupt count for thread 1
446	.byte 0x0 ! interrupt count for thread 2
447	.byte 0x0 ! interrupt count for thread 3
448	.byte 0x0 ! interrupt count for thread 4
449	.byte 0x0 ! interrupt count for thread 5
450	.byte 0x0 ! interrupt count for thread 6
451	.byte 0x0 ! interrupt count for thread 7
452
453	.end
454
455	/************************************************************************/