[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeMem32Rd.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeMem32Rd.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING    
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "peu_defines.h"
	
#define MEM_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
		
#ifndef NO_SELF_CHECK
#define BNE_TEST_FAIL  bne	test_failed
#else
#define BNE_TEST_FAIL  nop
#endif
	
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

	! select a MEM address in PCI address range and transmit the command to NCU

	! 1 byte loads, all 16 offsets
	setx	MEM_RD_ADDR, %g1, %g2
byte_os0:	
	nop     ! $EV trig_pc_d(1, @VA(.MAIN.byte_os0)) -> printf("\n byte_os0 \n")
	ldub	[%g2 + 0], %l0
	cmp	%l0, 0x10
	BNE_TEST_FAIL
	nop
byte_os1:
	ldub	[%g2 + 1], %l0
	cmp	%l0, 0x11
	BNE_TEST_FAIL
	nop
byte_os2:
	ldub	[%g2 + 2], %l0
	cmp	%l0, 0x12
	BNE_TEST_FAIL
	nop
byte_os3:
	ldub	[%g2 + 3], %l0
	cmp	%l0, 0x13
	BNE_TEST_FAIL
	nop
byte_os4:
	ldub	[%g2 + 4], %l0
	cmp	%l0, 0x14
	BNE_TEST_FAIL
	nop
byte_os5:
	ldub	[%g2 + 5], %l0
	cmp	%l0, 0x15
	BNE_TEST_FAIL
	nop
byte_os6:
	ldub	[%g2 + 6], %l0
	cmp	%l0, 0x16
	BNE_TEST_FAIL
	nop
byte_os7:
	ldub	[%g2 + 7], %l0
	cmp	%l0, 0x17
	BNE_TEST_FAIL
	nop
byte_os8:
	ldub	[%g2 + 8], %l0
	cmp	%l0, 0x18
	BNE_TEST_FAIL
	nop
byte_os9:
	ldub	[%g2 + 9], %l0
	cmp	%l0, 0x19
	BNE_TEST_FAIL
	nop
byte_os10:
	ldub	[%g2 + 10], %l0
	cmp	%l0, 0x1a
	BNE_TEST_FAIL
	nop
byte_os11:
	ldub	[%g2 + 11], %l0
	cmp	%l0, 0x1b
	BNE_TEST_FAIL
	nop
byte_os12:
	ldub	[%g2 + 12], %l0
	cmp	%l0, 0x1c
	BNE_TEST_FAIL
	nop
byte_os13:
	ldub	[%g2 + 13], %l0
	cmp	%l0, 0x1d
	BNE_TEST_FAIL
	nop
byte_os14:	
	ldub	[%g2 + 14], %l0
	cmp	%l0, 0x1e
	BNE_TEST_FAIL
	nop
byte_os15:	
	ldub	[%g2 + 15], %l0
	cmp	%l0, 0x1f
	BNE_TEST_FAIL
	nop
	
	! load half-word, 8 offsets within 16 bytes

	setx	MEM_RD_ADDR + 16, %g1, %g2
halfwd_os0:	
	nop     ! $EV trig_pc_d(1, @VA(.MAIN.halfwd_os0)) -> printf("\n halfwd_os0 \n")
	lduh	[%g2 + 0], %l0
	setx	0x2021, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os2:	
	lduh	[%g2 + 2], %l0
	setx	0x2223, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os4:	
	lduh	[%g2 + 4], %l0
	setx	0x2425, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os6:	
	lduh	[%g2 + 6], %l0
	setx	0x2627, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os8:
	lduh	[%g2 + 8], %l0
	setx	0x2829, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os10:	
	lduh	[%g2 + 10], %l0
	setx	0x2a2b, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os12:	
	lduh	[%g2 + 12], %l0
	setx	0x2c2d, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os14:	
	lduh	[%g2 + 14], %l0
	setx	0x2e2f, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop

	! Load word, 4 offsets within 16 bytes
	
	setx	MEM_RD_ADDR + 32, %g1, %g2
fullwd_os0:	
	nop     ! $EV trig_pc_d(1, @VA(.MAIN.fullwd_os0)) -> printf("\n fullwd_os0 \n")
	lduw	[%g2 + 0], %l1
	setx	0x30313233, %g1, %g4
	cmp	%l1, %g4
	BNE_TEST_FAIL
	nop
fullwd_os4:	
	lduw	[%g2 + 4], %l1
	setx	0x34353637, %g1, %g4
	cmp	%l1, %g4
	BNE_TEST_FAIL
	nop
fullwd_os8:	
	lduw	[%g2 + 8], %l1
	setx	0x38393a3b, %g1, %g4
	cmp	%l1, %g4
	BNE_TEST_FAIL
	nop
fullwd_os12:	
	lduw	[%g2 + 12], %l1
	setx	0x3c3d3e3f, %g1, %g4
	cmp	%l1, %g4
	BNE_TEST_FAIL
	nop

	! Load dword (8 bytes), 2 offsets within 16 bytes
	
	setx	MEM_RD_ADDR + 48, %g1, %g2
dblwd_os0:	
	nop     ! $EV trig_pc_d(1, @VA(.MAIN.dblwd_os0)) -> printf("\n dblwd_os0 \n")
	ldx	[%g2], %l0
	setx	0x4041424344454647, %g1, %g4
	cmp	%l0, %g4
	BNE_TEST_FAIL
	nop
dblwd_os8:	
	ldx	[%g2 + 8], %l0
	setx	0x48494a4b4c4d4e4f, %g1, %g4
	cmp	%l0, %g4
	BNE_TEST_FAIL
	nop
	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=MEM_RD_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
	
data0:	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
data1:	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
data2:	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
data3:	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
data4:	.xword 0x5051525354555657
	.xword 0x58595a5b5c5d5e5f

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeMem32Rd.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	40	#define MAIN_PAGE_HV_ALSO
	41
	42	#include "hboot.s"
	43	#include "peu_defines.h"
	44
	45	#define MEM_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	46
	47	#ifndef NO_SELF_CHECK
	48	#define BNE_TEST_FAIL bne test_failed
	49	#else
	50	#define BNE_TEST_FAIL nop
	51	#endif
	52
	53	/************************************************************************
	54	Test case code start
	55	************************************************************************/
	56	.text
	57	.global main
	58
	59	main:
	60	ta T_CHANGE_HPRIV
	61	nop
	62
	63	! select a MEM address in PCI address range and transmit the command to NCU
	64
65	! 1 byte loads, all 16 offsets
66	setx MEM_RD_ADDR, %g1, %g2
67	byte_os0:
68	nop ! $EV trig_pc_d(1, @VA(.MAIN.byte_os0)) -> printf("\n byte_os0 \n")
69	ldub [%g2 + 0], %l0
70	cmp %l0, 0x10
71	BNE_TEST_FAIL
72	nop
73	byte_os1:
74	ldub [%g2 + 1], %l0
75	cmp %l0, 0x11
76	BNE_TEST_FAIL
77	nop
78	byte_os2:
79	ldub [%g2 + 2], %l0
80	cmp %l0, 0x12
81	BNE_TEST_FAIL
82	nop
83	byte_os3:
84	ldub [%g2 + 3], %l0
85	cmp %l0, 0x13
86	BNE_TEST_FAIL
87	nop
88	byte_os4:
89	ldub [%g2 + 4], %l0
90	cmp %l0, 0x14
91	BNE_TEST_FAIL
92	nop
93	byte_os5:
94	ldub [%g2 + 5], %l0
95	cmp %l0, 0x15
96	BNE_TEST_FAIL
97	nop
98	byte_os6:
99	ldub [%g2 + 6], %l0
100	cmp %l0, 0x16
101	BNE_TEST_FAIL
102	nop
103	byte_os7:
104	ldub [%g2 + 7], %l0
105	cmp %l0, 0x17
106	BNE_TEST_FAIL
107	nop
108	byte_os8:
109	ldub [%g2 + 8], %l0
110	cmp %l0, 0x18
111	BNE_TEST_FAIL
112	nop
113	byte_os9:
114	ldub [%g2 + 9], %l0
115	cmp %l0, 0x19
116	BNE_TEST_FAIL
117	nop
118	byte_os10:
119	ldub [%g2 + 10], %l0
120	cmp %l0, 0x1a
121	BNE_TEST_FAIL
122	nop
123	byte_os11:
124	ldub [%g2 + 11], %l0
125	cmp %l0, 0x1b
126	BNE_TEST_FAIL
127	nop
128	byte_os12:
129	ldub [%g2 + 12], %l0
130	cmp %l0, 0x1c
131	BNE_TEST_FAIL
132	nop
133	byte_os13:
134	ldub [%g2 + 13], %l0
135	cmp %l0, 0x1d
136	BNE_TEST_FAIL
137	nop
138	byte_os14:
139	ldub [%g2 + 14], %l0
140	cmp %l0, 0x1e
141	BNE_TEST_FAIL
142	nop
143	byte_os15:
144	ldub [%g2 + 15], %l0
145	cmp %l0, 0x1f
146	BNE_TEST_FAIL
147	nop
148
149	! load half-word, 8 offsets within 16 bytes
150
151	setx MEM_RD_ADDR + 16, %g1, %g2
152	halfwd_os0:
153	nop ! $EV trig_pc_d(1, @VA(.MAIN.halfwd_os0)) -> printf("\n halfwd_os0 \n")
154	lduh [%g2 + 0], %l0
155	setx 0x2021, %g1, %g7
156	cmp %l0, %g7
157	BNE_TEST_FAIL
158	nop
159	halfwd_os2:
160	lduh [%g2 + 2], %l0
161	setx 0x2223, %g1, %g7
162	cmp %l0, %g7
163	BNE_TEST_FAIL
164	nop
165	halfwd_os4:
166	lduh [%g2 + 4], %l0
167	setx 0x2425, %g1, %g7
168	cmp %l0, %g7
169	BNE_TEST_FAIL
170	nop
171	halfwd_os6:
172	lduh [%g2 + 6], %l0
173	setx 0x2627, %g1, %g7
174	cmp %l0, %g7
175	BNE_TEST_FAIL
176	nop
177	halfwd_os8:
178	lduh [%g2 + 8], %l0
179	setx 0x2829, %g1, %g7
180	cmp %l0, %g7
181	BNE_TEST_FAIL
182	nop
183	halfwd_os10:
184	lduh [%g2 + 10], %l0
185	setx 0x2a2b, %g1, %g7
186	cmp %l0, %g7
187	BNE_TEST_FAIL
188	nop
189	halfwd_os12:
190	lduh [%g2 + 12], %l0
191	setx 0x2c2d, %g1, %g7
192	cmp %l0, %g7
193	BNE_TEST_FAIL
194	nop
195	halfwd_os14:
196	lduh [%g2 + 14], %l0
197	setx 0x2e2f, %g1, %g7
198	cmp %l0, %g7
199	BNE_TEST_FAIL
200	nop
201
202	! Load word, 4 offsets within 16 bytes
203
204	setx MEM_RD_ADDR + 32, %g1, %g2
205	fullwd_os0:
206	nop ! $EV trig_pc_d(1, @VA(.MAIN.fullwd_os0)) -> printf("\n fullwd_os0 \n")
207	lduw [%g2 + 0], %l1
208	setx 0x30313233, %g1, %g4
209	cmp %l1, %g4
210	BNE_TEST_FAIL
211	nop
212	fullwd_os4:
213	lduw [%g2 + 4], %l1
214	setx 0x34353637, %g1, %g4
215	cmp %l1, %g4
216	BNE_TEST_FAIL
217	nop
218	fullwd_os8:
219	lduw [%g2 + 8], %l1
220	setx 0x38393a3b, %g1, %g4
221	cmp %l1, %g4
222	BNE_TEST_FAIL
223	nop
224	fullwd_os12:
225	lduw [%g2 + 12], %l1
226	setx 0x3c3d3e3f, %g1, %g4
227	cmp %l1, %g4
228	BNE_TEST_FAIL
229	nop
230
231	! Load dword (8 bytes), 2 offsets within 16 bytes
232
233	setx MEM_RD_ADDR + 48, %g1, %g2
234	dblwd_os0:
235	nop ! $EV trig_pc_d(1, @VA(.MAIN.dblwd_os0)) -> printf("\n dblwd_os0 \n")
236	ldx [%g2], %l0
237	setx 0x4041424344454647, %g1, %g4
238	cmp %l0, %g4
239	BNE_TEST_FAIL
240	nop
241	dblwd_os8:
242	ldx [%g2 + 8], %l0
243	setx 0x48494a4b4c4d4e4f, %g1, %g4
244	cmp %l0, %g4
245	BNE_TEST_FAIL
246	nop
247
248	test_passed:
249	EXIT_GOOD
250
251	test_failed:
252	EXIT_BAD
253
254
255	/************************************************************************
256	Test case data start
257	************************************************************************/
258
259	SECTION .DATA DATA_VA=MEM_RD_ADDR
260	attr_data {
261	Name = .DATA,
262	hypervisor,
263	compressimage
264	}
265
266	.data
267	.global PCIAddr9
268
269	data0: .xword 0x1011121314151617
270	.xword 0x18191a1b1c1d1e1f
271	data1: .xword 0x2021222324252627
272	.xword 0x28292a2b2c2d2e2f
273	data2: .xword 0x3031323334353637
274	.xword 0x38393a3b3c3d3e3f
275	data3: .xword 0x4041424344454647
276	.xword 0x48494a4b4c4d4e4f
277	data4: .xword 0x5051525354555657
278	.xword 0x58595a5b5c5d5e5f
279
280	/************************************************************************/