[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeMem64Rd.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeMem64Rd.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define PCIE_MEM64_OFFSET	0xc800000000

#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "peu_defines.h"

! the default MEM64 OFFSET is 100000000. It is ORed with the base in the data section stmt
#define MEM64_BASE  mpeval(N2_PCIE_BASE_ADDR + MEM64_OFFSET_BASE_REG_DATA)

! a set of defines for which set each of the bits 39:32
#define MEM64_RD_ADR01 mpeval(MEM64_BASE | 0x0100000000 + 0x00)
#define MEM64_RD_ADR02 mpeval(MEM64_BASE | 0x0200000000 + 0x20)
#define MEM64_RD_ADR04 mpeval(MEM64_BASE | 0x0400000000 + 0x40)
#define MEM64_RD_ADR00 mpeval(MEM64_BASE | 0x0000000000 + 0x60)
		
#ifndef NO_SELF_CHECK
#define BNE_TEST_FAIL  bne	test_failed
#else
#define BNE_TEST_FAIL  nop
#endif
		
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

	! select a MEM address in PCI address range and transmit the command to NCU

	! 1 byte loads, all 16 offsets
	setx	MEM64_RD_ADR01, %g1, %g2
byte_os0:	
	nop     ! $EV trig_pc_d(1, @VA(.MAIN.byte_os0)) -> printf("\n byte_os0 \n")
	ldub	[%g2 + 0], %l0
	cmp	%l0, 0x10
	BNE_TEST_FAIL
	nop
byte_os1:
	ldub	[%g2 + 1], %l0
	cmp	%l0, 0x11
	BNE_TEST_FAIL
	nop
byte_os2:
	ldub	[%g2 + 2], %l0
	cmp	%l0, 0x12
	BNE_TEST_FAIL
	nop
byte_os3:
	ldub	[%g2 + 3], %l0
	cmp	%l0, 0x13
	BNE_TEST_FAIL
	nop
byte_os4:
	ldub	[%g2 + 4], %l0
	cmp	%l0, 0x14
	BNE_TEST_FAIL
	nop
byte_os5:
	ldub	[%g2 + 5], %l0
	cmp	%l0, 0x15
	BNE_TEST_FAIL
	nop
byte_os6:
	ldub	[%g2 + 6], %l0
	cmp	%l0, 0x16
	BNE_TEST_FAIL
	nop
byte_os7:
	ldub	[%g2 + 7], %l0
	cmp	%l0, 0x17
	BNE_TEST_FAIL
	nop
byte_os8:
	ldub	[%g2 + 8], %l0
	cmp	%l0, 0x18
	BNE_TEST_FAIL
	nop
byte_os9:
	ldub	[%g2 + 9], %l0
	cmp	%l0, 0x19
	BNE_TEST_FAIL
	nop
byte_os10:
	ldub	[%g2 + 10], %l0
	cmp	%l0, 0x1a
	BNE_TEST_FAIL
	nop
byte_os11:
	ldub	[%g2 + 11], %l0
	cmp	%l0, 0x1b
	BNE_TEST_FAIL
	nop
byte_os12:
	ldub	[%g2 + 12], %l0
	cmp	%l0, 0x1c
	BNE_TEST_FAIL
	nop
byte_os13:
	ldub	[%g2 + 13], %l0
	cmp	%l0, 0x1d
	BNE_TEST_FAIL
	nop
byte_os14:	
	ldub	[%g2 + 14], %l0
	cmp	%l0, 0x1e
	BNE_TEST_FAIL
	nop
byte_os15:	
	ldub	[%g2 + 15], %l0
	cmp	%l0, 0x1f
	BNE_TEST_FAIL
	nop
	
	! load half-word, 8 offsets within 16 bytes

	setx	MEM64_RD_ADR02, %g1, %g2
halfwd_os0:	
	nop     ! $EV trig_pc_d(1, @VA(.MAIN.halfwd_os0)) -> printf("\n halfwd_os0 \n")
	lduh	[%g2 + 0], %l0
	setx	0x2021, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os2:	
	lduh	[%g2 + 2], %l0
	setx	0x2223, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os4:	
	lduh	[%g2 + 4], %l0
	setx	0x2425, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os6:	
	lduh	[%g2 + 6], %l0
	setx	0x2627, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os8:
	lduh	[%g2 + 8], %l0
	setx	0x2829, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os10:	
	lduh	[%g2 + 10], %l0
	setx	0x2a2b, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os12:	
	lduh	[%g2 + 12], %l0
	setx	0x2c2d, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop
halfwd_os14:	
	lduh	[%g2 + 14], %l0
	setx	0x2e2f, %g1, %g7
	cmp	%l0, %g7
	BNE_TEST_FAIL
	nop

	! Load word, 4 offsets within 16 bytes
	
	setx	MEM64_RD_ADR04, %g1, %g2
fullwd_os0:	
	nop     ! $EV trig_pc_d(1, @VA(.MAIN.fullwd_os0)) -> printf("\n fullwd_os0 \n")
	lduw	[%g2 + 0], %l1
	setx	0x40414243, %g1, %g4
	cmp	%l1, %g4
	BNE_TEST_FAIL
	nop
fullwd_os4:	
	lduw	[%g2 + 4], %l1
	setx	0x44454647, %g1, %g4
	cmp	%l1, %g4
	BNE_TEST_FAIL
	nop
fullwd_os8:	
	lduw	[%g2 + 8], %l1
	setx	0x48494a4b, %g1, %g4
	cmp	%l1, %g4
	BNE_TEST_FAIL
	nop
fullwd_os12:	
	lduw	[%g2 + 12], %l1
	setx	0x4c4d4e4f, %g1, %g4
	cmp	%l1, %g4
	BNE_TEST_FAIL
	nop

	! Load dword (8 bytes), 2 offsets within 16 bytes
	
	setx	MEM64_RD_ADR00, %g1, %g2
dblwd_os0:	
	nop     ! $EV trig_pc_d(1, @VA(.MAIN.dblwd_os0)) -> printf("\n dblwd_os0 \n")
	ldx	[%g2], %l0
	setx	0x5051525354555657, %g1, %g4
	cmp	%l0, %g4
	BNE_TEST_FAIL
	nop
dblwd_os8:	
	ldx	[%g2 + 8], %l0
	setx	0x58595a5b5c5d5e5f, %g1, %g5
	cmp	%l0, %g5
	BNE_TEST_FAIL
	nop
  
	ldx	[%g2 + 16], %l0
	cmp	%l0, %g4
	BNE_TEST_FAIL
	nop
  
	ldx	[%g2 + 24], %l0
	cmp	%l0, %g5
	BNE_TEST_FAIL
	nop
  
	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
	DATA0 - DATA3 are expected pio fetch areas
	DATAa - DATAc are for diagnosing incorrect pio fetches
************************************************************************/

SECTION       .DATAa DATA_VA=0xC000000000
attr_data {     
      Name = .DATAa,
      hypervisor,
      compressimage
}
.data
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0
	.xword 0xc0c0c0c0c0c0c0c0

SECTION       .DATAb DATA_VA=0xC100000000
attr_data {     
      Name = .DATAb,
      hypervisor,
      compressimage
}
.data
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1
	.xword 0xc1c1c1c1c1c1c1c1

SECTION       .DATAc DATA_VA=0x0100000000
attr_data {     
      Name = .DATAc,
      hypervisor,
      compressimage
}
.data
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101

SECTION       .DATA0 DATA_VA=mpeval(MEM64_RD_ADR01 | PCIE_MEM64_OFFSET)
attr_data {     
      Name = .DATA0,
      hypervisor,
      compressimage
}
.data
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f

SECTION       .DATA1 DATA_VA=mpeval(MEM64_RD_ADR02 | PCIE_MEM64_OFFSET)
attr_data {     
      Name = .DATA1,
      hypervisor,
      compressimage
}
.data
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f

SECTION       .DATA2 DATA_VA=mpeval(MEM64_RD_ADR04 | PCIE_MEM64_OFFSET)
attr_data {     
      Name = .DATA2,
      hypervisor,
      compressimage
}
.data
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f

SECTION       .DATA3 DATA_VA=mpeval(MEM64_RD_ADR00 | PCIE_MEM64_OFFSET)
attr_data {     
      Name = .DATA3,
      hypervisor,
      compressimage
}
.data
	.xword 0x5051525354555657
	.xword 0x58595a5b5c5d5e5f
	.xword 0x5051525354555657
	.xword 0x58595a5b5c5d5e5f

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeMem64Rd.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define PCIE_MEM64_OFFSET 0xc800000000
	39
	40	#define ENABLE_PCIE_LINK_TRAINING
	41	#define MAIN_PAGE_HV_ALSO
	42
	43	#include "hboot.s"
	44	#include "peu_defines.h"
	45
	46	! the default MEM64 OFFSET is 100000000. It is ORed with the base in the data section stmt
	47	#define MEM64_BASE mpeval(N2_PCIE_BASE_ADDR + MEM64_OFFSET_BASE_REG_DATA)
	48
	49	! a set of defines for which set each of the bits 39:32
	50	#define MEM64_RD_ADR01 mpeval(MEM64_BASE \| 0x0100000000 + 0x00)
	51	#define MEM64_RD_ADR02 mpeval(MEM64_BASE \| 0x0200000000 + 0x20)
	52	#define MEM64_RD_ADR04 mpeval(MEM64_BASE \| 0x0400000000 + 0x40)
	53	#define MEM64_RD_ADR00 mpeval(MEM64_BASE \| 0x0000000000 + 0x60)
	54
	55	#ifndef NO_SELF_CHECK
	56	#define BNE_TEST_FAIL bne test_failed
	57	#else
	58	#define BNE_TEST_FAIL nop
	59	#endif
	60
	61	/************************************************************************
	62	Test case code start
	63	************************************************************************/
	64	.text
65	.global main
66
67	main:
68	ta T_CHANGE_HPRIV
69	nop
70
71	! select a MEM address in PCI address range and transmit the command to NCU
72
73	! 1 byte loads, all 16 offsets
74	setx MEM64_RD_ADR01, %g1, %g2
75	byte_os0:
76	nop ! $EV trig_pc_d(1, @VA(.MAIN.byte_os0)) -> printf("\n byte_os0 \n")
77	ldub [%g2 + 0], %l0
78	cmp %l0, 0x10
79	BNE_TEST_FAIL
80	nop
81	byte_os1:
82	ldub [%g2 + 1], %l0
83	cmp %l0, 0x11
84	BNE_TEST_FAIL
85	nop
86	byte_os2:
87	ldub [%g2 + 2], %l0
88	cmp %l0, 0x12
89	BNE_TEST_FAIL
90	nop
91	byte_os3:
92	ldub [%g2 + 3], %l0
93	cmp %l0, 0x13
94	BNE_TEST_FAIL
95	nop
96	byte_os4:
97	ldub [%g2 + 4], %l0
98	cmp %l0, 0x14
99	BNE_TEST_FAIL
100	nop
101	byte_os5:
102	ldub [%g2 + 5], %l0
103	cmp %l0, 0x15
104	BNE_TEST_FAIL
105	nop
106	byte_os6:
107	ldub [%g2 + 6], %l0
108	cmp %l0, 0x16
109	BNE_TEST_FAIL
110	nop
111	byte_os7:
112	ldub [%g2 + 7], %l0
113	cmp %l0, 0x17
114	BNE_TEST_FAIL
115	nop
116	byte_os8:
117	ldub [%g2 + 8], %l0
118	cmp %l0, 0x18
119	BNE_TEST_FAIL
120	nop
121	byte_os9:
122	ldub [%g2 + 9], %l0
123	cmp %l0, 0x19
124	BNE_TEST_FAIL
125	nop
126	byte_os10:
127	ldub [%g2 + 10], %l0
128	cmp %l0, 0x1a
129	BNE_TEST_FAIL
130	nop
131	byte_os11:
132	ldub [%g2 + 11], %l0
133	cmp %l0, 0x1b
134	BNE_TEST_FAIL
135	nop
136	byte_os12:
137	ldub [%g2 + 12], %l0
138	cmp %l0, 0x1c
139	BNE_TEST_FAIL
140	nop
141	byte_os13:
142	ldub [%g2 + 13], %l0
143	cmp %l0, 0x1d
144	BNE_TEST_FAIL
145	nop
146	byte_os14:
147	ldub [%g2 + 14], %l0
148	cmp %l0, 0x1e
149	BNE_TEST_FAIL
150	nop
151	byte_os15:
152	ldub [%g2 + 15], %l0
153	cmp %l0, 0x1f
154	BNE_TEST_FAIL
155	nop
156
157	! load half-word, 8 offsets within 16 bytes
158
159	setx MEM64_RD_ADR02, %g1, %g2
160	halfwd_os0:
161	nop ! $EV trig_pc_d(1, @VA(.MAIN.halfwd_os0)) -> printf("\n halfwd_os0 \n")
162	lduh [%g2 + 0], %l0
163	setx 0x2021, %g1, %g7
164	cmp %l0, %g7
165	BNE_TEST_FAIL
166	nop
167	halfwd_os2:
168	lduh [%g2 + 2], %l0
169	setx 0x2223, %g1, %g7
170	cmp %l0, %g7
171	BNE_TEST_FAIL
172	nop
173	halfwd_os4:
174	lduh [%g2 + 4], %l0
175	setx 0x2425, %g1, %g7
176	cmp %l0, %g7
177	BNE_TEST_FAIL
178	nop
179	halfwd_os6:
180	lduh [%g2 + 6], %l0
181	setx 0x2627, %g1, %g7
182	cmp %l0, %g7
183	BNE_TEST_FAIL
184	nop
185	halfwd_os8:
186	lduh [%g2 + 8], %l0
187	setx 0x2829, %g1, %g7
188	cmp %l0, %g7
189	BNE_TEST_FAIL
190	nop
191	halfwd_os10:
192	lduh [%g2 + 10], %l0
193	setx 0x2a2b, %g1, %g7
194	cmp %l0, %g7
195	BNE_TEST_FAIL
196	nop
197	halfwd_os12:
198	lduh [%g2 + 12], %l0
199	setx 0x2c2d, %g1, %g7
200	cmp %l0, %g7
201	BNE_TEST_FAIL
202	nop
203	halfwd_os14:
204	lduh [%g2 + 14], %l0
205	setx 0x2e2f, %g1, %g7
206	cmp %l0, %g7
207	BNE_TEST_FAIL
208	nop
209
210	! Load word, 4 offsets within 16 bytes
211
212	setx MEM64_RD_ADR04, %g1, %g2
213	fullwd_os0:
214	nop ! $EV trig_pc_d(1, @VA(.MAIN.fullwd_os0)) -> printf("\n fullwd_os0 \n")
215	lduw [%g2 + 0], %l1
216	setx 0x40414243, %g1, %g4
217	cmp %l1, %g4
218	BNE_TEST_FAIL
219	nop
220	fullwd_os4:
221	lduw [%g2 + 4], %l1
222	setx 0x44454647, %g1, %g4
223	cmp %l1, %g4
224	BNE_TEST_FAIL
225	nop
226	fullwd_os8:
227	lduw [%g2 + 8], %l1
228	setx 0x48494a4b, %g1, %g4
229	cmp %l1, %g4
230	BNE_TEST_FAIL
231	nop
232	fullwd_os12:
233	lduw [%g2 + 12], %l1
234	setx 0x4c4d4e4f, %g1, %g4
235	cmp %l1, %g4
236	BNE_TEST_FAIL
237	nop
238
239	! Load dword (8 bytes), 2 offsets within 16 bytes
240
241	setx MEM64_RD_ADR00, %g1, %g2
242	dblwd_os0:
243	nop ! $EV trig_pc_d(1, @VA(.MAIN.dblwd_os0)) -> printf("\n dblwd_os0 \n")
244	ldx [%g2], %l0
245	setx 0x5051525354555657, %g1, %g4
246	cmp %l0, %g4
247	BNE_TEST_FAIL
248	nop
249	dblwd_os8:
250	ldx [%g2 + 8], %l0
251	setx 0x58595a5b5c5d5e5f, %g1, %g5
252	cmp %l0, %g5
253	BNE_TEST_FAIL
254	nop
255
256	ldx [%g2 + 16], %l0
257	cmp %l0, %g4
258	BNE_TEST_FAIL
259	nop
260
261	ldx [%g2 + 24], %l0
262	cmp %l0, %g5
263	BNE_TEST_FAIL
264	nop
265
266
267	test_passed:
268	EXIT_GOOD
269
270	test_failed:
271	EXIT_BAD
272
273
274	/************************************************************************
275	Test case data start
276	DATA0 - DATA3 are expected pio fetch areas
277	DATAa - DATAc are for diagnosing incorrect pio fetches
278	************************************************************************/
279
280	SECTION .DATAa DATA_VA=0xC000000000
281	attr_data {
282	Name = .DATAa,
283	hypervisor,
284	compressimage
285	}
286	.data
287	.xword 0xc0c0c0c0c0c0c0c0
288	.xword 0xc0c0c0c0c0c0c0c0
289	.xword 0xc0c0c0c0c0c0c0c0
290	.xword 0xc0c0c0c0c0c0c0c0
291	.xword 0xc0c0c0c0c0c0c0c0
292	.xword 0xc0c0c0c0c0c0c0c0
293	.xword 0xc0c0c0c0c0c0c0c0
294	.xword 0xc0c0c0c0c0c0c0c0
295	.xword 0xc0c0c0c0c0c0c0c0
296	.xword 0xc0c0c0c0c0c0c0c0
297	.xword 0xc0c0c0c0c0c0c0c0
298	.xword 0xc0c0c0c0c0c0c0c0
299	.xword 0xc0c0c0c0c0c0c0c0
300	.xword 0xc0c0c0c0c0c0c0c0
301	.xword 0xc0c0c0c0c0c0c0c0
302	.xword 0xc0c0c0c0c0c0c0c0
303	.xword 0xc0c0c0c0c0c0c0c0
304	.xword 0xc0c0c0c0c0c0c0c0
305	.xword 0xc0c0c0c0c0c0c0c0
306	.xword 0xc0c0c0c0c0c0c0c0
307	.xword 0xc0c0c0c0c0c0c0c0
308	.xword 0xc0c0c0c0c0c0c0c0
309	.xword 0xc0c0c0c0c0c0c0c0
310	.xword 0xc0c0c0c0c0c0c0c0
311	.xword 0xc0c0c0c0c0c0c0c0
312	.xword 0xc0c0c0c0c0c0c0c0
313	.xword 0xc0c0c0c0c0c0c0c0
314	.xword 0xc0c0c0c0c0c0c0c0
315	.xword 0xc0c0c0c0c0c0c0c0
316	.xword 0xc0c0c0c0c0c0c0c0
317	.xword 0xc0c0c0c0c0c0c0c0
318	.xword 0xc0c0c0c0c0c0c0c0
319
320	SECTION .DATAb DATA_VA=0xC100000000
321	attr_data {
322	Name = .DATAb,
323	hypervisor,
324	compressimage
325	}
326	.data
327	.xword 0xc1c1c1c1c1c1c1c1
328	.xword 0xc1c1c1c1c1c1c1c1
329	.xword 0xc1c1c1c1c1c1c1c1
330	.xword 0xc1c1c1c1c1c1c1c1
331	.xword 0xc1c1c1c1c1c1c1c1
332	.xword 0xc1c1c1c1c1c1c1c1
333	.xword 0xc1c1c1c1c1c1c1c1
334	.xword 0xc1c1c1c1c1c1c1c1
335	.xword 0xc1c1c1c1c1c1c1c1
336	.xword 0xc1c1c1c1c1c1c1c1
337	.xword 0xc1c1c1c1c1c1c1c1
338	.xword 0xc1c1c1c1c1c1c1c1
339	.xword 0xc1c1c1c1c1c1c1c1
340	.xword 0xc1c1c1c1c1c1c1c1
341	.xword 0xc1c1c1c1c1c1c1c1
342	.xword 0xc1c1c1c1c1c1c1c1
343	.xword 0xc1c1c1c1c1c1c1c1
344	.xword 0xc1c1c1c1c1c1c1c1
345	.xword 0xc1c1c1c1c1c1c1c1
346	.xword 0xc1c1c1c1c1c1c1c1
347	.xword 0xc1c1c1c1c1c1c1c1
348	.xword 0xc1c1c1c1c1c1c1c1
349	.xword 0xc1c1c1c1c1c1c1c1
350	.xword 0xc1c1c1c1c1c1c1c1
351	.xword 0xc1c1c1c1c1c1c1c1
352	.xword 0xc1c1c1c1c1c1c1c1
353	.xword 0xc1c1c1c1c1c1c1c1
354	.xword 0xc1c1c1c1c1c1c1c1
355	.xword 0xc1c1c1c1c1c1c1c1
356	.xword 0xc1c1c1c1c1c1c1c1
357	.xword 0xc1c1c1c1c1c1c1c1
358	.xword 0xc1c1c1c1c1c1c1c1
359
360	SECTION .DATAc DATA_VA=0x0100000000
361	attr_data {
362	Name = .DATAc,
363	hypervisor,
364	compressimage
365	}
366	.data
367	.xword 0x0101010101010101
368	.xword 0x0101010101010101
369	.xword 0x0101010101010101
370	.xword 0x0101010101010101
371	.xword 0x0101010101010101
372	.xword 0x0101010101010101
373	.xword 0x0101010101010101
374	.xword 0x0101010101010101
375	.xword 0x0101010101010101
376	.xword 0x0101010101010101
377	.xword 0x0101010101010101
378	.xword 0x0101010101010101
379	.xword 0x0101010101010101
380	.xword 0x0101010101010101
381	.xword 0x0101010101010101
382	.xword 0x0101010101010101
383	.xword 0x0101010101010101
384	.xword 0x0101010101010101
385	.xword 0x0101010101010101
386	.xword 0x0101010101010101
387	.xword 0x0101010101010101
388	.xword 0x0101010101010101
389	.xword 0x0101010101010101
390	.xword 0x0101010101010101
391	.xword 0x0101010101010101
392	.xword 0x0101010101010101
393	.xword 0x0101010101010101
394	.xword 0x0101010101010101
395	.xword 0x0101010101010101
396	.xword 0x0101010101010101
397	.xword 0x0101010101010101
398	.xword 0x0101010101010101
399
400	SECTION .DATA0 DATA_VA=mpeval(MEM64_RD_ADR01 \| PCIE_MEM64_OFFSET)
401	attr_data {
402	Name = .DATA0,
403	hypervisor,
404	compressimage
405	}
406	.data
407	.xword 0x1011121314151617
408	.xword 0x18191a1b1c1d1e1f
409	.xword 0x1011121314151617
410	.xword 0x18191a1b1c1d1e1f
411
412	SECTION .DATA1 DATA_VA=mpeval(MEM64_RD_ADR02 \| PCIE_MEM64_OFFSET)
413	attr_data {
414	Name = .DATA1,
415	hypervisor,
416	compressimage
417	}
418	.data
419	.xword 0x2021222324252627
420	.xword 0x28292a2b2c2d2e2f
421	.xword 0x2021222324252627
422	.xword 0x28292a2b2c2d2e2f
423
424	SECTION .DATA2 DATA_VA=mpeval(MEM64_RD_ADR04 \| PCIE_MEM64_OFFSET)
425	attr_data {
426	Name = .DATA2,
427	hypervisor,
428	compressimage
429	}
430	.data
431	.xword 0x4041424344454647
432	.xword 0x48494a4b4c4d4e4f
433	.xword 0x4041424344454647
434	.xword 0x48494a4b4c4d4e4f
435
436	SECTION .DATA3 DATA_VA=mpeval(MEM64_RD_ADR00 \| PCIE_MEM64_OFFSET)
437	attr_data {
438	Name = .DATA3,
439	hypervisor,
440	compressimage
441	}
442	.data
443	.xword 0x5051525354555657
444	.xword 0x58595a5b5c5d5e5f
445	.xword 0x5051525354555657
446	.xword 0x58595a5b5c5d5e5f
447
448	/************************************************************************/