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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: PCIeMem64Rd32.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
40 | #define MAIN_PAGE_HV_ALSO | |
41 | ||
42 | #include "hboot.s" | |
43 | #include "peu_defines.h" | |
44 | ||
45 | #define MEM64_BASE mpeval(N2_PCIE_BASE_ADDR + (MEM64_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) | |
46 | ||
47 | #define MEM64_RD_ADDR0 MEM64_BASE | |
48 | !!#define MEM64_RD_ADDR0 mpeval(MEM64_BASE + 0x0000000000000000) | |
49 | !!#define MEM64_RD_ADDR1 mpeval(MEM64_BASE + 0x0000000100000000) | |
50 | !!#define MEM64_RD_ADDR2 mpeval(MEM64_BASE + 0x0000000200000000) | |
51 | !!#define MEM64_RD_ADDR4 mpeval(MEM64_BASE + 0x0000000400000000) | |
52 | ||
53 | !! Keep bit 39 set so that the data section gets read into gMem by vera | |
54 | ||
55 | #define MEM64_OFFSET 0xaabbcc8000000000 | |
56 | !!#define MEM64_OFFSET_PLUS_GARBAGE mpeval(MEM64_OFFSET + 0x0000000000112233, 16, 16) | |
57 | #define MEM64_OFFSET_PLUS_GARBAGE 0xaabbcc8000112233 | |
58 | ||
59 | !!#define MEM64_RD_ADDR0_PLUS_OFFSET mpeval(MEM64_OFFSET | MEM64_RD_ADDR0, 16, 16) | |
60 | #define MEM64_RD_ADDR0_PLUS_OFFSET 0xaabbcc8000000000 | |
61 | ||
62 | #ifndef NO_SELF_CHECK | |
63 | #define BNE_TEST_FAIL bne test_failed | |
64 | #else | |
65 | #define BNE_TEST_FAIL nop | |
66 | #endif | |
67 | ||
68 | /************************************************************************ | |
69 | Test case code start | |
70 | ************************************************************************/ | |
71 | .text | |
72 | .global main | |
73 | ||
74 | main: | |
75 | ta T_CHANGE_HPRIV | |
76 | nop | |
77 | ||
78 | ! Load the PCIE MEM64 OFFSET Register | |
79 | ||
80 | setx FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR, %g1, %g2 | |
81 | setx MEM64_OFFSET_PLUS_GARBAGE, %g1, %g3 | |
82 | stx %g3, [%g2] | |
83 | ldx [%g2], %g4 | |
84 | ||
85 | ! select a MEM address in PCI address range and | |
86 | ! set up the data area using stores, because Midas does not seem to | |
87 | ! allow a .data section to be set up with an address > 2**39 | |
88 | ||
89 | setx MEM64_RD_ADDR0, %g1, %g2 | |
90 | setx 0x1011121314151617, %g1, %g3 | |
91 | stx %g3,[%g2 + 0] | |
92 | setx 0x18191a1b1c1d1e1f, %g1, %g3 | |
93 | stx %g3,[%g2 + 8] | |
94 | setx 0x2021222324252627, %g1, %g3 | |
95 | stx %g3,[%g2 + 16] | |
96 | setx 0x28292a2b2c2d2e2f, %g1, %g3 | |
97 | stx %g3,[%g2 + 24] | |
98 | setx 0x3031323334353637, %g1, %g3 | |
99 | stx %g3,[%g2 + 32] | |
100 | setx 0x38393a3b3c3d3e3f, %g1, %g3 | |
101 | stx %g3,[%g2 + 40] | |
102 | setx 0x4041424344454647, %g1, %g3 | |
103 | stx %g3,[%g2 + 48] | |
104 | setx 0x48494a4b4c4d4e4f, %g1, %g3 | |
105 | stx %g3,[%g2 + 56] | |
106 | ||
107 | ! 1 byte loads, all 16 offsets | |
108 | ||
109 | byte_os0: | |
110 | nop ! $EV trig_pc_d(1, @VA(.MAIN.byte_os0)) -> printf("\n byte_os0 \n") | |
111 | ldub [%g2 + 0], %l0 | |
112 | cmp %l0, 0x10 | |
113 | BNE_TEST_FAIL | |
114 | nop | |
115 | byte_os1: | |
116 | ldub [%g2 + 1], %l0 | |
117 | cmp %l0, 0x11 | |
118 | BNE_TEST_FAIL | |
119 | nop | |
120 | byte_os2: | |
121 | ldub [%g2 + 2], %l0 | |
122 | cmp %l0, 0x12 | |
123 | BNE_TEST_FAIL | |
124 | nop | |
125 | byte_os3: | |
126 | ldub [%g2 + 3], %l0 | |
127 | cmp %l0, 0x13 | |
128 | BNE_TEST_FAIL | |
129 | nop | |
130 | byte_os4: | |
131 | ldub [%g2 + 4], %l0 | |
132 | cmp %l0, 0x14 | |
133 | BNE_TEST_FAIL | |
134 | nop | |
135 | byte_os5: | |
136 | ldub [%g2 + 5], %l0 | |
137 | cmp %l0, 0x15 | |
138 | BNE_TEST_FAIL | |
139 | nop | |
140 | byte_os6: | |
141 | ldub [%g2 + 6], %l0 | |
142 | cmp %l0, 0x16 | |
143 | BNE_TEST_FAIL | |
144 | nop | |
145 | byte_os7: | |
146 | ldub [%g2 + 7], %l0 | |
147 | cmp %l0, 0x17 | |
148 | BNE_TEST_FAIL | |
149 | nop | |
150 | byte_os8: | |
151 | ldub [%g2 + 8], %l0 | |
152 | cmp %l0, 0x18 | |
153 | BNE_TEST_FAIL | |
154 | nop | |
155 | byte_os9: | |
156 | ldub [%g2 + 9], %l0 | |
157 | cmp %l0, 0x19 | |
158 | BNE_TEST_FAIL | |
159 | nop | |
160 | byte_os10: | |
161 | ldub [%g2 + 10], %l0 | |
162 | cmp %l0, 0x1a | |
163 | BNE_TEST_FAIL | |
164 | nop | |
165 | byte_os11: | |
166 | ldub [%g2 + 11], %l0 | |
167 | cmp %l0, 0x1b | |
168 | BNE_TEST_FAIL | |
169 | nop | |
170 | byte_os12: | |
171 | ldub [%g2 + 12], %l0 | |
172 | cmp %l0, 0x1c | |
173 | BNE_TEST_FAIL | |
174 | nop | |
175 | byte_os13: | |
176 | ldub [%g2 + 13], %l0 | |
177 | cmp %l0, 0x1d | |
178 | BNE_TEST_FAIL | |
179 | nop | |
180 | byte_os14: | |
181 | ldub [%g2 + 14], %l0 | |
182 | cmp %l0, 0x1e | |
183 | BNE_TEST_FAIL | |
184 | nop | |
185 | byte_os15: | |
186 | ldub [%g2 + 15], %l0 | |
187 | cmp %l0, 0x1f | |
188 | BNE_TEST_FAIL | |
189 | nop | |
190 | ||
191 | ! load half-word, 8 offsets within 16 bytes | |
192 | ||
193 | setx MEM64_RD_ADDR0 + 16, %g1, %g2 | |
194 | halfwd_os0: | |
195 | nop ! $EV trig_pc_d(1, @VA(.MAIN.halfwd_os0)) -> printf("\n halfwd_os0 \n") | |
196 | lduh [%g2 + 0], %l0 | |
197 | setx 0x2021, %g1, %g7 | |
198 | cmp %l0, %g7 | |
199 | BNE_TEST_FAIL | |
200 | nop | |
201 | halfwd_os2: | |
202 | lduh [%g2 + 2], %l0 | |
203 | setx 0x2223, %g1, %g7 | |
204 | cmp %l0, %g7 | |
205 | BNE_TEST_FAIL | |
206 | nop | |
207 | halfwd_os4: | |
208 | lduh [%g2 + 4], %l0 | |
209 | setx 0x2425, %g1, %g7 | |
210 | cmp %l0, %g7 | |
211 | BNE_TEST_FAIL | |
212 | nop | |
213 | halfwd_os6: | |
214 | lduh [%g2 + 6], %l0 | |
215 | setx 0x2627, %g1, %g7 | |
216 | cmp %l0, %g7 | |
217 | BNE_TEST_FAIL | |
218 | nop | |
219 | halfwd_os8: | |
220 | lduh [%g2 + 8], %l0 | |
221 | setx 0x2829, %g1, %g7 | |
222 | cmp %l0, %g7 | |
223 | BNE_TEST_FAIL | |
224 | nop | |
225 | halfwd_os10: | |
226 | lduh [%g2 + 10], %l0 | |
227 | setx 0x2a2b, %g1, %g7 | |
228 | cmp %l0, %g7 | |
229 | BNE_TEST_FAIL | |
230 | nop | |
231 | halfwd_os12: | |
232 | lduh [%g2 + 12], %l0 | |
233 | setx 0x2c2d, %g1, %g7 | |
234 | cmp %l0, %g7 | |
235 | BNE_TEST_FAIL | |
236 | nop | |
237 | halfwd_os14: | |
238 | lduh [%g2 + 14], %l0 | |
239 | setx 0x2e2f, %g1, %g7 | |
240 | cmp %l0, %g7 | |
241 | BNE_TEST_FAIL | |
242 | nop | |
243 | ||
244 | ! Load word, 4 offsets within 16 bytes | |
245 | ||
246 | setx MEM64_RD_ADDR0 + 32, %g1, %g2 | |
247 | fullwd_os0: | |
248 | nop ! $EV trig_pc_d(1, @VA(.MAIN.fullwd_os0)) -> printf("\n fullwd_os0 \n") | |
249 | lduw [%g2 + 0], %l1 | |
250 | setx 0x30313233, %g1, %g4 | |
251 | cmp %l1, %g4 | |
252 | BNE_TEST_FAIL | |
253 | nop | |
254 | fullwd_os4: | |
255 | lduw [%g2 + 4], %l1 | |
256 | setx 0x34353637, %g1, %g4 | |
257 | cmp %l1, %g4 | |
258 | BNE_TEST_FAIL | |
259 | nop | |
260 | fullwd_os8: | |
261 | lduw [%g2 + 8], %l1 | |
262 | setx 0x38393a3b, %g1, %g4 | |
263 | cmp %l1, %g4 | |
264 | BNE_TEST_FAIL | |
265 | nop | |
266 | fullwd_os12: | |
267 | lduw [%g2 + 12], %l1 | |
268 | setx 0x3c3d3e3f, %g1, %g4 | |
269 | cmp %l1, %g4 | |
270 | BNE_TEST_FAIL | |
271 | nop | |
272 | ||
273 | ! Load dword (8 bytes), 2 offsets within 16 bytes | |
274 | ||
275 | setx MEM64_RD_ADDR0 + 48, %g1, %g2 | |
276 | dblwd_os0: | |
277 | nop ! $EV trig_pc_d(1, @VA(.MAIN.dblwd_os0)) -> printf("\n dblwd_os0 \n") | |
278 | ldx [%g2], %l0 | |
279 | setx 0x4041424344454647, %g1, %g4 | |
280 | cmp %l0, %g4 | |
281 | BNE_TEST_FAIL | |
282 | nop | |
283 | dblwd_os8: | |
284 | ldx [%g2 + 8], %l0 | |
285 | setx 0x48494a4b4c4d4e4f, %g1, %g4 | |
286 | cmp %l0, %g4 | |
287 | BNE_TEST_FAIL | |
288 | nop | |
289 | ||
290 | ||
291 | test_passed: | |
292 | EXIT_GOOD | |
293 | ||
294 | test_failed: | |
295 | EXIT_BAD |